Patch "PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support" has been added to the 5.10-stable tree

Hello stable maintainers,

I notice that upstream commit:
2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support")

has been backported (as it should) to:
5.10: https://marc.info/?l=linux-stable-commits&m=170839241818847&w=2 (only queued so far) 5.15: https://lore.kernel.org/stable/[email protected]/

6.1:  https://lore.kernel.org/stable/[email protected]/
6.6:  https://lore.kernel.org/stable/[email protected]/
6.7:  https://lore.kernel.org/stable/[email protected]/

Unfortunately, while this commit fixed a bug, it introduced another bug.

This "another bug" is fixed in upstream commit:
b5d1b4b46f85 ("PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()")

This fix has been backported to:
6.7: https://marc.info/?l=linux-stable-commits&m=170836979506847&w=2 (only queued so far)

But needs to be backported to 5.10, 5.15, 6.1, 6.6, 6.7.

It does not apply without conflicts, so I've attached two backported versions. (There was a minor conflict with the headers.)

backport-all-but-5_10.patch - for 5.15, 6.1, 6.6, 6.7 backport-5_10.patch - for 5.10

Kind regards,
Niklas

From cbc98e30eb470a924d2fd59ae693d5480b3d263d Mon Sep 17 00:00:00 2001
From: Dan Carpenter <[email protected]>
Date: Fri, 26 Jan 2024 11:40:37 +0300
Subject: [PATCH] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit b5d1b4b46f856da1473c7ba9a5cdfcb55c9b2478 upstream.

The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does:

  msg_addr &= ~aligned_offset;

it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do the alignment instead.

---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index 61a0f33c59cf..fcb1fdb22ffb 100644
@@ -6,6 +6,7 @@
  * Author: Kishon Vijay Abraham I <[email protected]>
  */
 
+#include <linux/align.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 

@@ -589,7 +590,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 	}
 
 	aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
-	msg_addr &= ~aligned_offset;
+	msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
 	ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr,
 				  epc->mem->window.page_size);
 	if (ret)

2.43.2

From 7ff5da5719c4d2ef67b89cdc9784bd8361b4b514 Mon Sep 17 00:00:00 2001
From: Dan Carpenter <[email protected]>
Date: Fri, 26 Jan 2024 11:40:37 +0300
Subject: [PATCH] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit b5d1b4b46f856da1473c7ba9a5cdfcb55c9b2478 upstream.

The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does:

  msg_addr &= ~aligned_offset;

it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do the alignment instead.

---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index e27bac623684..8b7ec0d9e90d 100644
@@ -6,6 +6,7 @@
  * Author: Kishon Vijay Abraham I <[email protected]>
  */
 
+#include <linux/align.h>
 #include <linux/of.h>
 
 #include "pcie-designware.h"

@@ -593,7 +594,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 	}
 
 	aligned_offset = msg_addr & (epc->mem->window.page_size - 1);
-	msg_addr &= ~aligned_offset;
+	msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size);
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,  msg_addr,
 				  epc->mem->window.page_size);
 	if (ret)

2.43.2

For some reason this was applied to 5.10.y, but not the other branches, our fault!

The other one is now queued up, thanks.

greg k-h