net/ena: v2.9.0 driver release
Subsystems (2)
cover net/ena: v2.9.0 driver release
From: Shai Brandes <[email protected]>
Hi all, the ena v2.9.0 release introduces:
1. HAL upgrade:
- renamed the 'base' folder to be 'hal'
- separated the HAL patches instead of a bulk update.
2. Restructured ena stats and metrics.
3. Restructured the LLQ configuration:
- configurable via devarg.
- support device recommendation.
- restructure the logic in driver.
4. Added support for the admin queue to work only in poll-mode
- configurable via devarg.
- allows to bind ports to uio_pci_generic kernel driver.
5. Reworked the device close to exhaust interrupt callbacks and alarms.
6. Fixed a bug in fast mbuf free.
Best regards,
Shai
Shai Brandes (33):
net/ena: rework the metrics multi-process functions net/ena: report new supported link speed capabilities net/ena: update imissed stat with Rx overruns net/ena: sub-optimal configuration notifications support net/ena: fix fast mbuf free
net/ena: rename base folder to hal
net/ena: restructure the llq policy setting process net/ena/hal: exponential backoff exp limit net/ena/hal: add a new csum offload bit net/ena/hal: added a bus parameter to ena memcpy macro net/ena/hal: optimize Rx ring submission queue net/ena/hal: rename fields in completion descriptors net/ena/hal: use correct read once on u8 field net/ena/hal: add completion descriptor corruption check net/ena/hal: malformed Tx descriptor error reason net/ena/hal: phc feature modifications net/ena/hal: restructure interrupt handling net/ena/hal: add unlikely to error checks net/ena/hal: missing admin interrupt reset reason net/ena/hal: check for existing keep alive notification net/ena/hal: modify memory barrier comment net/ena/hal: rework Rx ring submission queue net/ena/hal: remove operating system type enum net/ena/hal: handle command abort
net/ena/hal: add support for device reset request net/ena: cosmetic changes
net/ena/hal: modify customer metrics memory management net/ena/hal: cosmetic changes
net/ena: update device-preferred size of rings net/ena: exhaust interrupt callbacks in device close net/ena: support max large llq depth from the device net/ena: control path pure polling mode net/ena: upgrade driver version to 2.9.0
doc/guides/nics/ena.rst | 58 ++--
doc/guides/rel_notes/release_24_03.rst | 11 +
drivers/net/ena/ena_ethdev.c | 316 ++++++++++++------
drivers/net/ena/ena_ethdev.h | 17 +-
drivers/net/ena/{base => hal}/ena_com.c | 240 +++++++++----
drivers/net/ena/{base => hal}/ena_com.h | 53 ++-
.../{base => hal}/ena_defs/ena_admin_defs.h | 92 +++--
.../{base => hal}/ena_defs/ena_common_defs.h | 0
.../{base => hal}/ena_defs/ena_eth_io_defs.h | 49 ++-
.../ena/{base => hal}/ena_defs/ena_gen_info.h | 0
.../ena/{base => hal}/ena_defs/ena_includes.h | 0
.../{base => hal}/ena_defs/ena_regs_defs.h | 3 +
drivers/net/ena/{base => hal}/ena_eth_com.c | 56 ++--
drivers/net/ena/{base => hal}/ena_eth_com.h | 14 +-
drivers/net/ena/{base => hal}/ena_plat.h | 0
drivers/net/ena/{base => hal}/ena_plat_dpdk.h | 9 +-
drivers/net/ena/meson.build | 6 +-
17 files changed, 666 insertions(+), 258 deletions(-)
rename drivers/net/ena/{base => hal}/ena_com.c (94%)
rename drivers/net/ena/{base => hal}/ena_com.h (96%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_admin_defs.h (96%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_common_defs.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_eth_io_defs.h (95%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_gen_info.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_includes.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_regs_defs.h (97%)
rename drivers/net/ena/{base => hal}/ena_eth_com.c (93%)
rename drivers/net/ena/{base => hal}/ena_eth_com.h (94%)
rename drivers/net/ena/{base => hal}/ena_plat.h (100%)
rename drivers/net/ena/{base => hal}/ena_plat_dpdk.h (97%)Signature · 1 line
2.17.1
PATCH 1/33 net/ena: rework the metrics multi-process functions
From: Shai Brandes <[email protected]>
1. Changed the rte_memcpy call to use the precomputed buf_size.
2. Removed redundant address operators (ampersand symbol) when providing memcpy source address parameter.
3. Code style related change.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/ena_ethdev.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
drivers/net/ena/ena_ethdev.c +5 -6
@@ -531,8 +531,8 @@ __extension__ ({ __extension__ ({ENA_TOUCH (rsp);ENA_TOUCH (ena_dev); -if (stats != (struct ena_admin_eni_stats *)&adapter->metrics_stats) -rte_memcpy (stats, &adapter->metrics_stats,sizeof (*stats)); +if (stats != (struct ena_admin_eni_stats *)adapter->metrics_stats) +rte_memcpy (stats, adapter->metrics_stats,sizeof (*stats)); }), struct ena_com_dev *ena_dev, struct ena_admin_eni_stats *stats);
@@ -590,9 +590,8 @@ __extension__ ({ __extension__ ({ENA_TOUCH (rsp);ENA_TOUCH (ena_dev); -ENA_TOUCH (buf_size); -if (buf != (char *)&adapter->metrics_stats) -rte_memcpy (buf, &adapter->metrics_stats, adapter->metrics_num *sizeof (uint64_t )); +if (buf != (char *)adapter->metrics_stats) +rte_memcpy (buf, adapter->metrics_stats, buf_size); }), struct ena_com_dev *ena_dev, char *buf, size_t buf_size);
@@ -4088,7 +4087,7 @@ ena_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer)case ENA_MP_CUSTOMER_METRICS_GET : res =ena_com_get_customer_metrics (ena_dev, (char *)adapter->metrics_stats, -sizeof (uint64_t ) * adapter->metrics_num); + adapter->metrics_num *sizeof (uint64_t ));break ;case ENA_MP_SRD_STATS_GET : res = ena_com_get_ena_srd_info(ena_dev,
Signature · 1 line
2.17.1
PATCH 2/33 net/ena: report new supported link speed capabilities
In reply to [email protected]From: Shai Brandes <[email protected]>
Updated the rte_eth_dev_info device supported speed bitmap to include 200Gbps and 400Gbps capabilities.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/ena_ethdev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
drivers/net/ena/ena_ethdev.c +3 -1
@@ -2542,7 +2542,9 @@ static int ena_infos_get(struct rte_eth_dev *dev,RTE_ETH_LINK_SPEED_25G |RTE_ETH_LINK_SPEED_40G |RTE_ETH_LINK_SPEED_50G | -RTE_ETH_LINK_SPEED_100G ; +RTE_ETH_LINK_SPEED_100G | +RTE_ETH_LINK_SPEED_200G | +RTE_ETH_LINK_SPEED_400G ;/* Inform framework about available features */ dev_info->rx_offload_capa =ena_get_rx_port_offloads (adapter);
Signature · 1 line
2.17.1
PATCH 3/33 net/ena: update imissed stat with Rx overruns
In reply to [email protected]From: Shai Brandes <[email protected]>
Depending on its acceleration support, the device updates a different statistic when an ingress packet is dropped because no buffers are available to hold it.
- In AWS instance types from later generations 'rx_overruns' is updated.
- Otherwise, in legacy instance types, 'rx_dropped_cnt' is updated.
That is, there is no need to report rx_overruns separately as an xstat and the driver can simply sum up the two self-contained counters as the 'imissed' statistic.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/rel_notes/release_24_03.rst | 4 ++++ drivers/net/ena/ena_ethdev.c | 8 +++++--- drivers/net/ena/ena_ethdev.h | 1 - 3 files changed, 9 insertions(+), 4 deletions(-)
doc/guides/rel_notes/release_24_03.rst +4 -0
@@ -101,6 +101,10 @@ New Features * ``rte_flow_template_table_resize_complete()``. Complete table resize. +* **Updated Amazon ena (Elastic Network Adapter) net driver.** + + * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. + * **Updated Atomic Rules' Arkville driver.** * Added support for Atomic Rules' TK242 packet-capture family of devices
drivers/net/ena/ena_ethdev.c +5 -3
@@ -93,7 +93,6 @@ static const struct ena_stats ena_stats_global_strings[] = {ENA_STAT_GLOBAL_ENTRY (dev_start),ENA_STAT_GLOBAL_ENTRY (dev_stop), ENA_STAT_GLOBAL_ENTRY(tx_drops), - ENA_STAT_GLOBAL_ENTRY(rx_overruns), };/*
@@ -4014,9 +4013,12 @@ static void ena_keep_alive(void *adapter_data, tx_drops = ((uint64_t )desc->tx_drops_high <<32 ) | desc->tx_drops_low; rx_overruns = ((uint64_t )desc->rx_overruns_high <<32 ) | desc->rx_overruns_low; - adapter->drv_stats->rx_drops = rx_drops; +/* +* Depending on its acceleration support, the device updates a different statistic when +* Rx packet is dropped because there are no available buffers to accommodate it. +*/ + adapter->drv_stats->rx_drops = rx_drops + rx_overruns; adapter->dev_stats.tx_drops = tx_drops; - adapter->dev_stats.rx_overruns = rx_overruns; }/**
drivers/net/ena/ena_ethdev.h +0 -1
@@ -219,7 +219,6 @@ struct ena_stats_dev {* As a workaround it is being published as an extended statistic. */ u64 tx_drops; -u64 rx_overruns; };struct ena_stats_metrics {
Signature · 1 line
2.17.1
PATCH 4/33 net/ena: sub-optimal configuration notifications support
In reply to [email protected]From: Shai Brandes <[email protected]>
ENA device will send asynchronous notifications to the driver in order to notify users about sub-optimal configurations and refer them to public AWS documentation for further action.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/rel_notes/release_24_03.rst | 1 + .../net/ena/base/ena_defs/ena_admin_defs.h | 11 +++++++- drivers/net/ena/ena_ethdev.c | 26 +++++++++++++++++-- 3 files changed, 35 insertions(+), 3 deletions(-)
doc/guides/rel_notes/release_24_03.rst +1 -0
@@ -104,6 +104,7 @@ New Features * **Updated Amazon ena (Elastic Network Adapter) net driver.** * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. + * Added support for sub-optimal configuration notifications from the device. * **Updated Atomic Rules' Arkville driver.**
drivers/net/ena/base/ena_defs/ena_admin_defs.h +10 -1
@@ -1214,7 +1214,8 @@ enum ena_admin_aenq_group {ENA_ADMIN_NOTIFICATION =3 ,ENA_ADMIN_KEEP_ALIVE =4 ,ENA_ADMIN_REFRESH_CAPABILITIES =5 , - ENA_ADMIN_AENQ_GROUPS_NUM = 6, +ENA_ADMIN_CONF_NOTIFICATIONS =6 , + ENA_ADMIN_AENQ_GROUPS_NUM = 7, }; enum ena_admin_aenq_notification_syndrome {
@@ -1251,6 +1252,14 @@ struct ena_admin_aenq_keep_alive_desc {uint32_t rx_overruns_high; }; +struct ena_admin_aenq_conf_notifications_desc { +struct ena_admin_aenq_common_desc aenq_common_desc; + +uint64_t notifications_bitmap; + +uint64_t reserved; +}; +struct ena_admin_ena_mmio_req_read_less_resp {uint16_t req_id;
drivers/net/ena/ena_ethdev.c +24 -2
@@ -36,6 +36,10 @@#define ENA_MIN_RING_DESC 128 +#define BITS_PER_BYTE 8 + +#define BITS_PER_TYPE (type) (sizeof(type) * BITS_PER_BYTE) +/* * We should try to keep ENA_CLEANUP_BUF_SIZE lower than * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache.
@@ -1842,7 +1846,8 @@ static int ena_device_init(struct ena_adapter *adapter,BIT (ENA_ADMIN_NOTIFICATION ) |BIT (ENA_ADMIN_KEEP_ALIVE ) |BIT (ENA_ADMIN_FATAL_ERROR ) | -BIT (ENA_ADMIN_WARNING ); +BIT (ENA_ADMIN_WARNING ) | +BIT (ENA_ADMIN_CONF_NOTIFICATIONS ); aenq_groups &= get_feat_ctx->aenq.supported_groups;
@@ -4021,6 +4026,22 @@ static void ena_keep_alive(void *adapter_data, adapter->dev_stats.tx_drops = tx_drops; } +static void ena_suboptimal_configuration(__rte_unused void *adapter_data, +struct ena_admin_aenq_entry *aenq_e) +{ +struct ena_admin_aenq_conf_notifications_desc *desc; +int bit, num_bits; + + desc = (struct ena_admin_aenq_conf_notifications_desc *)aenq_e; + num_bits =BITS_PER_TYPE (desc->notifications_bitmap); +for (bit =0 ; bit < num_bits; bit++) { +if (desc->notifications_bitmap &RTE_BIT64 (bit)) { +PMD_DRV_LOG (WARNING , +"Sub-optimal configuration notification code: %d\n" , bit +1 ); + } + } +} +/** * This handler will called for unknown event group or unimplemented handlers **/
@@ -4035,7 +4056,8 @@ static struct ena_aenq_handlers aenq_handlers = { .handlers = { [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, [ENA_ADMIN_NOTIFICATION] = ena_notification, - [ENA_ADMIN_KEEP_ALIVE ] = ena_keep_alive + [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive, + [ENA_ADMIN_CONF_NOTIFICATIONS ] = ena_suboptimal_configuration }, .unimplemented_handler = unimplemented_aenq_handler };
Signature · 1 line
2.17.1
PATCH 5/33 net/ena: fix fast mbuf free
In reply to [email protected]From: Shai Brandes <[email protected]>
In case the application enables fast mbuf release optimization, the driver releases 256 TX mbufs in bulk upon reaching the TX free threshold.
The existing implementation utilizes rte_mempool_put_bulk for bulk freeing TXs, which exclusively supports direct mbufs.
In case the application transmits indirect bufs, the driver must also decrement the mbuf reference count and unlink the mbuf segment. For such case, the driver should employ rte_pktmbuf_free_bulk.
Fixes c339f53823f3 ("net/ena: support fast mbuf free")
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/ena/ena_ethdev.c | 6 ++---- 2 files changed, 3 insertions(+), 4 deletions(-)
doc/guides/rel_notes/release_24_03.rst +1 -0
@@ -105,6 +105,7 @@ New Features * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. * Added support for sub-optimal configuration notifications from the device. + * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. * **Updated Atomic Rules' Arkville driver.**
drivers/net/ena/ena_ethdev.c +2 -4
@@ -3122,8 +3122,7 @@ ena_tx_cleanup_mbuf_fast(struct rte_mbuf **mbufs_to_clean, m_next = mbuf->next; mbufs_to_clean[mbuf_cnt++] = mbuf;if (mbuf_cnt == buf_size) { -rte_mempool_put_bulk (mbufs_to_clean[0 ]->pool, (void **)mbufs_to_clean, - (unsigned int )mbuf_cnt); +rte_pktmbuf_free_bulk (mbufs_to_clean, mbuf_cnt); mbuf_cnt =0 ; } mbuf = m_next;
@@ -3191,8 +3190,7 @@ static int ena_tx_cleanup(void *txp, uint32_t free_pkt_cnt) }if (mbuf_cnt !=0 ) -rte_mempool_put_bulk (mbufs_to_clean[0 ]->pool, - (void **)mbufs_to_clean, mbuf_cnt); +rte_pktmbuf_free_bulk (mbufs_to_clean, mbuf_cnt);/* Notify completion handler that full cleanup was performed */ if (free_pkt_cnt ==0 || total_tx_pkts < cleanup_budget)
Signature · 1 line
2.17.1
PATCH 6/33 net/ena: rename base folder to hal
In reply to [email protected]From: Shai Brandes <[email protected]>
Changed the base HAL folder to hal.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
---
drivers/net/ena/{base => hal}/ena_com.c | 0
drivers/net/ena/{base => hal}/ena_com.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_admin_defs.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_common_defs.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_eth_io_defs.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_gen_info.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_includes.h | 0
drivers/net/ena/{base => hal}/ena_defs/ena_regs_defs.h | 0
drivers/net/ena/{base => hal}/ena_eth_com.c | 0
drivers/net/ena/{base => hal}/ena_eth_com.h | 0
drivers/net/ena/{base => hal}/ena_plat.h | 0
drivers/net/ena/{base => hal}/ena_plat_dpdk.h | 0
drivers/net/ena/meson.build | 6 +++---
13 files changed, 3 insertions(+), 3 deletions(-)
rename drivers/net/ena/{base => hal}/ena_com.c (100%)
rename drivers/net/ena/{base => hal}/ena_com.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_admin_defs.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_common_defs.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_eth_io_defs.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_gen_info.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_includes.h (100%)
rename drivers/net/ena/{base => hal}/ena_defs/ena_regs_defs.h (100%)
rename drivers/net/ena/{base => hal}/ena_eth_com.c (100%)
rename drivers/net/ena/{base => hal}/ena_eth_com.h (100%)
rename drivers/net/ena/{base => hal}/ena_plat.h (100%)
rename drivers/net/ena/{base => hal}/ena_plat_dpdk.h (100%)drivers/net/ena/hal/ena_com.c renamed from drivers/net/ena/base/ena_com.c +0 -0
drivers/net/ena/hal/ena_com.h renamed from drivers/net/ena/base/ena_com.h +0 -0
drivers/net/ena/hal/ena_defs/ena_admin_defs.h renamed from drivers/net/ena/base/ena_defs/ena_admin_defs.h +0 -0
drivers/net/ena/hal/ena_defs/ena_common_defs.h renamed from drivers/net/ena/base/ena_defs/ena_common_defs.h +0 -0
drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h renamed from drivers/net/ena/base/ena_defs/ena_eth_io_defs.h +0 -0
drivers/net/ena/hal/ena_defs/ena_gen_info.h renamed from drivers/net/ena/base/ena_defs/ena_gen_info.h +0 -0
drivers/net/ena/hal/ena_defs/ena_includes.h renamed from drivers/net/ena/base/ena_defs/ena_includes.h +0 -0
drivers/net/ena/hal/ena_defs/ena_regs_defs.h renamed from drivers/net/ena/base/ena_defs/ena_regs_defs.h +0 -0
drivers/net/ena/hal/ena_eth_com.c renamed from drivers/net/ena/base/ena_eth_com.c +0 -0
drivers/net/ena/hal/ena_eth_com.h renamed from drivers/net/ena/base/ena_eth_com.h +0 -0
drivers/net/ena/hal/ena_plat.h renamed from drivers/net/ena/base/ena_plat.h +0 -0
drivers/net/ena/hal/ena_plat_dpdk.h renamed from drivers/net/ena/base/ena_plat_dpdk.h +0 -0
drivers/net/ena/meson.build +3 -3
@@ -10,10 +10,10 @@ endif sources = files( 'ena_ethdev.c', 'ena_rss.c', - 'base/ena_com.c', - 'base/ena_eth_com.c', + 'hal/ena_com.c', + 'hal/ena_eth_com.c', ) deps += ['timer'] -includes += include_directories('base', 'base/ena_defs') +includes += include_directories('hal', 'hal/ena_defs')
Signature · 1 line
2.17.1
PATCH 7/33 net/ena: restructure the llq policy setting process
In reply to [email protected]From: Shai Brandes <[email protected]>
The driver will set the size of the LLQ header size according to the recommendation from the device.
Replaced enable_llq and large_llq_hdr devargs with
a new devarg llq_policy that accepts the following values:
0 - Disable LLQ.
Use with extreme caution as it leads to a huge performance degradation on AWS instances from 6th generation onwards.
1 - Accept device recommended LLQ policy (Default).
Device can recommend normal or large LLQ policy.
2 - Enforce normal LLQ policy.
3 - Enforce large LLQ policy.
Required for packets with header that exceed 96 bytes on AWS instances prior to 5th generation.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/nics/ena.rst | 21 ++--- doc/guides/rel_notes/release_24_03.rst | 1 + drivers/net/ena/ena_ethdev.c | 110 +++++++++++++------------ drivers/net/ena/ena_ethdev.h | 11 ++- 4 files changed, 77 insertions(+), 66 deletions(-)
doc/guides/nics/ena.rst +8 -13
@@ -107,11 +107,15 @@ Configuration Runtime Configuration ^^^^^^^^^^^^^^^^^^^^^ - * **large_llq_hdr** (default 0) + * **llq_policy** (default 1) - Enables or disables usage of large LLQ headers. This option will have - effect only if the device also supports large LLQ headers. Otherwise, the - default value will be used. + Controls whether use device recommended header policy or override it. + 0 - Disable LLQ. + **Use with extreme caution as it leads to a huge performance + degradation on AWS instances from 6th generation onwards.** + 1 - Accept device recommended LLQ policy (Default). + 2 - Enforce normal LLQ policy. + 3 - Enforce large LLQ policy. * **miss_txc_to** (default 5)
@@ -122,15 +126,6 @@ Runtime Configuration timer service. Setting this parameter to 0 disables this feature. Maximum allowed value is 60 seconds. - * **enable_llq** (default 1) - - Determines whenever the driver should use the LLQ (if it's available) or - not. - - **NOTE: On the 6th generation AWS instances disabling LLQ may lead to a - huge performance degradation. In general disabling LLQ is highly not - recommended!** - ENA Configuration Parameters ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
doc/guides/rel_notes/release_24_03.rst +1 -0
@@ -106,6 +106,7 @@ New Features * Removed the reporting of `rx_overruns` errors from xstats and instead updated `imissed` stat with its value. * Added support for sub-optimal configuration notifications from the device. * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. + * Replaced `enable_llq` and `large_llq_hdr` devargs with a new devarg `llq_policy`. * **Updated Atomic Rules' Arkville driver.**
drivers/net/ena/ena_ethdev.c +59 -51
224 lines not on this page · raw message
drivers/net/ena/ena_ethdev.h +9 -2
@@ -85,6 +85,14 @@ enum ena_ring_type { ENA_RING_TYPE_TX = 2, }; +typedef enum ena_llq_policy_t { +ENA_LLQ_POLICY_DISABLED =0 ,/* Host queues */ +ENA_LLQ_POLICY_RECOMMENDED =1 ,/* Device recommendation */ +ENA_LLQ_POLICY_NORMAL =2 ,/* 128B long LLQ entry */ +ENA_LLQ_POLICY_LARGE =3 ,/* 256B long LLQ entry */ +ENA_LLQ_POLICY_LAST , +}ena_llq_policy ; +struct ena_tx_buffer {struct rte_mbuf *mbuf;unsigned int tx_descs;
@@ -329,8 +337,7 @@ struct ena_adapter {bool trigger_reset; -bool enable_llq; -bool use_large_llq_hdr; +ena_llq_policy llq_header_policy;uint32_t last_tx_comp_qid;uint64_t missing_tx_completion_to;
Signature · 1 line
2.17.1
PATCH 8/33 net/ena/hal: exponential backoff exp limit
In reply to [email protected]From: Shai Brandes <[email protected]>
limits the exponent in the exponential backoff mechanism in order to avoid the value overflowing.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/net/ena/hal/ena_com.c +4 -1
@@ -34,6 +34,8 @@#define ENA_REGS_ADMIN_INTR_MASK 1 +#define ENA_MAX_BACKOFF_DELAY_EXP 16U +#define ENA_MIN_ADMIN_POLL_US 100#define ENA_MAX_ADMIN_POLL_US 5000
@@ -545,8 +547,9 @@ static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue,static void ena_delay_exponential_backoff_us (u32 exp,u32 delay_us) { + exp =ENA_MIN32 (ENA_MAX_BACKOFF_DELAY_EXP , exp); delay_us =ENA_MAX32 (ENA_MIN_ADMIN_POLL_US , delay_us); - delay_us =ENA_MIN32 (delay_us * (1U << exp),ENA_MAX_ADMIN_POLL_US ); + delay_us =ENA_MIN32 (ENA_MAX_ADMIN_POLL_US , delay_us * (1U << exp));ENA_USLEEP (delay_us); }
Signature · 1 line
2.17.1
PATCH 9/33 net/ena/hal: add a new csum offload bit
In reply to [email protected]From: Shai Brandes <[email protected]>
Add a new driver supported feature bit for TX IPv6 checksum offload.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +18 -1
@@ -985,7 +985,8 @@ struct ena_admin_host_info {* 4 : rss_configurable_function_key * 5 : reserved * 6 : rx_page_reuse -* 31:7 : reserved +* 7 : tx_ipv6_csum_offload +* 31:8 : reserved */ uint32_t driver_supported_features; };
@@ -1377,6 +1378,8 @@ struct ena_admin_phc_resp {#define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6#define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) +#define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7 +#define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7)/* feature_rss_ind_table */ #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
@@ -1851,6 +1854,20 @@ static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_iENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK ; } +static inline +uint32_t get_ena_admin_host_info_tx_ipv6_csum_offload (const struct ena_admin_host_info *p) +{ +return (p->driver_supported_features &ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK ) >> +ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT ; +} + +static inline void set_ena_admin_host_info_tx_ipv6_csum_offload (struct ena_admin_host_info *p, +uint32_t val) +{ + p->driver_supported_features |= (val <<ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT ) & +ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK ; +} +static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update (const struct ena_admin_feature_rss_ind_table *p) {return p->flags &ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK ;
Signature · 1 line
2.17.1
PATCH 10/33 net/ena/hal: added a bus parameter to ena memcpy macro
In reply to [email protected]From: Shai Brandes <[email protected]>
ENA_MEMCPY_TO_DEVICE_64 macro needs pci bus id in order to write to the device memory when using llq.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.c | 3 ++- drivers/net/ena/hal/ena_plat_dpdk.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-)
drivers/net/ena/hal/ena_eth_com.c +2 -1
@@ -74,7 +74,8 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq,wmb ();/* The line is completed. Copy it to dev */ -ENA_MEMCPY_TO_DEVICE_64 (io_sq->desc_addr.pbuf_dev_addr + dst_offset, +ENA_MEMCPY_TO_DEVICE_64 (io_sq->bus, + io_sq->desc_addr.pbuf_dev_addr + dst_offset, bounce_buffer, llq_info->desc_list_entry_size);
drivers/net/ena/hal/ena_plat_dpdk.h +2 -1
@@ -301,11 +301,12 @@ ena_mem_alloc_coherent(struct rte_eth_dev_data *data, size_t size,#define ENA_WAIT_EVENTS_DESTROY (admin_queue) ((void)(admin_queue))/* The size must be 8 byte align */ -#define ENA_MEMCPY_TO_DEVICE_64 (dst, src, size) \ +#define ENA_MEMCPY_TO_DEVICE_64 (bus, dst, src, size) \ do { \ int count, i; \ uint64_t *to = (uint64_t *)(dst); \ const uint64_t *from = (const uint64_t *)(src); \ + (void)(bus); \ count = (size) / 8; \ for (i = 0; i < count; i++, from++, to++) \ rte_write64_relaxed(*from, to); \
Signature · 1 line
2.17.1
PATCH 11/33 net/ena/hal: optimize Rx ring submission queue
In reply to [email protected]From: Shai Brandes <[email protected]>
RX ring submission queue descriptors are always located in host memory This optimization replaces the generic descriptor retrieval method with a tailored method for host memory type descriptors to avoid unnecessary if statement.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
drivers/net/ena/hal/ena_eth_com.c +2 -3
@@ -631,9 +631,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,if (unlikely (!ena_com_sq_have_enough_space (io_sq,1 )))return ENA_COM_NO_SPACE ; - desc =get_sq_desc (io_sq); -if (unlikely (!desc)) -return ENA_COM_FAULT ; +/* virt_addr allocation success is checked before calling this function */ + desc =get_sq_desc_regular_queue (io_sq);memset (desc,0x0 ,sizeof (struct ena_eth_io_rx_desc ));
Signature · 1 line
2.17.1
PATCH 12/33 net/ena/hal: rename fields in completion descriptors
In reply to [email protected]From: Shai Brandes <[email protected]>
Several reserved bits in ena_eth_io_tx_cdesc and ena_eth_io_rx_cdesc_base have been renamed explicitly to MBZ (Must Be Zero).
These bits are set by the device to zero before being sent to the driver. The fields are used as an integrity check in order to ensure that the received descriptor is not corrupted.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 1 + .../net/ena/hal/ena_defs/ena_eth_io_defs.h | 49 +++++++++++++++++-- 2 files changed, 47 insertions(+), 3 deletions(-)
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +1 -0
@@ -84,6 +84,7 @@ enum ena_admin_aq_caps_id {ENA_ADMIN_ENA_SRD_INFO =1 ,ENA_ADMIN_CUSTOMER_METRICS =2 ,ENA_ADMIN_EXTENDED_RESET_REASONS =3 , + ENA_ADMIN_CDESC_MBZ = 4, }; enum ena_admin_placement_policy_type {
drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h +46 -3
103 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH 13/33 net/ena/hal: use correct read once on u8 field
In reply to [email protected]From: Shai Brandes <[email protected]>
The flags field in ena_eth_io_tx_cdesc is 8-bits long. The current macro used is READ_ONCE16.
Switching to READ_ONCE8 to avoid reading extra data. Given that there's an implicit cast to u8 in the assignment, the correct value is being read, but this change makes it even more accurate.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/net/ena/hal/ena_eth_com.h +1 -1
@@ -219,7 +219,7 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq,* expected, it mean that the device still didn't update * this completion. */ - cdesc_phase =READ_ONCE16 (cdesc->flags) &ENA_ETH_IO_TX_CDESC_PHASE_MASK ; + cdesc_phase =READ_ONCE8 (cdesc->flags) &ENA_ETH_IO_TX_CDESC_PHASE_MASK ;if (cdesc_phase != expected_phase)return ENA_COM_TRY_AGAIN ;
Signature · 1 line
2.17.1
PATCH 14/33 net/ena/hal: add completion descriptor corruption check
In reply to [email protected]From: Shai Brandes <[email protected]>
Adding a check of the MBZ (Must Be Zero) fields in the incoming tx and rx completion descriptors in order to identify corrupted descriptors.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.c | 13 +++++++++++-- drivers/net/ena/hal/ena_eth_com.h | 14 +++++++++++++- 2 files changed, 24 insertions(+), 3 deletions(-)
drivers/net/ena/hal/ena_eth_com.c +11 -2
@@ -237,6 +237,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, u16 *first_cdesc_idx, u16 *num_descs) { +struct ena_com_dev *dev =ena_com_io_cq_to_ena_dev (io_cq);u16 count = io_cq->cur_rx_pkt_cdesc_count, head_masked;struct ena_eth_io_rx_cdesc_base *cdesc;u32 last =0 ;
@@ -252,13 +253,21 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,ena_com_cq_inc_head (io_cq);if (unlikely ((status &ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK ) >>ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count !=0 )) { -struct ena_com_dev *dev =ena_com_io_cq_to_ena_dev (io_cq); -ena_trc_err (dev,"First bit is on in descriptor #%d on q_id: %d, req_id: %u\n" , count, io_cq->qid, cdesc->req_id);return ENA_COM_FAULT ; } + +if (unlikely ((status & (ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK | +ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK )) && +ena_com_get_cap (dev,ENA_ADMIN_CDESC_MBZ ))) { +ena_trc_err (dev, +"Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n" , + count, io_cq->qid, cdesc->req_id); +return ENA_COM_FAULT ; + } + count++; last = (status &ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK ) >>ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT ;
drivers/net/ena/hal/ena_eth_com.h +13 -1
@@ -204,9 +204,11 @@ static inline void ena_com_cq_inc_head(struct ena_com_io_cq *io_cq)static inline int ena_com_tx_comp_req_id_get (struct ena_com_io_cq *io_cq,u16 *req_id) { +struct ena_com_dev *dev =ena_com_io_cq_to_ena_dev (io_cq);u8 expected_phase, cdesc_phase;struct ena_eth_io_tx_cdesc *cdesc;u16 masked_head; +u8 flags; masked_head = io_cq->head & (io_cq->q_depth -1 ); expected_phase = io_cq->phase;
@@ -215,14 +217,24 @@ static inline int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, ((uintptr_t )io_cq->cdesc_addr.virt_addr + (masked_head * io_cq->cdesc_entry_size_in_bytes)); + flags =READ_ONCE8 (cdesc->flags); +/* When the current completion descriptor phase isn't the same as the * expected, it mean that the device still didn't update * this completion. */ - cdesc_phase =READ_ONCE8 (cdesc->flags) &ENA_ETH_IO_TX_CDESC_PHASE_MASK ; + cdesc_phase = flags &ENA_ETH_IO_TX_CDESC_PHASE_MASK ;if (cdesc_phase != expected_phase)return ENA_COM_TRY_AGAIN ; +if (unlikely ((flags &ENA_ETH_IO_TX_CDESC_MBZ6_MASK ) && +ena_com_get_cap (dev,ENA_ADMIN_CDESC_MBZ ))) { +ena_trc_err (dev, +"Corrupted TX descriptor on q_id: %d, req_id: %u\n" , + io_cq->qid, cdesc->req_id); +return ENA_COM_FAULT ; + } +dma_rmb (); *req_id =READ_ONCE16 (cdesc->req_id);
Signature · 1 line
2.17.1
PATCH 15/33 net/ena/hal: malformed Tx descriptor error reason
In reply to [email protected]From: Shai Brandes <[email protected]>
Adding ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED to identify cases where the returned TX completion descriptors are corrupted.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_defs/ena_regs_defs.h | 1 + 1 file changed, 1 insertion(+)
drivers/net/ena/hal/ena_defs/ena_regs_defs.h +1 -0
@@ -23,6 +23,7 @@ enum ena_regs_reset_reason_types {ENA_REGS_RESET_MISS_INTERRUPT =14 ,ENA_REGS_RESET_SUSPECTED_POLL_STARVATION =15 ,ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED =16 , +ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED =17 , ENA_REGS_RESET_LAST, };
Signature · 1 line
2.17.1
PATCH 16/33 net/ena/hal: phc feature modifications
In reply to [email protected]From: Shai Brandes <[email protected]>
1. PHC algorithm is updated to support reading new PHC values.
2. Update default PHC expiration timeout.
3. Fix a theoretical PHC destroy race.
4. Adjust PHC for multiple devices.
5. PHC activation version check point.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 111 ++++++++++++------ drivers/net/ena/hal/ena_com.h | 31 +++-- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 45 +++++-- 3 files changed, 135 insertions(+), 52 deletions(-)
drivers/net/ena/hal/ena_com.c +75 -36
@@ -41,10 +41,12 @@#define ENA_MAX_ADMIN_POLL_US 5000/* PHC definitions */ -#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 20 +#define ENA_PHC_DEFAULT_EXPIRE_TIMEOUT_USEC 10#define ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC 1000 -#define ENA_PHC_TIMESTAMP_ERROR 0xFFFFFFFFFFFFFFFF +#define ENA_PHC_MAX_ERROR_BOUND 0xFFFFFFFF#define ENA_PHC_REQ_ID_OFFSET 0xDEAD +#define ENA_PHC_ERROR_FLAGS (ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP | \ + ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND)/*****************************************************************************/ /*****************************************************************************/
@@ -1778,16 +1780,21 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)struct ena_admin_set_feat_cmd set_feat_cmd;int ret =0 ; -/* Get device PHC default configuration */ - ret =ena_com_get_feature (ena_dev, &get_feat_resp,ENA_ADMIN_PHC_CONFIG ,0 ); +/* Get default device PHC configuration */ + ret =ena_com_get_feature (ena_dev, + &get_feat_resp, +ENA_ADMIN_PHC_CONFIG , +ENA_ADMIN_PHC_FEATURE_VERSION_0 );if (unlikely (ret)) {ena_trc_err (ena_dev,"Failed to get PHC feature configuration, error: %d\n" , ret);return ret; } -/* Supporting only readless PHC retrieval */ -if (get_feat_resp.u.phc.type !=ENA_ADMIN_PHC_TYPE_READLESS ) { -ena_trc_err (ena_dev,"Unsupported PHC type, error: %d\n" ,ENA_COM_UNSUPPORTED ); +/* Supporting only PHC V0 (readless mode with error bound) */ +if (get_feat_resp.u.phc.version !=ENA_ADMIN_PHC_FEATURE_VERSION_0 ) { +ena_trc_err (ena_dev,"Unsupprted PHC version (0x%X), error: %d\n" , + get_feat_resp.u.phc.version, +ENA_COM_UNSUPPORTED );return ENA_COM_UNSUPPORTED ; }
@@ -1804,11 +1811,11 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev) get_feat_resp.u.phc.block_timeout_usec :ENA_PHC_DEFAULT_BLOCK_TIMEOUT_USEC ; -/* Sanity check - expire timeout must not be above skip timeout */ +/* Sanity check - expire timeout must not exceed block timeout */ if (phc->expire_timeout_usec > phc->block_timeout_usec) phc->expire_timeout_usec = phc->block_timeout_usec; -/* Prepare PHC feature command with PHC output address */ +/* Prepare PHC config feature command */ memset (&set_feat_cmd,0x0 ,sizeof (set_feat_cmd)); set_feat_cmd.aq_common_descriptor.opcode =ENA_ADMIN_SET_FEATURE ; set_feat_cmd.feat_common.feature_id =ENA_ADMIN_PHC_CONFIG ;
@@ -1840,13 +1847,16 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)void ena_com_phc_destroy (struct ena_com_dev *ena_dev) {struct ena_com_phc_info *phc = &ena_dev->phc; - - phc->active = false; +unsigned long flags =0 ;/* In case PHC is not supported by the device, silently exiting */ if (!phc->virt_addr)return ; +ENA_SPINLOCK_LOCK (phc->lock, flags); + phc->active = false; +ENA_SPINLOCK_UNLOCK (phc->lock, flags); + ENA_MEM_FREE_COHERENT(ena_dev->dmadev, sizeof(*phc->virt_addr), phc->virt_addr,
@@ -1857,15 +1867,14 @@ void ena_com_phc_destroy(struct ena_com_dev *ena_dev)ENA_SPINLOCK_DESTROY (phc->lock); } -int ena_com_phc_get (struct ena_com_dev *ena_dev,u64 *timestamp) +int ena_com_phc_get_timestamp (struct ena_com_dev *ena_dev,u64 *timestamp) {volatile struct ena_admin_phc_resp *read_resp = ena_dev->phc.virt_addr; +const ena_time_high_res_t zero_system_time =ENA_TIME_INIT_HIGH_RES ();struct ena_com_phc_info *phc = &ena_dev->phc; -ena_time_high_res_t initial_time =ENA_TIME_INIT_HIGH_RES (); -static ena_time_high_res_t start_time; -unsigned long flags =0 ;ena_time_high_res_t expire_time;ena_time_high_res_t block_time; +unsigned long flags =0 ;int ret =ENA_COM_OK ;if (!phc->active) {
@@ -1876,9 +1885,10 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp)ENA_SPINLOCK_LOCK (phc->lock, flags);/* Check if PHC is in blocked state */ -if (unlikely (ENA_TIME_COMPARE_HIGH_RES (start_time, initial_time))) { +if (unlikely (ENA_TIME_COMPARE_HIGH_RES (phc->system_time, zero_system_time))) {/* Check if blocking time expired */ - block_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (start_time, phc->block_timeout_usec); + block_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (phc->system_time, + phc->block_timeout_usec);if (!ENA_TIME_EXPIRE_HIGH_RES (block_time)) {/* PHC is still in blocked state, skip PHC request */ phc->stats.phc_skp++;
@@ -1886,22 +1896,23 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp) goto skip; } -/* PHC is in active state, update statistics according to req_id and timestamp */ +/* PHC is in active state, update statistics according to req_id and error_flags */ if ((READ_ONCE16 (read_resp->req_id) != phc->req_id) || - read_resp->timestamp ==ENA_PHC_TIMESTAMP_ERROR ) + (read_resp->error_flags &ENA_PHC_ERROR_FLAGS )) {/* Device didn't update req_id during blocking time or timestamp is invalid, * this indicates on a device error */ phc->stats.phc_err++; -else + }else {/* Device updated req_id during blocking time with valid timestamp */ phc->stats.phc_exp++; + } }/* Setting relative timeouts */ - start_time =ENA_GET_SYSTEM_TIME_HIGH_RES (); - block_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (start_time, phc->block_timeout_usec); - expire_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (start_time, phc->expire_timeout_usec); + phc->system_time =ENA_GET_SYSTEM_TIME_HIGH_RES (); + block_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (phc->system_time, phc->block_timeout_usec); + expire_time =ENA_GET_SYSTEM_TIMEOUT_HIGH_RES (phc->system_time, phc->expire_timeout_usec);/* We expect the device to return this req_id once the new PHC timestamp is updated */ phc->req_id++;
@@ -1918,35 +1929,45 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp)while (1 ) {if (unlikely (ENA_TIME_EXPIRE_HIGH_RES (expire_time))) {/* Gave up waiting for updated req_id, PHC enters into blocked state until -* passing blocking time +* passing blocking time, during this time any get PHC timestamp or +* error bound requests will fail with device busy error */ + phc->error_bound =ENA_PHC_MAX_ERROR_BOUND ; ret =ENA_COM_DEVICE_BUSY ;break ; }/* Check if req_id was updated by the device */ if (READ_ONCE16 (read_resp->req_id) != phc->req_id) { -/* req_id was not updated by the device, check again on next loop */ +/* req_id was not updated by the device yet, check again on next loop */ continue ; } -/* req_id was updated which indicates that PHC timestamp was updated too */ - *timestamp = read_resp->timestamp; - -/* PHC timestamp validty check */ -if (unlikely (*timestamp ==ENA_PHC_TIMESTAMP_ERROR )) { -/* Retrieved invalid PHC timestamp, PHC enters into blocked state until -* passing blocking time +/* req_id was updated by the device which indicates that PHC timestamp, error_bound +* and error_flags are updated too, checking errors before retrieving timestamp and +* error_bound values +*/ +if (unlikely (read_resp->error_flags &ENA_PHC_ERROR_FLAGS )) { +/* Retrieved timestamp or error bound errors, PHC enters into blocked state +* until passing blocking time, during this time any get PHC timestamp or +* error bound requests will fail with device busy error */ + phc->error_bound =ENA_PHC_MAX_ERROR_BOUND ; ret =ENA_COM_DEVICE_BUSY ;break ; } -/* Retrieved valid PHC timestamp */ +/* PHC timestamp value is returned to the caller */ + *timestamp = read_resp->timestamp; + +/* Error bound value is cached for future retrieval by caller */ + phc->error_bound = read_resp->error_bound; + +/* Update statistic on valid PHC timestamp retrieval */ phc->stats.phc_cnt++;/* This indicates PHC state is active */ - start_time = initial_time; + phc->system_time = zero_system_time;break ; }
@@ -1956,6 +1977,24 @@ int ena_com_phc_get(struct ena_com_dev *ena_dev, u64 *timestamp)return ret; } +int ena_com_phc_get_error_bound (struct ena_com_dev *ena_dev,u32 *error_bound) +{ +struct ena_com_phc_info *phc = &ena_dev->phc; +u32 local_error_bound = phc->error_bound; + +if (!phc->active) { +ena_trc_err (ena_dev,"PHC feature is not active in the device\n" ); +return ENA_COM_UNSUPPORTED ; + } + +if (local_error_bound ==ENA_PHC_MAX_ERROR_BOUND ) +return ENA_COM_DEVICE_BUSY ; + + *error_bound = local_error_bound; + +return ENA_COM_OK ; +} +int ena_com_mmio_reg_read_request_init (struct ena_com_dev *ena_dev) {struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read;
@@ -2453,9 +2492,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, reset_val |= reset_reason_lsb <<ENA_REGS_DEV_CTL_RESET_REASON_SHIFT ; -if (ena_com_get_cap (ena_dev,ENA_ADMIN_EXTENDED_RESET_REASONS )) { +if (ena_com_get_cap (ena_dev,ENA_ADMIN_EXTENDED_RESET_REASONS )) reset_val |= reset_reason_msb <<ENA_REGS_DEV_CTL_RESET_REASON_EXT_SHIFT ; - }else if (reset_reason_msb) { +else if (reset_reason_msb) {/* In case the device does not support intended * extended reset reason fallback to generic */
drivers/net/ena/hal/ena_com.h +22 -9
@@ -274,6 +274,9 @@ struct ena_com_phc_info {/* PHC shared memory - virtual address */ struct ena_admin_phc_resp *virt_addr; +/* System time of last PHC request */ +ena_time_high_res_t system_time; +/* Spin lock to ensure a single outstanding PHC read */ ena_spinlock_t lock;
@@ -293,17 +296,20 @@ struct ena_com_phc_info {*/ u32 block_timeout_usec; +/* PHC shared memory - physical address */ +dma_addr_t phys_addr; + +/* PHC shared memory handle */ +ena_mem_handle_t mem_handle; + +/* Cached error bound per timestamp sample */ +u32 error_bound; +/* Request id sent to the device */ u16 req_id;/* True if PHC is active in the device */ bool active; - -/* PHC shared memory - memory handle */ -ena_mem_handle_t mem_handle; - -/* PHC shared memory - physical address */ -dma_addr_t phys_addr; };struct ena_rss {
@@ -468,12 +474,19 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev);*/ void ena_com_phc_destroy (struct ena_com_dev *ena_dev); -/* ena_com_phc_get - Retrieve PHC timestamp +/* ena_com_phc_get_timestamp - Retrieve PHC timestamp +* @ena_dev: ENA communication layer struct +* @timestamp: Retrieved PHC timestamp +* @return - 0 on success, negative value on failure +*/ +int ena_com_phc_get_timestamp (struct ena_com_dev *ena_dev,u64 *timestamp); + +/* ena_com_phc_get_error_bound - Retrieve cached PHC error bound * @ena_dev: ENA communication layer struct -* @timestamp: Retrieve PHC timestamp +* @error_bound: Cached PHC error bound * @return - 0 on success, negative value on failure */ -int ena_com_phc_get (struct ena_com_dev *ena_dev,u64 *timestamp); +int ena_com_phc_get_error_bound (struct ena_com_dev *ena_dev,u32 *error_bound);/* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism * @ena_dev: ENA communication layer struct
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +38 -7
88 lines not on this page · raw message
Signature · 1 line
2.17.1
PATCH 17/33 net/ena/hal: restructure interrupt handling
In reply to [email protected]From: Shai Brandes <[email protected]>
When invoking an admin command, in interrupt mode, if the interrupt is received after timeout and also after the calling function finished running, the response will be written into a memory that is no longer valid.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/net/ena/hal/ena_com.c +4 -0
@@ -181,6 +181,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev,static void comp_ctxt_release (struct ena_com_admin_queue *queue,struct ena_comp_ctx *comp_ctx) { + comp_ctx->user_cqe =NULL ; comp_ctx->occupied = false;ATOMIC32_DEC (&queue->outstanding_cmds); }
@@ -474,6 +475,9 @@ static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *areturn ; } +if (!comp_ctx->occupied) +return ; + comp_ctx->status =ENA_CMD_COMPLETED ; comp_ctx->comp_status = cqe->acq_common_descriptor.status;
Signature · 1 line
2.17.1
PATCH 18/33 net/ena/hal: add unlikely to error checks
In reply to [email protected]From: Shai Brandes <[email protected]>
The unlikely mechanism is used to reduce pipe flush,
caused by a wrong branch prediction.
Moreover, it increases readability by wrapping unexpected errors. This commit adds unlikely to error checks that are unlikely to happen.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 56 +++++++++++++++---------------- drivers/net/ena/hal/ena_eth_com.c | 2 +- 2 files changed, 29 insertions(+), 29 deletions(-)
drivers/net/ena/hal/ena_com.c +28 -28
@@ -79,7 +79,7 @@ static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, struct ena_common_mem_addr *ena_addr, dma_addr_t addr) { -if ((addr &GENMASK_ULL (ena_dev->dma_addr_bits -1 ,0 )) != addr) { + if (unlikely((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr)) { ena_trc_err(ena_dev, "DMA address has more bits than the device supports\n");return ENA_COM_INVAL ; }
@@ -99,7 +99,7 @@ static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue)ENA_MEM_ALLOC_COHERENT (admin_queue->q_dmadev, size, sq->entries, sq->dma_addr, sq->mem_handle); -if (!sq->entries) { +if (unlikely (!sq->entries)) {ena_trc_err (ena_dev,"Memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -122,7 +122,7 @@ static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue)ENA_MEM_ALLOC_COHERENT (admin_queue->q_dmadev, size, cq->entries, cq->dma_addr, cq->mem_handle); -if (!cq->entries) { +if (unlikely (!cq->entries)) {ena_trc_err (ena_dev,"Memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -147,7 +147,7 @@ static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, aenq->dma_addr, aenq->mem_handle); -if (!aenq->entries) { +if (unlikely (!aenq->entries)) {ena_trc_err (ena_dev,"Memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -233,7 +233,7 @@ static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queu/* In case of queue FULL */ cnt = (u16 )ATOMIC32_READ (&admin_queue->outstanding_cmds); -if (cnt >= admin_queue->q_depth) { +if (unlikely (cnt >= admin_queue->q_depth)) {ena_trc_dbg (admin_queue->ena_dev,"Admin queue is full.\n" ); admin_queue->stats.out_of_space++;return ERR_PTR (ENA_COM_NO_SPACE );
@@ -357,7 +357,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, io_sq->desc_addr.mem_handle); } -if (!io_sq->desc_addr.virt_addr) { +if (unlikely (!io_sq->desc_addr.virt_addr)) {ena_trc_err (ena_dev,"Memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -382,7 +382,7 @@ static int ena_com_init_io_sq(struct ena_com_dev *ena_dev,if (!io_sq->bounce_buf_ctrl.base_buffer) io_sq->bounce_buf_ctrl.base_buffer =ENA_MEM_ALLOC (ena_dev->dmadev, size); -if (!io_sq->bounce_buf_ctrl.base_buffer) { +if (unlikely (!io_sq->bounce_buf_ctrl.base_buffer)) {ena_trc_err (ena_dev,"Bounce buffer memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -447,7 +447,7 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, ENA_CDESC_RING_SIZE_ALIGNMENT); } -if (!io_cq->cdesc_addr.virt_addr) { +if (unlikely (!io_cq->cdesc_addr.virt_addr)) {ena_trc_err (ena_dev,"Memory allocation failed\n" );return ENA_COM_NO_MEM ; }
@@ -577,7 +577,7 @@ static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_cif (comp_ctx->status !=ENA_CMD_SUBMITTED )break ; -if (ENA_TIME_EXPIRE (timeout)) { +if (unlikely (ENA_TIME_EXPIRE (timeout))) {ena_trc_err (admin_queue->ena_dev,"Wait for completion (polling) timeout\n" );/* ENA didn't have any completion */
@@ -776,7 +776,7 @@ static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, llq_default_cfg->llq_ring_entry_size_value; rc =ena_com_set_llq (ena_dev); -if (rc) +if (unlikely (rc))ena_trc_err (ena_dev,"Cannot set LLQ configuration: %d\n" , rc);return rc;
@@ -882,7 +882,7 @@ static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) goto err; } -if (read_resp->reg_off != offset) { +if (unlikely (read_resp->reg_off != offset)) {ena_trc_err (ena_dev,"Read failure: wrong offset provided\n" ); ret =ENA_MMIO_READ_TIMEOUT ; }else {
@@ -1006,7 +1006,7 @@ static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, exp_state)return 0 ; -if (ENA_TIME_EXPIRE (timeout_stamp)) +if (unlikely (ENA_TIME_EXPIRE (timeout_stamp)))return ENA_COM_TIMER_EXPIRED ;ena_delay_exponential_backoff_us (exp++, ena_dev->ena_min_poll_delay_us);
@@ -1467,7 +1467,7 @@ int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, struct ena_com_io_sq **io_sq, struct ena_com_io_cq **io_cq) { -if (qid >=ENA_TOTAL_NUM_QUEUES ) { + if (unlikely(qid >= ENA_TOTAL_NUM_QUEUES)) { ena_trc_err(ena_dev, "Invalid queue number %d but the max is %d\n", qid, ENA_TOTAL_NUM_QUEUES);return ENA_COM_INVAL ;
@@ -1575,7 +1575,7 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag)int ret; ret =ena_com_get_feature (ena_dev, &get_resp,ENA_ADMIN_AENQ_CONFIG ,0 ); -if (ret) { +if (unlikely (ret)) {ena_trc_info (ena_dev,"Can't get aenq configuration\n" );return ret; }
@@ -1622,7 +1622,7 @@ int ena_com_get_dma_width(struct ena_com_dev *ena_dev)ena_trc_dbg (ena_dev,"ENA dma width: %d\n" , width); -if ((width <32 ) || width >ENA_MAX_PHYS_ADDR_SIZE_BITS ) { +if (unlikely (width <32 || width >ENA_MAX_PHYS_ADDR_SIZE_BITS )) {ena_trc_err (ena_dev,"DMA width illegal value: %d\n" , width);return ENA_COM_INVAL ; }
@@ -2092,15 +2092,15 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,ENA_SPINLOCK_INIT (admin_queue->q_lock); ret =ena_com_init_comp_ctxt (admin_queue); -if (ret) +if (unlikely (ret)) goto error; ret =ena_com_admin_init_sq (admin_queue); -if (ret) +if (unlikely (ret)) goto error; ret =ena_com_admin_init_cq (admin_queue); -if (ret) +if (unlikely (ret)) goto error; admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
@@ -2133,7 +2133,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev,ENA_REG_WRITE32 (ena_dev->bus, aq_caps, ena_dev->reg_bar +ENA_REGS_AQ_CAPS_OFF );ENA_REG_WRITE32 (ena_dev->bus, acq_caps, ena_dev->reg_bar +ENA_REGS_ACQ_CAPS_OFF ); ret =ena_com_admin_init_aenq (ena_dev, aenq_handlers); -if (ret) +if (unlikely (ret)) goto error; admin_queue->ena_dev = ena_dev;
@@ -2153,7 +2153,7 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,struct ena_com_io_cq *io_cq;int ret; -if (ctx->qid >=ENA_TOTAL_NUM_QUEUES ) { +if (unlikely (ctx->qid >=ENA_TOTAL_NUM_QUEUES )) {ena_trc_err (ena_dev,"Qid (%d) is bigger than max num of queues (%d)\n" , ctx->qid,ENA_TOTAL_NUM_QUEUES );return ENA_COM_INVAL ;
@@ -2184,18 +2184,18 @@ int ena_com_create_io_queue(struct ena_com_dev *ena_dev,ENA_MIN32 (ena_dev->tx_max_header_size,SZ_256 ); ret =ena_com_init_io_sq (ena_dev, ctx, io_sq); -if (ret) +if (unlikely (ret)) goto error; ret =ena_com_init_io_cq (ena_dev, ctx, io_cq); -if (ret) +if (unlikely (ret)) goto error; ret =ena_com_create_io_cq (ena_dev, io_cq); -if (ret) +if (unlikely (ret)) goto error; ret =ena_com_create_io_sq (ena_dev, io_sq, io_cq->idx); -if (ret) +if (unlikely (ret)) goto destroy_io_cq;return 0 ;
@@ -2212,7 +2212,7 @@ void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid)struct ena_com_io_sq *io_sq;struct ena_com_io_cq *io_cq; -if (qid >=ENA_TOTAL_NUM_QUEUES ) { +if (unlikely (qid >=ENA_TOTAL_NUM_QUEUES )) {ena_trc_err (ena_dev,"Qid (%d) is bigger than max num of queues (%d)\n" , qid,ENA_TOTAL_NUM_QUEUES );return ;
@@ -2513,7 +2513,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev, rc =wait_for_reset_state (ena_dev, timeout,ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK ); -if (rc !=0 ) { +if (unlikely (rc)) {ena_trc_err (ena_dev,"Reset indication didn't turn on\n" );return rc; }
@@ -2521,7 +2521,7 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev,/* reset done */ ENA_REG_WRITE32 (ena_dev->bus,0 , ena_dev->reg_bar +ENA_REGS_DEV_CTL_OFF ); rc =wait_for_reset_state (ena_dev, timeout,0 ); -if (rc !=0 ) { +if (unlikely (rc)) {ena_trc_err (ena_dev,"Reset indication didn't turn off\n" );return rc; }
@@ -3383,7 +3383,7 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, } rc =ena_com_config_llq_info (ena_dev, llq_features, llq_default_cfg); -if (rc) +if (unlikely (rc))return rc; ena_dev->tx_max_header_size = llq_info->desc_list_entry_size -
drivers/net/ena/hal/ena_eth_com.c +1 -1
@@ -455,7 +455,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,/* If the caller doesn't want to send packets */ if (unlikely (!num_bufs && !header_len)) { rc =ena_com_close_bounce_buffer (io_sq); -if (rc) +if (unlikely (rc))ena_trc_err (ena_com_io_sq_to_ena_dev (io_sq),"Failed to write buffers to LLQ\n" ); *nb_hw_desc = io_sq->tail - start_tail;
Signature · 1 line
2.17.1
PATCH 19/33 net/ena/hal: missing admin interrupt reset reason
In reply to [email protected]From: Shai Brandes <[email protected]>
There can be cases when we trigger reset if an admin interrupt is missing.
In order to identify this use-case specifically, this commit adds a new reset reason.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 2 ++ drivers/net/ena/hal/ena_com.h | 12 ++++++++++++ drivers/net/ena/hal/ena_defs/ena_regs_defs.h | 1 + 3 files changed, 15 insertions(+)
drivers/net/ena/hal/ena_com.c +2 -0
@@ -803,6 +803,7 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comENA_SPINLOCK_UNLOCK (admin_queue->q_lock, flags);if (comp_ctx->status ==ENA_CMD_COMPLETED ) { + admin_queue->is_missing_admin_interrupt = true;ena_trc_err (admin_queue->ena_dev,"The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n" , comp_ctx->cmd_opcode, admin_queue->auto_polling ?"ON" :"OFF" );
@@ -2138,6 +2139,7 @@ int ena_com_admin_init(struct ena_com_dev *ena_dev, admin_queue->ena_dev = ena_dev; admin_queue->running_state = true; + admin_queue->is_missing_admin_interrupt = false;return 0 ; error:
drivers/net/ena/hal/ena_com.h +12 -0
@@ -237,6 +237,8 @@ struct ena_com_admin_queue {*/ bool running_state; +bool is_missing_admin_interrupt; +/* Count the number of outstanding admin commands */ ena_atomic32_t outstanding_cmds;
@@ -1089,6 +1091,16 @@ int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,struct ena_admin_feature_llq_desc *llq_features, struct ena_llq_configurations *llq_default_config); +/* ena_com_get_missing_admin_interrupt - Return if there is a missing admin interrupt +* @ena_dev: ENA communication layer struct +* +* @return - true if there is a missing admin interrupt or false otherwise +*/ +static inline bool ena_com_get_missing_admin_interrupt (struct ena_com_dev *ena_dev) +{ +return ena_dev->admin_queue.is_missing_admin_interrupt; +} +/* ena_com_io_sq_to_ena_dev - Extract ena_com_dev using contained field io_sq. * @io_sq: IO submit queue struct *
drivers/net/ena/hal/ena_defs/ena_regs_defs.h +1 -0
@@ -24,6 +24,7 @@ enum ena_regs_reset_reason_types {ENA_REGS_RESET_SUSPECTED_POLL_STARVATION =15 ,ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED =16 ,ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED =17 , +ENA_REGS_RESET_MISSING_ADMIN_INTERRUPT =18 , ENA_REGS_RESET_LAST, };
Signature · 1 line
2.17.1
PATCH 20/33 net/ena/hal: check for existing keep alive notification
In reply to [email protected]From: Shai Brandes <[email protected]>
This commit adds an API to query the aenq on whether there is a pending keep alive notification.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 39 +++++++++++++++++++++++++++++++++++ drivers/net/ena/hal/ena_com.h | 10 +++++++++ 2 files changed, 49 insertions(+)
drivers/net/ena/hal/ena_com.c +39 -0
@@ -2456,6 +2456,45 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)mmiowb (); } +bool ena_com_aenq_has_keep_alive (struct ena_com_dev *ena_dev) +{ +struct ena_admin_aenq_common_desc *aenq_common; +struct ena_com_aenq *aenq = &ena_dev->aenq; +struct ena_admin_aenq_entry *aenq_e; +u8 phase = aenq->phase; +u16 masked_head; + + masked_head = aenq->head & (aenq->q_depth -1 ); + aenq_e = &aenq->entries[masked_head];/* Get first entry */ + aenq_common = &aenq_e->aenq_common_desc; + +/* Go over all the events */ +while ((READ_ONCE8 (aenq_common->flags) & +ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK ) == phase) { +/* Make sure the device finished writing the rest of the descriptor +* before reading it. +*/ +dma_rmb (); + +if (aenq_common->group ==ENA_ADMIN_KEEP_ALIVE ) +return true; + +/* Get next event entry */ + masked_head++; + +if (unlikely (masked_head == aenq->q_depth)) { + masked_head =0 ; + phase = !phase; + } + + aenq_e = &aenq->entries[masked_head]; + aenq_common = &aenq_e->aenq_common_desc; + } + +return false; +} + +int ena_com_dev_reset (struct ena_com_dev *ena_dev,enum ena_regs_reset_reason_types reset_reason) {
drivers/net/ena/hal/ena_com.h +10 -0
@@ -639,6 +639,16 @@ void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);*/ void ena_com_aenq_intr_handler (struct ena_com_dev *ena_dev,void *data); +/* ena_com_aenq_has_keep_alive - Retrieve if there is a keep alive notification in the aenq +* @ena_dev: ENA communication layer struct +* +* This method goes over the async event notification queue and returns if there +* is a keep alive notification. +* +* @return - true if there is a keep alive notification in the aenq or false otherwise +*/ +bool ena_com_aenq_has_keep_alive (struct ena_com_dev *ena_dev); +/* ena_com_abort_admin_commands - Abort all the outstanding admin commands. * @ena_dev: ENA communication layer struct *
Signature · 1 line
2.17.1
PATCH 21/33 net/ena/hal: modify memory barrier comment
In reply to [email protected]From: Shai Brandes <[email protected]>
The dma_rmb() memory barrier guarantees that the device set the phase bit before continuing to read the rest of the descriptor. Because the phase bit and the rest of the descriptor are in the same cache line this ensures coherency of the data from the descriptor.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/net/ena/hal/ena_com.c +2 -2
@@ -2412,8 +2412,8 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data)/* Go over all the events */ while ((READ_ONCE8 (aenq_common->flags) &ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK ) == phase) { -/* Make sure the phase bit (ownership) is as expected before -* reading the rest of the descriptor. +/* Make sure the device finished writing the rest of the descriptor +* before reading it. */ dma_rmb ();
Signature · 1 line
2.17.1
PATCH 22/33 net/ena/hal: rework Rx ring submission queue
In reply to [email protected]From: Shai Brandes <[email protected]>
RX ring submission queue descriptors are always located in host memory This optimization replaces the generic update tail method with a tailored method for host memory type descriptors to avoid unnecessary if statement.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
drivers/net/ena/hal/ena_eth_com.c +10 -5
@@ -210,11 +210,8 @@ static int ena_com_sq_update_llq_tail(struct ena_com_io_sq *io_sq)return ENA_COM_OK ; } -static int ena_com_sq_update_tail (struct ena_com_io_sq *io_sq) +static int ena_com_sq_update_reqular_queue_tail (struct ena_com_io_sq *io_sq) { -if (io_sq->mem_queue_type ==ENA_ADMIN_PLACEMENT_POLICY_DEV ) -return ena_com_sq_update_llq_tail (io_sq); - io_sq->tail++;/* Switch phase bit in case of wrap around */
@@ -224,6 +221,14 @@ static int ena_com_sq_update_tail(struct ena_com_io_sq *io_sq)return ENA_COM_OK ; } +static int ena_com_sq_update_tail (struct ena_com_io_sq *io_sq) +{ +if (io_sq->mem_queue_type ==ENA_ADMIN_PLACEMENT_POLICY_DEV ) +return ena_com_sq_update_llq_tail (io_sq); + +return ena_com_sq_update_reqular_queue_tail (io_sq); +} +static struct ena_eth_io_rx_cdesc_base *ena_com_rx_cdesc_idx_to_ptr (struct ena_com_io_cq *io_cq,u16 idx) {
@@ -662,7 +667,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->buff_addr_hi = ((ena_buf->paddr &GENMASK_ULL (io_sq->dma_addr_bits -1 ,32 )) >>32 ); -return ena_com_sq_update_tail (io_sq); +return ena_com_sq_update_reqular_queue_tail (io_sq); }bool ena_com_cq_empty (struct ena_com_io_cq *io_cq)
Signature · 1 line
2.17.1
PATCH 23/33 net/ena/hal: remove operating system type enum
In reply to [email protected]From: Shai Brandes <[email protected]>
remove all othe operating system enumeration as they are unrelated to DPDK. Use a constant value instead.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 13 +------------ drivers/net/ena/hal/ena_plat_dpdk.h | 1 + 2 files changed, 2 insertions(+), 12 deletions(-)
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +1 -12
@@ -933,19 +933,8 @@ struct ena_admin_feature_rss_flow_hash_input {uint16_t enabled_input_sort; }; -enum ena_admin_os_type { -ENA_ADMIN_OS_LINUX =1 , -ENA_ADMIN_OS_WIN =2 , -ENA_ADMIN_OS_DPDK =3 , -ENA_ADMIN_OS_FREEBSD =4 , -ENA_ADMIN_OS_IPXE =5 , -ENA_ADMIN_OS_ESXI =6 , -ENA_ADMIN_OS_MACOS =7 , -ENA_ADMIN_OS_GROUPS_NUM =7 , -}; -struct ena_admin_host_info { -/* defined in enum ena_admin_os_type */ +/* Host OS type defined as ENA_ADMIN_OS_* */ uint32_t os_type;/* os distribution string format */
drivers/net/ena/hal/ena_plat_dpdk.h +1 -0
@@ -341,5 +341,6 @@ static __rte_always_inline int ena_bits_per_u64(uint64_t bitmap) return count; } +#define ENA_ADMIN_OS_DPDK 3#endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */
Signature · 1 line
2.17.1
PATCH 24/33 net/ena/hal: handle command abort
In reply to [email protected]From: Shai Brandes <[email protected]>
Currently admin_queue->stats.aborted_cmd counter is incremented if an admin command status is ENA_CMD_ABORTED and only if the admin queue is in polling mode.
This commit fixes handling the case of incrementing admin_queue->stats.aborted_cmd if the admin queue is in interrupt mode as well.
Also added a verification that the command status is a valid completion status which is currently verified only if the admin queue is in polling mode.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 11 +++++++++++ 1 file changed, 11 insertions(+)
drivers/net/ena/hal/ena_com.c +11 -0
@@ -824,8 +824,19 @@ static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *com ret =ENA_COM_TIMER_EXPIRED ; goto err; } + }else if (unlikely (comp_ctx->status ==ENA_CMD_ABORTED )) { +ena_trc_err (admin_queue->ena_dev,"Command was aborted\n" ); +ENA_SPINLOCK_LOCK (admin_queue->q_lock, flags); + admin_queue->stats.aborted_cmd++; +ENA_SPINLOCK_UNLOCK (admin_queue->q_lock, flags); + ret =ENA_COM_NO_DEVICE ; + goto err; } +ENA_WARN (comp_ctx->status !=ENA_CMD_COMPLETED , + admin_queue->ena_dev,"Invalid comp status %d\n" , + comp_ctx->status); + ret =ena_com_comp_status_to_errno (admin_queue, comp_ctx->comp_status); err:comp_ctxt_release (admin_queue, comp_ctx);
Signature · 1 line
2.17.1
PATCH 25/33 net/ena/hal: add support for device reset request
In reply to [email protected]From: Shai Brandes <[email protected]>
Adds support for reset request message from the device to the driver, over AENQ, which in turn should cause the driver to trigger reset.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 3 ++- drivers/net/ena/hal/ena_defs/ena_regs_defs.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-)
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +2 -1
@@ -1213,7 +1213,8 @@ enum ena_admin_aenq_group {ENA_ADMIN_KEEP_ALIVE =4 ,ENA_ADMIN_REFRESH_CAPABILITIES =5 ,ENA_ADMIN_CONF_NOTIFICATIONS =6 , - ENA_ADMIN_AENQ_GROUPS_NUM = 7, +ENA_ADMIN_DEVICE_REQUEST_RESET =7 , + ENA_ADMIN_AENQ_GROUPS_NUM = 8, }; enum ena_admin_aenq_notification_syndrome {
drivers/net/ena/hal/ena_defs/ena_regs_defs.h +1 -0
@@ -25,6 +25,7 @@ enum ena_regs_reset_reason_types {ENA_REGS_RESET_RX_DESCRIPTOR_MALFORMED =16 ,ENA_REGS_RESET_TX_DESCRIPTOR_MALFORMED =17 ,ENA_REGS_RESET_MISSING_ADMIN_INTERRUPT =18 , +ENA_REGS_RESET_DEVICE_REQUEST =19 , ENA_REGS_RESET_LAST, };
Signature · 1 line
2.17.1
PATCH 26/33 net/ena: cosmetic changes
In reply to [email protected]From: Shai Brandes <[email protected]>
This patch makes several changes to improve
the style and readability of the code.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-)
drivers/net/ena/hal/ena_com.c +6 -9
@@ -1808,7 +1808,7 @@ int ena_com_phc_config(struct ena_com_dev *ena_dev)/* Supporting only PHC V0 (readless mode with error bound) */ if (get_feat_resp.u.phc.version !=ENA_ADMIN_PHC_FEATURE_VERSION_0 ) { -ena_trc_err (ena_dev,"Unsupprted PHC version (0x%X), error: %d\n" , +ena_trc_err (ena_dev,"Unsupported PHC version (0x%X), error: %d\n" , get_feat_resp.u.phc.version,ENA_COM_UNSUPPORTED );return ENA_COM_UNSUPPORTED ;
@@ -1914,15 +1914,14 @@ int ena_com_phc_get_timestamp(struct ena_com_dev *ena_dev, u64 *timestamp)/* PHC is in active state, update statistics according to req_id and error_flags */ if ((READ_ONCE16 (read_resp->req_id) != phc->req_id) || - (read_resp->error_flags &ENA_PHC_ERROR_FLAGS )) { + (read_resp->error_flags &ENA_PHC_ERROR_FLAGS ))/* Device didn't update req_id during blocking time or timestamp is invalid, * this indicates on a device error */ phc->stats.phc_err++; - }else { +else /* Device updated req_id during blocking time with valid timestamp */ phc->stats.phc_exp++; - } }/* Setting relative timeouts */
@@ -2431,7 +2430,7 @@ void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) timestamp = (u64 )aenq_common->timestamp_low | ((u64 )aenq_common->timestamp_high <<32 ); -ena_trc_dbg (ena_dev,"AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIU64 "s]\n" , +ena_trc_dbg (ena_dev,"AENQ! Group[%x] Syndrome[%x] timestamp: [%" ENA_PRIu64"s]\n" , aenq_common->group, aenq_common->syndrome, timestamp);
@@ -3233,16 +3232,15 @@ int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev) {struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; + customer_metrics->buffer_len =ENA_CUSTOMER_METRICS_BUFFER_SIZE ;ENA_MEM_ALLOC_COHERENT (ena_dev->dmadev, customer_metrics->buffer_len, customer_metrics->buffer_virt_addr, customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); -if (unlikely (customer_metrics->buffer_virt_addr ==NULL )) +if (unlikely (!customer_metrics->buffer_virt_addr))return ENA_COM_NO_MEM ; - customer_metrics->buffer_len =ENA_CUSTOMER_METRICS_BUFFER_SIZE ; -return 0 ; }
@@ -3285,7 +3283,6 @@ void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev) customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); customer_metrics->buffer_virt_addr =NULL ; - customer_metrics->buffer_len =0 ; } }
Signature · 1 line
2.17.1
PATCH 27/33 net/ena/hal: modify customer metrics memory management
In reply to [email protected]From: Shai Brandes <[email protected]>
1. Set buffer length to zero in case memory allocation failed and after memory is released.
2. The driver checks buffer_virt_addr for customer allocation success. In case the allocation fails, buffer_virt_addr may not necessarily be NULL.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_com.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/net/ena/hal/ena_com.c +6 -1
@@ -3233,13 +3233,17 @@ int ena_com_allocate_customer_metrics_buffer(struct ena_com_dev *ena_dev)struct ena_customer_metrics *customer_metrics = &ena_dev->customer_metrics; customer_metrics->buffer_len =ENA_CUSTOMER_METRICS_BUFFER_SIZE ; + customer_metrics->buffer_virt_addr =NULL ; +ENA_MEM_ALLOC_COHERENT (ena_dev->dmadev, customer_metrics->buffer_len, customer_metrics->buffer_virt_addr, customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); -if (unlikely (!customer_metrics->buffer_virt_addr)) +if (unlikely (!customer_metrics->buffer_virt_addr)) { + customer_metrics->buffer_len =0 ;return ENA_COM_NO_MEM ; + }return 0 ; }
@@ -3283,6 +3287,7 @@ void ena_com_delete_customer_metrics_buffer(struct ena_com_dev *ena_dev) customer_metrics->buffer_dma_addr, customer_metrics->buffer_dma_handle); customer_metrics->buffer_virt_addr =NULL ; + customer_metrics->buffer_len =0 ; } }
Signature · 1 line
2.17.1
PATCH 28/33 net/ena/hal: cosmetic changes
In reply to [email protected]From: Shai Brandes <[email protected]>
1. modify log prints to use correct format specifier for unsigned variables.
2. removed line breaks for lines that do not exceed maximal line length.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/hal/ena_eth_com.c | 22 +++++++++++----------- drivers/net/ena/hal/ena_plat_dpdk.h | 5 ++--- 2 files changed, 13 insertions(+), 14 deletions(-)
drivers/net/ena/hal/ena_eth_com.c +11 -11
@@ -64,7 +64,7 @@ static int ena_com_write_bounce_buffer_to_dev(struct ena_com_io_sq *io_sq, io_sq->entries_in_tx_burst_left--;ena_trc_dbg (ena_com_io_sq_to_ena_dev (io_sq), -"Decreasing entries_in_tx_burst_left of queue %d to %d\n" , +"Decreasing entries_in_tx_burst_left of queue %u to %u\n" , io_sq->qid, io_sq->entries_in_tx_burst_left); }
@@ -259,7 +259,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,if (unlikely ((status &ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK ) >>ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT && count !=0 )) {ena_trc_err (dev, -"First bit is on in descriptor #%d on q_id: %d, req_id: %u\n" , +"First bit is on in descriptor #%u on q_id: %u, req_id: %u\n" , count, io_cq->qid, cdesc->req_id);return ENA_COM_FAULT ; }
@@ -268,7 +268,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK)) && ena_com_get_cap(dev, ENA_ADMIN_CDESC_MBZ))) {ena_trc_err (dev, -"Corrupted RX descriptor #%d on q_id: %d, req_id: %u\n" , +"Corrupted RX descriptor #%u on q_id: %u, req_id: %u\n" , count, io_cq->qid, cdesc->req_id);return ENA_COM_FAULT ; }
@@ -288,7 +288,7 @@ static int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq, io_cq->cur_rx_pkt_cdesc_start_idx = head_masked;ena_trc_dbg (ena_com_io_cq_to_ena_dev (io_cq), -"ENA q_id: %d packets were completed. first desc idx %u descs# %d\n" , +"ENA q_id: %u packets were completed. first desc idx %u descs# %u\n" , io_cq->qid, *first_cdesc_idx, count); }else { io_cq->cur_rx_pkt_cdesc_count = count;
@@ -394,7 +394,7 @@ static void ena_com_rx_set_flags(struct ena_com_io_cq *io_cq,ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT ; ena_trc_dbg(ena_com_io_cq_to_ena_dev(io_cq), - "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %d frag %d cdesc_status %x\n", + "l3_proto %d l4_proto %d l3_csum_err %d l4_csum_err %d hash %u frag %d cdesc_status %x\n", ena_rx_ctx->l3_proto, ena_rx_ctx->l4_proto, ena_rx_ctx->l3_csum_err,
@@ -434,7 +434,7 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,if (unlikely (header_len > io_sq->tx_max_header_size)) {ena_trc_err (ena_com_io_sq_to_ena_dev (io_sq), -"Header size is too large %d max header: %d\n" , +"Header size is too large %u max header: %u\n" , header_len, io_sq->tx_max_header_size);return ENA_COM_INVAL ; }
@@ -592,12 +592,12 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, }ena_trc_dbg (ena_com_io_cq_to_ena_dev (io_cq), -"Fetch rx packet: queue %d completed desc: %d\n" , +"Fetch rx packet: queue %u completed desc: %u\n" , io_cq->qid, nb_hw_desc);if (unlikely (nb_hw_desc > ena_rx_ctx->max_bufs)) {ena_trc_err (ena_com_io_cq_to_ena_dev (io_cq), -"Too many RX cdescs (%d) > MAX(%d)\n" , +"Too many RX cdescs (%u) > MAX(%u)\n" , nb_hw_desc, ena_rx_ctx->max_bufs);return ENA_COM_NO_SPACE ; }
@@ -622,7 +622,7 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq, io_sq->next_to_comp += nb_hw_desc;ena_trc_dbg (ena_com_io_cq_to_ena_dev (io_cq), -"[%s][QID#%d] Updating SQ head to: %d\n" , __func__, +"Updating Queue %u, SQ head to: %u\n" , io_sq->qid, io_sq->next_to_comp);/* Get rx flags from the last pkt */
@@ -660,8 +660,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq, desc->req_id = req_id;ena_trc_dbg (ena_com_io_sq_to_ena_dev (io_sq), -"[%s] Adding single RX desc, Queue: %u, req_id: %u\n" , - __func__, io_sq->qid, req_id); +"Adding single RX desc, Queue: %u, req_id: %u\n" , + io_sq->qid, req_id); desc->buff_addr_lo = (u32 )ena_buf->paddr; desc->buff_addr_hi =
drivers/net/ena/hal/ena_plat_dpdk.h +2 -3
@@ -40,7 +40,7 @@ typedef uint64_t dma_addr_t;#define ETIME ETIMEDOUT#endif -#define ENA_PRIU64 PRIu64 +#define ENA_PRIu64 PRIu64#define ena_atomic32_t rte_atomic32_t#define ena_mem_handle_t const struct rte_memzone *
@@ -73,8 +73,7 @@ typedef uint64_t dma_addr_t;/* Redefine memcpy with caution: rte_memcpy can be simply aliased to memcpy, so * make the redefinition only if it's safe (and beneficial) to do so. */ -#if defined(RTE_ARCH_X86 ) || defined(RTE_ARCH_ARM64_MEMCPY ) || \ - defined(RTE_ARCH_ARM_NEON_MEMCPY ) +#if defined(RTE_ARCH_X86 ) || defined(RTE_ARCH_ARM64_MEMCPY ) || defined(RTE_ARCH_ARM_NEON_MEMCPY )#undef memcpy#define memcpy rte_memcpy#endif
Signature · 1 line
2.17.1
PATCH 29/33 net/ena: update device-preferred size of rings
In reply to [email protected]From: Shai Brandes <[email protected]>
Update the device-preferred size of the Tx ring to fall within the valid range when a large LLQ is enabled. For consistency, align the device-preferred size of the Rx ring accordingly.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/ena_ethdev.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/net/ena/ena_ethdev.c +4 -2
@@ -2595,8 +2595,10 @@ static int ena_infos_get(struct rte_eth_dev *dev, dev_info->tx_desc_lim.nb_mtu_seg_max =RTE_MIN (ENA_PKT_MAX_BUFS , adapter->max_tx_sgl_size); - dev_info->default_rxportconf.ring_size =ENA_DEFAULT_RING_SIZE ; - dev_info->default_txportconf.ring_size =ENA_DEFAULT_RING_SIZE ; + dev_info->default_rxportconf.ring_size =RTE_MIN (ENA_DEFAULT_RING_SIZE , + dev_info->rx_desc_lim.nb_max); + dev_info->default_txportconf.ring_size =RTE_MIN (ENA_DEFAULT_RING_SIZE , + dev_info->tx_desc_lim.nb_max); dev_info->err_handle_mode =RTE_ETH_ERROR_HANDLE_MODE_PASSIVE ;
Signature · 1 line
2.17.1
PATCH 30/33 net/ena: exhaust interrupt callbacks in device close
In reply to [email protected]From: Shai Brandes <[email protected]>
Change rte_intr_callback_unregister to its synchronous variant to ensure all active interrupt callbacks are completed before proceeding with the flow. Relocate the interrupt deregistration to precede the release of stats memory, thereby preventing the interrupt handler from accessing memory that has already been freed.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/ena_ethdev.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
drivers/net/ena/ena_ethdev.c +6 -5
@@ -871,6 +871,7 @@ static int ena_close(struct rte_eth_dev *dev)struct rte_intr_handle *intr_handle = pci_dev->intr_handle;struct ena_adapter *adapter = dev->data->dev_private;int ret =0 ; +int rc;if (rte_eal_process_type () !=RTE_PROC_PRIMARY )return 0 ;
@@ -879,17 +880,17 @@ static int ena_close(struct rte_eth_dev *dev) ret =ena_stop (dev); adapter->state =ENA_ADAPTER_STATE_CLOSED ; +rte_intr_disable (intr_handle); + rc =rte_intr_callback_unregister_sync (intr_handle, ena_interrupt_handler_rte, dev); +if (unlikely (rc !=0 )) +PMD_INIT_LOG (ERR ,"Failed to unregister interrupt handler\n" ); +ena_rx_queue_release_all (dev);ena_tx_queue_release_all (dev);rte_free (adapter->drv_stats); adapter->drv_stats =NULL ; -rte_intr_disable (intr_handle); -rte_intr_callback_unregister (intr_handle, - ena_interrupt_handler_rte, - dev); -/* * MAC is not allocated dynamically. Setting NULL should prevent from * release of the resource in the rte_eth_dev_release_port().
Signature · 1 line
2.17.1
PATCH 31/33 net/ena: support max large llq depth from the device
In reply to [email protected]From: Shai Brandes <[email protected]>
Selected AWS instances from later generations enable large LLQ by default, allowing the transmission of packets with headers exceeding 96 bytes.
Due to the overall ENA memory BAR size limitation, large LLQ has the side effect of halving the maximum number of LLQ entries (from 1024 to 512).
ENA-Express, powered by AWS Scalable Reliable Datagram (SRD) technology, requires Tx queue with 1024 entries. Selected AWS instances from upcoming generations will have double the size of the ENA memory BAR, enabling ENA-Express to work with a large LLQ of 1024 entries.
The initial default large LLQ size will remain 512.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/rel_notes/release_24_03.rst | 2 + drivers/net/ena/ena_ethdev.c | 38 ++++++++++++------- drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 4 +- 3 files changed, 29 insertions(+), 15 deletions(-)
doc/guides/rel_notes/release_24_03.rst +2 -0
@@ -107,6 +107,8 @@ New Features * Added support for sub-optimal configuration notifications from the device. * Restructured fast release of mbufs when RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE optimization is enabled. * Replaced `enable_llq` and `large_llq_hdr` devargs with a new devarg `llq_policy`. + * Added support for LLQ header size recommendation from the device. + * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR. * **Updated Atomic Rules' Arkville driver.**
drivers/net/ena/ena_ethdev.c +25 -13
@@ -42,6 +42,8 @@#define DECIMAL_BASE 10 +#define MAX_WIDE_LLQ_DEPTH_UNSUPPORTED 0 +/* * We should try to keep ENA_CLEANUP_BUF_SIZE lower than * RTE_MEMPOOL_CACHE_MAX_SIZE, so we can fit this in mempool local cache.
@@ -1071,7 +1073,7 @@ static int ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, bool use_large_llq_hdr) { -struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; +struct ena_admin_feature_llq_desc *dev = &ctx->get_feat_ctx->llq;struct ena_com_dev *ena_dev = ctx->ena_dev;uint32_t max_tx_queue_size;uint32_t max_rx_queue_size;
@@ -1086,7 +1088,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,if (ena_dev->tx_mem_queue_type ==ENA_ADMIN_PLACEMENT_POLICY_DEV ) { max_tx_queue_size =RTE_MIN (max_tx_queue_size, - llq->max_llq_depth); + dev->max_llq_depth); }else { max_tx_queue_size =RTE_MIN (max_tx_queue_size, max_queue_ext->max_tx_sq_depth);
@@ -1106,7 +1108,7 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx,if (ena_dev->tx_mem_queue_type ==ENA_ADMIN_PLACEMENT_POLICY_DEV ) { max_tx_queue_size =RTE_MIN (max_tx_queue_size, - llq->max_llq_depth); + dev->max_llq_depth); }else { max_tx_queue_size =RTE_MIN (max_tx_queue_size, max_queues->max_sq_depth);
@@ -1122,18 +1124,28 @@ ena_calc_io_queue_size(struct ena_calc_queue_size_ctx *ctx, max_rx_queue_size =rte_align32prevpow2 (max_rx_queue_size); max_tx_queue_size =rte_align32prevpow2 (max_tx_queue_size); -if (use_large_llq_hdr) { -if ((llq->entry_size_ctrl_supported & -ENA_ADMIN_LIST_ENTRY_SIZE_256B ) && - (ena_dev->tx_mem_queue_type == -ENA_ADMIN_PLACEMENT_POLICY_DEV )) { - max_tx_queue_size /=2 ; -PMD_INIT_LOG (INFO , -"Forcing large headers and decreasing maximum Tx queue size to %d\n" , +if (ena_dev->tx_mem_queue_type ==ENA_ADMIN_PLACEMENT_POLICY_DEV && use_large_llq_hdr) { +/* intersection between driver configuration and device capabilities */ +if (dev->entry_size_ctrl_supported &ENA_ADMIN_LIST_ENTRY_SIZE_256B ) { +if (dev->max_wide_llq_depth ==MAX_WIDE_LLQ_DEPTH_UNSUPPORTED ) { +/* Devices that do not support the double-sized ENA memory BAR will +* report max_wide_llq_depth as 0. In such case, driver halves the +* queue depth when working in large llq policy. +*/ + max_tx_queue_size >>=1 ; +PMD_INIT_LOG (INFO , +"large LLQ policy requires limiting Tx queue size to %u entries\n" , max_tx_queue_size); + }else if (dev->max_wide_llq_depth < max_tx_queue_size) { +/* In case the queue depth that the driver calculated exceeds +* the maximal value that the device allows, it will be limited +* to that maximal value +*/ + max_tx_queue_size = dev->max_wide_llq_depth; + } }else { -PMD_INIT_LOG (ERR , -"Forcing large headers failed: LLQ is disabled or device does not support large headers\n" ); +PMD_INIT_LOG (INFO , +"Forcing large LLQ headers failed since device lacks this support\n" ); } }
drivers/net/ena/hal/ena_defs/ena_admin_defs.h +2 -2
@@ -696,8 +696,8 @@ struct ena_admin_feature_llq_desc {*/ uint8_t entry_size_recommended; -/* reserved */ -uint8_t reserved1[2 ]; +/* max depth of wide llq, or 0 for N/A */ +uint16_t max_wide_llq_depth;/* accelerated low latency queues requirement. driver needs to * support those requirements in order to use accelerated llq
Signature · 1 line
2.17.1
PATCH 32/33 net/ena: control path pure polling mode
In reply to [email protected]From: Shai Brandes <[email protected]>
This commit implements a new operation mode that enables purely polling-based functionality, eliminating the need for interrupts in the control path. This mode is not activated by default and can be toggled using the "control_poll_interval" devarg. When operating in this mode, periodic alarms are used to monitor the control queues.
A non-zero value for this devarg is mandatory for control path functionality when binding ports to uio_pci_generic kernel module which lacks interrupt support.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- doc/guides/nics/ena.rst | 49 ++++++++--- doc/guides/rel_notes/release_24_03.rst | 2 + drivers/net/ena/ena_ethdev.c | 108 ++++++++++++++++++++----- drivers/net/ena/ena_ethdev.h | 5 ++ 4 files changed, 130 insertions(+), 34 deletions(-)
doc/guides/nics/ena.rst +36 -13
@@ -109,12 +109,16 @@ Runtime Configuration * **llq_policy** (default 1) - Controls whether use device recommended header policy or override it. + Controls whether use device recommended header policy or override it: + 0 - Disable LLQ. - **Use with extreme caution as it leads to a huge performance - degradation on AWS instances from 6th generation onwards.** + **Use with extreme caution as it leads to a huge performance + degradation on AWS instances from 6th generation onwards.** + 1 - Accept device recommended LLQ policy (Default). + 2 - Enforce normal LLQ policy. + 3 - Enforce large LLQ policy. * **miss_txc_to** (default 5)
@@ -126,6 +130,18 @@ Runtime Configuration timer service. Setting this parameter to 0 disables this feature. Maximum allowed value is 60 seconds. + * **control_poll_interval** (default 0) + + Enable polling-based functionality of the admin queues, eliminating the + need for interrupts in the control-path: + + 0 - Disable (Admin queue will work in interrupt mode). + + [1..1000] - Number of milliseconds to wait between periodic inspection of the admin queues. + + **A non-zero value for this devarg is mandatory for control path functionality + when binding ports to uio_pci_generic kernel module which lacks interrupt support.** + ENA Configuration Parameters ^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -164,23 +180,23 @@ Prerequisites #. Prepare the system as recommended by DPDK suite. This includes environment variables, hugepages configuration, tool-chains and configuration. -#. ENA PMD can operate with ``vfio-pci``(*) or ``igb_uio`` driver. +#. ENA PMD can operate with ``vfio-pci`` (*), ``igb_uio``, or ``uio_pci_generic`` driver. (*) ENAv2 hardware supports Low Latency Queue v2 (LLQv2). This feature reduces the latency of the packets by pushing the header directly through the PCI to the device, before the DMA is even triggered. For proper work - kernel PCI driver must support write combining (WC). + kernel PCI driver must support write-combining (WC). In DPDK ``igb_uio`` it must be enabled by loading module with ``wc_activate=1`` flag (example below). However, mainline's vfio-pci - driver in kernel doesn't have WC support yet (planed to be added). + driver in kernel doesn't have WC support yet (planned to be added). If vfio-pci is used user should follow `AWS ENA PMD documentation <https://github.com/amzn/amzn-drivers/tree/master/userspace/dpdk/README.md>`_. -#. Insert ``vfio-pci`` or ``igb_uio`` kernel module using the command - ``modprobe vfio-pci`` or ``modprobe uio; insmod igb_uio.ko wc_activate=1`` - respectively. +#. For ``igb_uio``: + Insert ``igb_uio`` kernel module using the command ``modprobe uio; insmod igb_uio.ko wc_activate=1`` -#. For ``vfio-pci`` users only: +#. For ``vfio-pci``: + Insert ``vfio-pci`` kernel module using the command ``modprobe vfio-pci`` Please make sure that ``IOMMU`` is enabled in your system, or use ``vfio`` driver in ``noiommu`` mode::
@@ -189,7 +205,14 @@ Prerequisites To use ``noiommu`` mode, the ``vfio-pci`` must be built with flag ``CONFIG_VFIO_NOIOMMU``. -#. Bind the intended ENA device to ``vfio-pci`` or ``igb_uio`` module. +#. For ``uio_pci_generic``: + Insert ``uio_pci_generic`` kernel module using the command ``modprobe uio_pci_generic``. + + Note that when launching the application, the ``control_poll_interval`` devarg must be used with a non-zero value (1000 is recommended) + as ``uio_pci_generic`` lacks interrupt support. The control-path (admin queues) of the ENA require poll-mode + to process command completion and asyncronous notification from the device. + +#. Bind the intended ENA device to ``vfio-pci``, ``igb_uio``, or ``uio_pci_generic`` module. At this point the system should be ready to run DPDK applications. Once the application runs to completion, the ENA can be detached from attached module if
@@ -198,7 +221,7 @@ necessary. **Rx interrupts support** ENA PMD supports Rx interrupts, which can be used to wake up lcores waiting for -input. Please note that it won't work with ``igb_uio``, so to use this feature, +input. Please note that it won't work with ``igb_uio`` and ``uio_pci_generic`` so to use this feature, the ``vfio-pci`` should be used. ENA handles admin interrupts and AENQ notifications on separate interrupt.
@@ -209,7 +232,7 @@ will fail. **Note about usage on \*.metal instances** On AWS, the metal instances are supporting IOMMU for both arm64 and x86_64 -hosts. +hosts. Note that ``uio_pci_generic`` lacks IOMMU support and cannot be used for metal instances. * x86_64 (e.g. c5.metal, i3.metal): IOMMU should be disabled by default. In that situation, the ``igb_uio`` can
doc/guides/rel_notes/release_24_03.rst +2 -0
@@ -109,6 +109,8 @@ New Features * Replaced `enable_llq` and `large_llq_hdr` devargs with a new devarg `llq_policy`. * Added support for LLQ header size recommendation from the device. * Allowed large LLQ with 1024 entries when the device supports enlarged memory BAR. + * Added `control_poll_interval` devarg that configure control-path to work in poll-mode. + * Added support for binding ports to `uio_pci_generic` kernel module. * **Updated Atomic Rules' Arkville driver.**
drivers/net/ena/ena_ethdev.c +87 -21
206 lines not on this page · raw message
drivers/net/ena/ena_ethdev.h +5 -0
@@ -44,6 +44,8 @@#define ENA_MONITORED_TX_QUEUES 3#define ENA_DEFAULT_MISSING_COMP 256U +#define ENA_MAX_CONTROL_PATH_POLL_INTERVAL_MSEC 1000 +/* While processing submitted and completed descriptors (rx and tx path * respectively) in a loop it is desired to: * - perform batch submissions while populating submission queue
@@ -346,6 +348,9 @@ struct ena_adapter {uint64_t memzone_cnt; +/* Time (in microseconds) of the control path queues monitoring interval */ +uint64_t control_path_poll_interval; +/* * Helper variables for holding the information about the supported * metrics.
Signature · 1 line
2.17.1
PATCH 33/33 net/ena: upgrade driver version to 2.9.0
In reply to [email protected]From: Shai Brandes <[email protected]>
upgrade driver version to 2.9.0.
Signed-off-by Shai Brandes <[email protected]>
Reviewed-by Amit Bernstein <[email protected]>
--- drivers/net/ena/ena_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/net/ena/ena_ethdev.c +1 -1
@@ -22,7 +22,7 @@#include <ena_eth_io_defs.h> #define DRV_MODULE_VER_MAJOR 2 -#define DRV_MODULE_VER_MINOR 8 +#define DRV_MODULE_VER_MINOR 9#define DRV_MODULE_VER_SUBMINOR 0#define __MERGE_64B_H_L (h, l) (((uint64_t)h << 32) | l)
Signature · 1 line
2.17.1