FAILED: patch "[PATCH] perf/x86/amd/core: Update and fix stalled-cycles-* events for" failed to apply to 6.6-stable tree
Subsystems (3)
[email protected]
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x c7b2edd8377be983442c1344cb940cd2ac21b601
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2024040100-clinking-stylized-0888@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^..
Possible dependencies:
c7b2edd8377b ("perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From c7b2edd8377be983442c1344cb940cd2ac21b601 Mon Sep 17 00:00:00 2001
From: Sandipan Das <[email protected]>
Date: Mon, 25 Mar 2024 13:17:53 +0530
Subject: [PATCH] perf/x86/amd/core: Update and fix stalled-cycles-* events for
Zen 2 and later
AMD processors based on Zen 2 and later microarchitectures do not support PMCx087 (instruction pipe stalls) which is used as the backing event for "stalled-cycles-frontend" and "stalled-cycles-backend".
Use PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend stalls and remove the entry for backend stalls since there is no direct replacement.
arch/x86/events/amd/core.c +17 -3
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =/* * AMD Performance Monitor Family 17h and later: */ -static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX ] = +static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX ] = { [PERF_COUNT_HW_CPU_CYCLES ] =0x0076 , [PERF_COUNT_HW_INSTRUCTIONS ] =0x00c0 ,
@@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187, }; +static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX ] = +{ + [PERF_COUNT_HW_CPU_CYCLES ] =0x0076 , + [PERF_COUNT_HW_INSTRUCTIONS ] =0x00c0 , + [PERF_COUNT_HW_CACHE_REFERENCES ] =0xff60 , + [PERF_COUNT_HW_CACHE_MISSES ] =0x0964 , + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS ] =0x00c2 , + [PERF_COUNT_HW_BRANCH_MISSES ] =0x00c3 , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x00a9 , +}; +static u64 amd_pmu_event_map (int hw_event) { -if (boot_cpu_data.x86 >=0x17 ) -return amd_f17h_perfmon_event_map[hw_event]; +if (cpu_feature_enabled (X86_FEATURE_ZEN2 ) || boot_cpu_data.x86 >=0x19 ) +return amd_zen2_perfmon_event_map[hw_event]; + +if (cpu_feature_enabled (X86_FEATURE_ZEN1 )) +return amd_zen1_perfmon_event_map[hw_event];return amd_perfmon_event_map[hw_event]; }