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arm64: dts: sprd: Split PMU nodes for heterogeneous CPUs

PATCH Applied Rob Herring 2 participants 2 messages Apr 12, 2024 – Jun 12, 2024

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Rob Herring

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PATCH 1/1 arm64: dts: sprd: Split PMU nodes for heterogeneous CPUs

Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations.

Signed-off-by Rob Herring <[email protected]>
---
 arch/arm64/boot/dts/sprd/ums512.dtsi  | 14 ++++++++++----
 arch/arm64/boot/dts/sprd/ums9620.dtsi | 14 ++++++++++----
 2 files changed, 20 insertions(+), 8 deletions(-)
arch/arm64/boot/dts/sprd/ums512.dtsi +10 -4
index dbdb79f8e959..4c080df48724 100644
@@ -136,16 +136,22 @@ timer {
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
 		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>;
+	};
+
+	pmu-a75 {
+		compatible = "arm,cortex-a75-pmu";
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CPU6>, <&CPU7>;
 	};
 
 	soc: soc {
arch/arm64/boot/dts/sprd/ums9620.dtsi +10 -4
index 2191f0a4811b..2458071320c9 100644
@@ -144,16 +144,22 @@ timer {
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
+	pmu-a55 {
+		compatible = "arm,cortex-a55-pmu";
 		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>;
+	};
+
+	pmu-a76 {
+		compatible = "arm,cortex-a76-pmu";
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
 	};
 
 	soc: soc {
Signature · 1 line
2.43.0
Applied
#1 lore raw
Quoted 6 lines · Rob Herring

Arm heterogeneous configurations should have separate PMU nodes for each CPU uarch as the uarch specific events can be different. The "arm,armv8-pmuv3" compatible is also intended for s/w models rather than specific uarch implementations.

No one took it for two months (!!!), so I'll grab it for my other generic cleanups.

Applied, thanks!

[1/1] arm64: dts: sprd: Split PMU nodes for heterogeneous CPUs

      https://git.kernel.org/krzk/linux-dt/c/b32e036a7403289b2a10a438bb852da7ca651c86

Best regards,

Signature · 1 line
Krzysztof Kozlowski <[email protected]>