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Add GPADC for Allwinner H616

PATCH Applied Chris Morgan 8 participants 14 messages Apr 17, 2024 – May 28, 2024

Subsystems (5)
Device tree bindings Common clk IIO Arm/Allwinner sunXi SoC support +1 more subsystems

v1 of 2 Applied Latest is v2 →

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Chris Morgan

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#0 lore raw

cover Add GPADC for Allwinner H616

From: Chris Morgan <[email protected]>

Add support for the general purpose analog-to-digital converter (GPADC) for the Allwinner H616 SoC.

Chris Morgan (3):
clk: sunxi-ng: h616: Add clock/reset for GPADC
dt-bindings: iio: adc: Add GPADC for Allwinner H616
arm64: dts: allwinner: h616: Add GPADC device node

 .../bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml   |  9 +++++++--
 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi        | 11 +++++++++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c                |  5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h                |  2 +-
 include/dt-bindings/clock/sun50i-h616-ccu.h           |  1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h           |  1 +
 6 files changed, 26 insertions(+), 3 deletions(-)

--
2.34.1

author
#1 lore raw

PATCH 1/3 clk: sunxi-ng: h616: Add clock/reset for GPADC

From: Chris Morgan <[email protected]>

Add the GPADC required clock and reset which is used for the onboard GPADC.

Signed-off-by Chris Morgan <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c      | 5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h      | 2 +-
 include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun50i-h616.c +5 -0
index 21e918582aa5..3646be2b88ab 100644
@@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
 
 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
 
+static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
+
 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
 
 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",

@@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
 	&bus_emac1_clk.common,
 	&ts_clk.common,
 	&bus_ts_clk.common,
+	&bus_gpadc_clk.common,
 	&bus_ths_clk.common,
 	&spdif_clk.common,
 	&bus_spdif_clk.common,

@@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
 		[CLK_BUS_EMAC1]		= &bus_emac1_clk.common.hw,
 		[CLK_TS]		= &ts_clk.common.hw,
 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
+		[CLK_BUS_GPADC]		= &bus_gpadc_clk.common.hw,
 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,

@@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
 	[RST_BUS_EMAC0]		= { 0x97c, BIT(16) },
 	[RST_BUS_EMAC1]		= { 0x97c, BIT(17) },
 	[RST_BUS_TS]		= { 0x9bc, BIT(16) },
+	[RST_BUS_GPADC]		= { 0x9ec, BIT(16) },
 	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
 	[RST_BUS_SPDIF]		= { 0xa2c, BIT(16) },
 	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
drivers/clk/sunxi-ng/ccu-sun50i-h616.h +1 -1
index fdd2f4d5103f..a75803b49f6a 100644
@@ -51,6 +51,6 @@
 
 #define CLK_BUS_DRAM		56
 
-#define CLK_NUMBER		(CLK_PLL_SYSTEM_32K + 1)
+#define CLK_NUMBER		(CLK_BUS_GPADC + 1)
 
 #endif /* _CCU_SUN50I_H616_H_ */
include/dt-bindings/clock/sun50i-h616-ccu.h +1 -0
index 6f8f01e67628..ebb146ab7f8c 100644
@@ -112,5 +112,6 @@
 #define CLK_HDCP		126
 #define CLK_BUS_HDCP		127
 #define CLK_PLL_SYSTEM_32K	128
+#define CLK_BUS_GPADC		129
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
include/dt-bindings/reset/sun50i-h616-ccu.h +1 -0
index 1bd8bb0a11be..ed177c04afdd 100644
@@ -66,5 +66,6 @@
 #define RST_BUS_TVE0		57
 #define RST_BUS_HDCP		58
 #define RST_BUS_KEYADC		59
+#define RST_BUS_GPADC		60
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
Signature · 1 line
2.34.1
maintainer Acked-by on v1 1/3
#2 lore raw

Re: [PATCH 1/3] clk: sunxi-ng: h616: Add clock/reset for GPADC

Dne sreda, 17. april 2024 ob 19:04:21 GMT +2 je Chris Morgan napisal(a):

Quoted 6 lines

From: Chris Morgan <[email protected]>

Add the GPADC required clock and reset which is used for the onboard GPADC.

Signed-off-by Chris Morgan <[email protected]>
Acked-by Jernej Skrabec <[email protected]>

Best regards,
Jernej

Quoted 79 lines
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c      | 5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h      | 2 +-
 include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun50i-h616.c +5 -0
index 21e918582aa5..3646be2b88ab 100644
@@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
 
 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
 
+static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
+
 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
 
 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",

@@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
 	&bus_emac1_clk.common,
 	&ts_clk.common,
 	&bus_ts_clk.common,
+	&bus_gpadc_clk.common,
 	&bus_ths_clk.common,
 	&spdif_clk.common,
 	&bus_spdif_clk.common,

@@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
 		[CLK_BUS_EMAC1]		= &bus_emac1_clk.common.hw,
 		[CLK_TS]		= &ts_clk.common.hw,
 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
+		[CLK_BUS_GPADC]		= &bus_gpadc_clk.common.hw,
 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,

@@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
 	[RST_BUS_EMAC0]		= { 0x97c, BIT(16) },
 	[RST_BUS_EMAC1]		= { 0x97c, BIT(17) },
 	[RST_BUS_TS]		= { 0x9bc, BIT(16) },
+	[RST_BUS_GPADC]		= { 0x9ec, BIT(16) },
 	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
 	[RST_BUS_SPDIF]		= { 0xa2c, BIT(16) },
 	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
drivers/clk/sunxi-ng/ccu-sun50i-h616.h +1 -1
index fdd2f4d5103f..a75803b49f6a 100644
@@ -51,6 +51,6 @@
 
 #define CLK_BUS_DRAM		56
 
-#define CLK_NUMBER		(CLK_PLL_SYSTEM_32K + 1)
+#define CLK_NUMBER		(CLK_BUS_GPADC + 1)
 
 #endif /* _CCU_SUN50I_H616_H_ */
include/dt-bindings/clock/sun50i-h616-ccu.h +1 -0
index 6f8f01e67628..ebb146ab7f8c 100644
@@ -112,5 +112,6 @@
 #define CLK_HDCP		126
 #define CLK_BUS_HDCP		127
 #define CLK_PLL_SYSTEM_32K	128
+#define CLK_BUS_GPADC		129
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
include/dt-bindings/reset/sun50i-h616-ccu.h +1 -0
index 1bd8bb0a11be..ed177c04afdd 100644
@@ -66,5 +66,6 @@
 #define RST_BUS_TVE0		57
 #define RST_BUS_HDCP		58
 #define RST_BUS_KEYADC		59
+#define RST_BUS_GPADC		60
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
Reviewed-by on v1 1/3
#3 lore raw

Re: [PATCH 1/3] clk: sunxi-ng: h616: Add clock/reset for GPADC

In reply to Chris Morgan

On Wed, 17 Apr 2024 12:04:21 -0500
Chris Morgan <[email protected]> wrote:

Hi,

Quoted 4 lines

From: Chris Morgan <[email protected]>

Add the GPADC required clock and reset which is used for the onboard GPADC.

Compared the register offsets, bit numbers and parent clock against the
manual: they match. Also the new clock numbers look fine.

Reviewed-by Andre Przywara <[email protected]>

Cheers,
Andre

Quoted 79 lines
Signed-off-by Chris Morgan <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c      | 5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h      | 2 +-
 include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +
 4 files changed, 8 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun50i-h616.c +5 -0
index 21e918582aa5..3646be2b88ab 100644
@@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
 
 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
 
+static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
+
 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
 
 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",

@@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
 	&bus_emac1_clk.common,
 	&ts_clk.common,
 	&bus_ts_clk.common,
+	&bus_gpadc_clk.common,
 	&bus_ths_clk.common,
 	&spdif_clk.common,
 	&bus_spdif_clk.common,

@@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
 		[CLK_BUS_EMAC1]		= &bus_emac1_clk.common.hw,
 		[CLK_TS]		= &ts_clk.common.hw,
 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
+		[CLK_BUS_GPADC]		= &bus_gpadc_clk.common.hw,
 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
 		[CLK_SPDIF]		= &spdif_clk.common.hw,
 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,

@@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
 	[RST_BUS_EMAC0]		= { 0x97c, BIT(16) },
 	[RST_BUS_EMAC1]		= { 0x97c, BIT(17) },
 	[RST_BUS_TS]		= { 0x9bc, BIT(16) },
+	[RST_BUS_GPADC]		= { 0x9ec, BIT(16) },
 	[RST_BUS_THS]		= { 0x9fc, BIT(16) },
 	[RST_BUS_SPDIF]		= { 0xa2c, BIT(16) },
 	[RST_BUS_DMIC]		= { 0xa4c, BIT(16) },
drivers/clk/sunxi-ng/ccu-sun50i-h616.h +1 -1
index fdd2f4d5103f..a75803b49f6a 100644
@@ -51,6 +51,6 @@
 
 #define CLK_BUS_DRAM		56
 
-#define CLK_NUMBER		(CLK_PLL_SYSTEM_32K + 1)
+#define CLK_NUMBER		(CLK_BUS_GPADC + 1)
 
 #endif /* _CCU_SUN50I_H616_H_ */
include/dt-bindings/clock/sun50i-h616-ccu.h +1 -0
index 6f8f01e67628..ebb146ab7f8c 100644
@@ -112,5 +112,6 @@
 #define CLK_HDCP		126
 #define CLK_BUS_HDCP		127
 #define CLK_PLL_SYSTEM_32K	128
+#define CLK_BUS_GPADC		129
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
include/dt-bindings/reset/sun50i-h616-ccu.h +1 -0
index 1bd8bb0a11be..ed177c04afdd 100644
@@ -66,5 +66,6 @@
 #define RST_BUS_TVE0		57
 #define RST_BUS_HDCP		58
 #define RST_BUS_KEYADC		59
+#define RST_BUS_GPADC		60
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
#4 lore raw

Re: [PATCH 1/3] clk: sunxi-ng: h616: Add clock/reset for GPADC

In reply to Chris Morgan
Quoted 6 lines · Chris Morgan

From: Chris Morgan <[email protected]>

Add the GPADC required clock and reset which is used for the onboard GPADC.

Quoted 8 lines
Signed-off-by Chris Morgan <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c      | 5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h      | 2 +-
 include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +

These need an Ack from the DT binding maintainers. And it's better to split these into a separate patch.

ChenYu

Quoted 76 lines
 4 files changed, 8 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun50i-h616.c +5 -0
index 21e918582aa5..3646be2b88ab 100644
@@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
 
 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
 
+static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
+
 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
 
 static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",

@@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
        &bus_emac1_clk.common,
        &ts_clk.common,
        &bus_ts_clk.common,
+       &bus_gpadc_clk.common,
        &bus_ths_clk.common,
        &spdif_clk.common,
        &bus_spdif_clk.common,

@@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
                [CLK_BUS_EMAC1]         = &bus_emac1_clk.common.hw,
                [CLK_TS]                = &ts_clk.common.hw,
                [CLK_BUS_TS]            = &bus_ts_clk.common.hw,
+               [CLK_BUS_GPADC]         = &bus_gpadc_clk.common.hw,
                [CLK_BUS_THS]           = &bus_ths_clk.common.hw,
                [CLK_SPDIF]             = &spdif_clk.common.hw,
                [CLK_BUS_SPDIF]         = &bus_spdif_clk.common.hw,

@@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
        [RST_BUS_EMAC0]         = { 0x97c, BIT(16) },
        [RST_BUS_EMAC1]         = { 0x97c, BIT(17) },
        [RST_BUS_TS]            = { 0x9bc, BIT(16) },
+       [RST_BUS_GPADC]         = { 0x9ec, BIT(16) },
        [RST_BUS_THS]           = { 0x9fc, BIT(16) },
        [RST_BUS_SPDIF]         = { 0xa2c, BIT(16) },
        [RST_BUS_DMIC]          = { 0xa4c, BIT(16) },
drivers/clk/sunxi-ng/ccu-sun50i-h616.h +1 -1
index fdd2f4d5103f..a75803b49f6a 100644
@@ -51,6 +51,6 @@
 
 #define CLK_BUS_DRAM           56
 
-#define CLK_NUMBER             (CLK_PLL_SYSTEM_32K + 1)
+#define CLK_NUMBER             (CLK_BUS_GPADC + 1)
 
 #endif /* _CCU_SUN50I_H616_H_ */
include/dt-bindings/clock/sun50i-h616-ccu.h +1 -0
index 6f8f01e67628..ebb146ab7f8c 100644
@@ -112,5 +112,6 @@
 #define CLK_HDCP               126
 #define CLK_BUS_HDCP           127
 #define CLK_PLL_SYSTEM_32K     128
+#define CLK_BUS_GPADC          129
 
 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
include/dt-bindings/reset/sun50i-h616-ccu.h +1 -1
index 1bd8bb0a11be..ed177c04afdd 100644
@@ -66,5 +66,6 @@
 #define RST_BUS_TVE0           57
 #define RST_BUS_HDCP           58
 #define RST_BUS_KEYADC         59
+#define RST_BUS_GPADC          60
 
 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
--

2.34.1

#5 lore raw

Re: [PATCH 1/3] clk: sunxi-ng: h616: Add clock/reset for GPADC

Quoted 13 lines · Chen-Yu Tsai
Quoted 10 lines · Chris Morgan

From: Chris Morgan <[email protected]>

Add the GPADC required clock and reset which is used for the onboard GPADC.

Signed-off-by Chris Morgan <[email protected]>
---
 drivers/clk/sunxi-ng/ccu-sun50i-h616.c      | 5 +++++
 drivers/clk/sunxi-ng/ccu-sun50i-h616.h      | 2 +-
Quoted 5 lines
Quoted 2 lines
 include/dt-bindings/clock/sun50i-h616-ccu.h | 1 +
 include/dt-bindings/reset/sun50i-h616-ccu.h | 1 +

These need an Ack from the DT binding maintainers. And it's better to split these into a separate patch.

I am surprised that they were combined... So usual comment: Please split the bindings, because we do not want bindings to be in the same commit as driver.

Best regards,
Krzysztof

author
#6 lore raw

PATCH 2/3 dt-bindings: iio: adc: Add GPADC for Allwinner H616

In reply to Chris Morgan

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

Signed-off-by Chris Morgan <[email protected]>
---
 .../bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml      | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +7 -2
index 7ef46c90ebc8..da605a051b94 100644
@@ -11,8 +11,13 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - allwinner,sun20i-d1-gpadc
+    oneOf:
+      - enum:
+          - allwinner,sun20i-d1-gpadc
+      - items:
+          - enum:
+              - allwinner,sun50i-h616-gpadc
+          - const: allwinner,sun20i-d1-gpadc
 
   "#io-channel-cells":
     const: 1
Signature · 1 line
2.34.1
#7 lore raw

Re: [PATCH 2/3] dt-bindings: iio: adc: Add GPADC for Allwinner H616

On Wed, 17 Apr 2024 12:04:22 -0500
Chris Morgan <[email protected]> wrote:

Hi,

Quoted 4 lines

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

The H616 is using the same die as the T507 and the H700, and since the T507 is already mentioned in the commit message for the original binding, I wonder if we actually need a new compatible?
I guess we follow the usual approach and provide this new per-SoC compatible string, since the D1 and H616 SoCs are quite different? Just wanted to point this out...

Quoted 12 lines
Signed-off-by Chris Morgan <[email protected]>
---
 .../bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml      | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +0 -0
index 7ef46c90ebc8..da605a051b94 100644
@@ -11,8 +11,13 @@ maintainers:
 
 properties:

Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml maintainers: · line 20

Quoted 10 lines
Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +7 -2
   compatible:
-    enum:
-      - allwinner,sun20i-d1-gpadc
+    oneOf:
+      - enum:
+          - allwinner,sun20i-d1-gpadc
+      - items:
+          - enum:
+              - allwinner,sun50i-h616-gpadc
+          - const: allwinner,sun20i-d1-gpadc

I think a more compact way to write this would be:
oneOf:
- const: allwinner,sun20i-d1-gpadc
- items:
- const: allwinner,sun50i-h616-gpadc
- const: allwinner,sun20i-d1-gpadc

In general: the description in the T507 manual looks the same as in the D1 manual, just with the former having 4, and the latter 2 channels. If I understand correctly, this difference is not modelled in the binding (or the Linux driver, fwiw), so using the compatible fallback looks good.

Cheers,
Andre

Quoted 3 lines
Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +0 -0
   "#io-channel-cells":
     const: 1
maintainer
#8 lore raw

Re: [PATCH 2/3] dt-bindings: iio: adc: Add GPADC for Allwinner H616

Quoted 5 lines · Andre Przywara

On Wed, 17 Apr 2024 12:04:22 -0500
Chris Morgan <[email protected]> wrote:

Hi,

Quoted 8 lines
Quoted 4 lines

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

The H616 is using the same die as the T507 and the H700, and since the T507 is already mentioned in the commit message for the original binding, I wonder if we actually need a new compatible?

For same die, I would say no you don't. But adding a compatible is fine, too.

Rob

#9 lore raw

Re: [PATCH 2/3] dt-bindings: iio: adc: Add GPADC for Allwinner H616

Quoted 11 lines · Rob Herring
Quoted 10 lines · Andre Przywara

On Wed, 17 Apr 2024 12:04:22 -0500
Chris Morgan <[email protected]> wrote:

Hi,

Quoted 4 lines

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

Quoted 8 lines
Quoted 3 lines

The H616 is using the same die as the T507 and the H700, and since the T507 is already mentioned in the commit message for the original binding, I wonder if we actually need a new compatible?

For same die, I would say no you don't. But adding a compatible is fine, too.

Rob

I've been burned before, if it's just the same to you I'd like to do a compatible. But I will defer to the experts on this matter.

Also if there is a more compact way of expressing this while still maintaining backwards compatibility please let me know. Otherwise, I'm okay with this if you all are (it passes dt_binding_check, yamllint, and checkpatch.pl so I'm okay with it if you are).

Chris

maintainer Acked-by on v1 2/3
#10 lore raw

Re: [PATCH 2/3] dt-bindings: iio: adc: Add GPADC for Allwinner H616

In reply to Chris Morgan
Quoted 10 lines · Chris Morgan

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

Signed-off-by Chris Morgan <[email protected]>
---
 .../bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml      | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
Acked-by Rob Herring (Arm) <[email protected]>
maintainer Applied
#11 lore raw

Re: [PATCH 2/3] dt-bindings: iio: adc: Add GPADC for Allwinner H616

Quoted 6 lines · On Thu, 18 Apr 2024 10:17:33 -0500 Rob Herring <[email protected]> wrote:
Quoted 5 lines · Chris Morgan

From: Chris Morgan <[email protected]>

Add support for the GPADC for the Allwinner H616. It is identical to the existing ADC for the D1/T113s/R329/T507 SoCs.

Quoted 9 lines
Quoted 5 lines
Signed-off-by Chris Morgan <[email protected]>
---
 .../bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml      | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
Acked-by Rob Herring (Arm) <[email protected]>

Applied this patch to the IIO tree.

Jonathan

author
#12 lore raw

PATCH 3/3 arm64: dts: allwinner: h616: Add GPADC device node

In reply to Chris Morgan

From: Chris Morgan <[email protected]>

The H616 has a GPADC controller which is identical to the one found on the D1/T113s/R329/T507 SoCs.

Signed-off-by Chris Morgan <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +11 -0
index b2e85e52d1a1..3da37948b89f 100644
@@ -581,6 +581,17 @@ spdif: spdif@5093000 {
 			status = "disabled";
 		};
 
+		gpadc: adc@5070000 {
+			compatible = "allwinner,sun50i-h616-gpadc",
+				     "allwinner,sun20i-d1-gpadc";
+			reg = <0x05070000 0x400>;
+			clocks = <&ccu CLK_BUS_GPADC>;
+			resets = <&ccu RST_BUS_GPADC>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
 		ths: thermal-sensor@5070400 {
 			compatible = "allwinner,sun50i-h616-ths";
 			reg = <0x05070400 0x400>;
Signature · 1 line
2.34.1
Reviewed-by on v1 3/3
#13 lore raw

Re: [PATCH 3/3] arm64: dts: allwinner: h616: Add GPADC device node

Quoted 4 lines · On Wed, 17 Apr 2024 12:04:23 -0500 Chris Morgan <[email protected]> wrote:

From: Chris Morgan <[email protected]>

The H616 has a GPADC controller which is identical to the one found on the D1/T113s/R329/T507 SoCs.

Compared against the manual:

Reviewed-by Andre Przywara <[email protected]>

Cheers,
Andre

Quoted 27 lines
Signed-off-by Chris Morgan <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +11 -0
index b2e85e52d1a1..3da37948b89f 100644
@@ -581,6 +581,17 @@ spdif: spdif@5093000 {
 			status = "disabled";
 		};
 
+		gpadc: adc@5070000 {
+			compatible = "allwinner,sun50i-h616-gpadc",
+				     "allwinner,sun20i-d1-gpadc";
+			reg = <0x05070000 0x400>;
+			clocks = <&ccu CLK_BUS_GPADC>;
+			resets = <&ccu RST_BUS_GPADC>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
 		ths: thermal-sensor@5070400 {
 			compatible = "allwinner,sun50i-h616-ths";
 			reg = <0x05070400 0x400>;