drm/msm: Support a750 "software fuse" for raytracing

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +51 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +16 -0

+               adreno_gpu->has_ray_tracing =
+                       !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
+       }
+
+       return 0;
+}
+
+
 #define GBIF_CLIENT_HALT_MASK          BIT(0)
 #define GBIF_ARB_HALT_MASK             BIT(1)
 #define VBIF_XIN_HALT_CTRL0_MASK       GENMASK(3, 0)

@@ -3094,6 +3173,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
                return ERR_PTR(ret);
        }
 
+       if (adreno_is_a7xx(adreno_gpu)) {
+               ret = a7xx_cx_mem_init(a6xx_gpu);
+               if (ret) {
+                       a6xx_destroy(&(a6xx_gpu->base.base));
+                       return ERR_PTR(ret);
+               }
+       }
+
        if (gpu->aspace)
                msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
                                a6xx_fault_handler);

drivers/gpu/drm/msm/adreno/adreno_gpu.h +2 -1

index 77526892eb8c..4180f3149dd8 100644
@@ -182,6 +182,8 @@ struct adreno_gpu {
         */
        const unsigned int *reg_offsets;
        bool gmu_is_wrapper;
+
+       bool has_ray_tracing;
 };
 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
 
--

2.31.1

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

Quoted 41 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +16 -0

+               adreno_gpu->has_ray_tracing =
+                       !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
+       }
+
+       return 0;
+}
+
+
 #define GBIF_CLIENT_HALT_MASK          BIT(0)
 #define GBIF_ARB_HALT_MASK             BIT(1)
 #define VBIF_XIN_HALT_CTRL0_MASK       GENMASK(3, 0)

@@ -3094,6 +3173,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
                return ERR_PTR(ret);
        }
 
+       if (adreno_is_a7xx(adreno_gpu)) {
+               ret = a7xx_cx_mem_init(a6xx_gpu);
+               if (ret) {
+                       a6xx_destroy(&(a6xx_gpu->base.base));
+                       return ERR_PTR(ret);
+               }
+       }
+
        if (gpu->aspace)
                msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
                                a6xx_fault_handler);

drivers/gpu/drm/msm/adreno/adreno_gpu.h +2 -1

index 77526892eb8c..4180f3149dd8 100644
@@ -182,6 +182,8 @@ struct adreno_gpu {
         */
        const unsigned int *reg_offsets;
        bool gmu_is_wrapper;
+
+       bool has_ray_tracing;
 };
 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
 
--

Quoted 2 lines

2.31.1

--
With best wishes
Dmitry

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 123 lines · Connor Abbott

Quoted 119 lines · Dmitry Baryshkov

Quoted 103 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +51 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 10 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +10 -0

+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+
+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

Quoted 2 lines

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Sorry, didn't finish this thought. I meant to ask if you wanted to duplicate qcom_scm_is_available check and qcom_scm_gpu_init_regs between a750+ and everything else.

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 1 line

Quoted 4 lines

Quoted 2 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

Quoted 11 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 5 lines

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

Quoted 2 lines

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

Quoted 157 lines · Connor Abbott

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Quoted 9 lines

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

arch/arm64/qcom/dts and drivers/firmware/qcom are two separate trees. So yes, this needs a lot of coordination.

Quoted 14 lines

Quoted 13 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 5 lines

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

Quoted 4 lines

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

And it can happen if somebody running a bisect ends up in the branch with these patches in, but with the dtsi bits not being picked up.

Quoted 194 lines · Dmitry Baryshkov

Quoted 157 lines · Connor Abbott

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Quoted 9 lines

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

arch/arm64/qcom/dts and drivers/firmware/qcom are two separate trees. So yes, this needs a lot of coordination.

Quoted 18 lines

Quoted 6 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 1 line

Quoted 7 lines

Quoted 4 lines

Quoted 2 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

Quoted 2 lines

And it can happen if somebody running a bisect ends up in the branch with these patches in, but with the dtsi bits not being picked up.

That wouldn't be possible unless we merged the "bad" commit introducing the GPU node to sm8650.dtsi into msm-next but not the fix. So yeah, it's going to require a lot of careful cooperation but it should be possible to avoid that happening.

Quoted 200 lines · Connor Abbott

Quoted 196 lines · Dmitry Baryshkov

Quoted 157 lines · Connor Abbott

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Quoted 9 lines

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

arch/arm64/qcom/dts and drivers/firmware/qcom are two separate trees. So yes, this needs a lot of coordination.

Quoted 11 lines

Quoted 11 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 5 lines

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

Quoted 7 lines

Quoted 2 lines

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

And it can happen if somebody running a bisect ends up in the branch with these patches in, but with the dtsi bits not being picked up.

Quoted 4 lines

That wouldn't be possible unless we merged the "bad" commit introducing the GPU node to sm8650.dtsi into msm-next but not the fix. So yeah, it's going to require a lot of careful cooperation but it should be possible to avoid that happening.

Well, the GPU node is already there in the linux-next.

Anyway. Please. Don't break compat with old DTS. That is a rule of thumb.

Quoted 202 lines · Dmitry Baryshkov

Quoted 200 lines · Connor Abbott

Quoted 196 lines · Dmitry Baryshkov

Quoted 157 lines · Connor Abbott

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Quoted 9 lines

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

arch/arm64/qcom/dts and drivers/firmware/qcom are two separate trees. So yes, this needs a lot of coordination.

Quoted 11 lines

Quoted 11 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 5 lines

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

Quoted 7 lines

Quoted 2 lines

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

And it can happen if somebody running a bisect ends up in the branch with these patches in, but with the dtsi bits not being picked up.

Quoted 6 lines

Quoted 4 lines

That wouldn't be possible unless we merged the "bad" commit introducing the GPU node to sm8650.dtsi into msm-next but not the fix. So yeah, it's going to require a lot of careful cooperation but it should be possible to avoid that happening.

Well, the GPU node is already there in the linux-next.

And? As long as the devicetree fix lands first, linux-next will never be broken.

Quoted 2 lines

Anyway. Please. Don't break compat with old DTS. That is a rule of thumb.

It's exactly that, a rule of thumb. This is obviously a bit of an exceptional case, and you haven't articulated any reason why we should follow it in this case when there's an obvious reason not to.

Quoted 200 lines · Connor Abbott

Quoted 196 lines · Dmitry Baryshkov

Quoted 157 lines · Connor Abbott

Quoted 150 lines · Dmitry Baryshkov

Quoted 142 lines · Connor Abbott

Quoted 111 lines · Dmitry Baryshkov

Quoted 109 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +57 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,
+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+

Quoted 8 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 4 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +4 -0

+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

You mean to duplicate the qcom_scm_is_available check and qcom_scm_

Quoted 16 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 12 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +11 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */
+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi

Quoted 5 lines

I don't see how this is an issue. msm-next is currently based on 6.9, which doesn't have the GPU defined in sm8650.dtsi. AFAIK patches 1 and 2 will have to go through the linux-arm-msm tree, which will have to be merged into msm-next before this patch lands there, so there will never be any breakage.

Quoted 3 lines

linux-arm-msm isn't going to be merged into msm-next. If we do not ask for ack for the fix to go through msm-next, they will get these patches in parallel.

Quoted 9 lines

I'm not familiar with how complicated cross-tree changes like this get merged, but why would we merge these in parallel given that this patch depends on the previous patch that introduces qcom_scm_gpu_init_regs(), and that would (I assume?) normally go through the same tree as patch 1? Even if patch 1 gets merged in parallel in linux-arm-msm, in what scenario would we have a broken boot? You won't have a devicetree with a working sm8650 GPU and drm/msm with raytracing until linux-arm-msm is merged into msm-next at which point patch 1 will have landed somehow.

arch/arm64/qcom/dts and drivers/firmware/qcom are two separate trees. So yes, this needs a lot of coordination.

Quoted 11 lines

Quoted 11 lines

Another option is to get dtsi fix into 6.9 and delay the raytracing until 6.10-rc which doesn't make a lot of sense from my POV).

Quoted 5 lines

Quoted 3 lines

(not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

That policy only applies to released kernels, so that's irrelevant here.

Quoted 7 lines

Quoted 2 lines

It applies to all kernels, the reason being pretty simple: git-bisect should not be broken.

As I wrote above, this is not an issue. The point I was making is that mixing and matching dtb's from one unmerged subsystem tree and a kernel from another isn't supported AFAIK, and that's the only scenario where this could break.

And it can happen if somebody running a bisect ends up in the branch with these patches in, but with the dtsi bits not being picked up.

Quoted 4 lines

That wouldn't be possible unless we merged the "bad" commit introducing the GPU node to sm8650.dtsi into msm-next but not the fix. So yeah, it's going to require a lot of careful cooperation but it should be possible to avoid that happening.

Well, the GPU node is already there in the linux-next.

Anyway. Please. Don't break compat with old DTS. That is a rule of thumb.

Quoted 103 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +51 -1

index cf0b1de1c071..fb2722574ae5 100644
@@ -10,6 +10,7 @@
 
 #include <linux/bitfield.h>
 #include <linux/devfreq.h>
+#include <linux/firmware/qcom/qcom_scm.h>
 #include <linux/pm_domain.h>
 #include <linux/soc/qcom/llcc-qcom.h>
 

@@ -1686,7 +1687,8 @@ static int a6xx_zap_shader_init(struct msm_gpu *gpu)
                       A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
                       A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
                       A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR | \
-                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR)
+                      A6XX_RBBM_INT_0_MASK_TSBWRITEERROR | \
+                      A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
 
 #define A7XX_APRIV_MASK (A6XX_CP_APRIV_CNTL_ICACHE | \
                         A6XX_CP_APRIV_CNTL_RBFETCH | \

@@ -2356,6 +2358,26 @@ static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
        kthread_queue_work(gpu->worker, &gpu->recover_work);
 }
 
+static void a7xx_sw_fuse_violation_irq(struct msm_gpu *gpu)
+{
+       u32 status;
+
+       status = gpu_read(gpu, REG_A7XX_RBBM_SW_FUSE_INT_STATUS);
+       gpu_write(gpu, REG_A7XX_RBBM_SW_FUSE_INT_MASK, 0);
+
+       dev_err_ratelimited(&gpu->pdev->dev, "SW fuse violation status=%8.8x\n", status);
+
+       /* Ignore FASTBLEND violations, because the HW will silently fall back
+        * to legacy blending.
+        */
+       if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                     A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {
+               del_timer(&gpu->hangcheck_timer);
+
+               kthread_queue_work(gpu->worker, &gpu->recover_work);
+       }
+}
+
 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 {
        struct msm_drm_private *priv = gpu->dev->dev_private;

@@ -2384,6 +2406,9 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
        if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
                dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
 
+       if (status & A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION)
+               a7xx_sw_fuse_violation_irq(gpu);
+
        if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
                msm_gpu_retire(gpu);
 

@@ -2525,6 +2550,60 @@ static void a6xx_llc_slices_init(struct platform_device *pdev,
                a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
 }
 
+static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu)
+{
+       struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
+       struct msm_gpu *gpu = &adreno_gpu->base;
+       u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ;
+       u32 fuse_val;
+       int ret;
+
+       if (adreno_is_a740(adreno_gpu)) {
+               /* Raytracing is always enabled on a740 */
+               adreno_gpu->has_ray_tracing = true;
+       }
+
+       if (!qcom_scm_is_available()) {
+               /* Assume that if qcom scm isn't available, that whatever
+                * replacement allows writing the fuse register ourselves.
+                * Users of alternative firmware need to make sure this
+                * register is writeable or indicate that it's not somehow.
+                * Print a warning because if you mess this up you're about to
+                * crash horribly.
+                */
+               if (adreno_is_a750(adreno_gpu)) {
+                       dev_warn_once(gpu->dev->dev,
+                               "SCM is not available, poking fuse register\n");
+                       a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE,

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2587

Quoted 10 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +10 -0

+                               A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND |
+                               A7XX_CX_MISC_SW_FUSE_VALUE_LPAC);
+                       adreno_gpu->has_ray_tracing = true;
+               }
+
+               return 0;
+       }
+
+       if (adreno_is_a750(adreno_gpu))

Most of the function is under the if (adreno_is_a750) conditions. Can we invert the logic and add a single block of if(adreno_is_a750) and then place all the code underneath?

Quoted 9 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +9 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */

drivers/gpu/drm/msm/adreno/a6xx_gpu.c static void a6xx_llc_slices_init(struct platform_device *pdev, · line 2598

Quoted 2 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +2 -0

+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi (not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

Quoted 40 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +16 -0

+               adreno_gpu->has_ray_tracing =
+                       !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING);
+       }
+
+       return 0;
+}
+
+
 #define GBIF_CLIENT_HALT_MASK          BIT(0)
 #define GBIF_ARB_HALT_MASK             BIT(1)
 #define VBIF_XIN_HALT_CTRL0_MASK       GENMASK(3, 0)

@@ -3094,6 +3173,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
                return ERR_PTR(ret);
        }
 
+       if (adreno_is_a7xx(adreno_gpu)) {
+               ret = a7xx_cx_mem_init(a6xx_gpu);
+               if (ret) {
+                       a6xx_destroy(&(a6xx_gpu->base.base));
+                       return ERR_PTR(ret);
+               }
+       }
+
        if (gpu->aspace)
                msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
                                a6xx_fault_handler);

drivers/gpu/drm/msm/adreno/adreno_gpu.h +2 -1

index 77526892eb8c..4180f3149dd8 100644
@@ -182,6 +182,8 @@ struct adreno_gpu {
         */
        const unsigned int *reg_offsets;
        bool gmu_is_wrapper;
+
+       bool has_ray_tracing;
 };
 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
 
--

Quoted 2 lines

2.31.1

--
With best wishes
Dmitry

Quoted 17 lines · Dmitry Baryshkov

Quoted 15 lines · Connor Abbott

On all Qualcomm platforms with a7xx GPUs, qcom_scm provides a method to initialize cx_mem. Copy this from downstream (minus BCL which we currently don't support). On a750, this includes a new "fuse" register which can be used by qcom_scm to fuse off certain features like raytracing in software. The fuse is default off, and is initialized by calling the method. Afterwards we have to read it to find out which features were enabled.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c   | 89 ++++++++++++++++++++++++-
 drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +
 2 files changed, 90 insertions(+), 1 deletion(-)

Quoted 9 lines

Quoted 9 lines

drivers/gpu/drm/msm/adreno/a6xx_gpu.c +9 -0

+               gpu_req |= QCOM_SCM_GPU_TSENSE_EN_REQ;
+
+       ret = qcom_scm_gpu_init_regs(gpu_req);
+       if (ret)
+               return ret;
+
+       /* On a750 raytracing may be disabled by the firmware, find out whether
+        * that's the case. The scm call above sets the fuse register.
+        */

Quoted 8 lines

Review

Quoted 2 lines

(quoted diff) +2 -0

+       if (adreno_is_a750(adreno_gpu)) {
+               fuse_val = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE);

This register isn't accessible with the current sm8650.dtsi. Since DT and driver are going through different trees, please add safety guards here, so that the driver doesn't crash if used with older dtsi (not to mention that dts is considered to be an ABI and newer kernels are supposed not to break with older DT files).

I'd be happy if older kernels consistently worked with newer dtb, the other direction is too much to ask.

If necessary we can ask for ack
to land the dts fix thru msm-next somehow, but since the gpu is newly enabled device landing in the same merge window I think that is not necessary.

Expose the value of the software fuse to userspace.

Signed-off-by Connor Abbott <[email protected]>

---
 drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +++
 include/uapi/drm/msm_drm.h              | 1 +
 2 files changed, 4 insertions(+)

On a750, Qualcomm decided to gate support for certain features behind a "software fuse." This consists of a register in the cx_mem zone, which is normally only writeable by the TrustZone firmware. On bootup it is 0, and we must call an SCM method to initialize it. Then we communicate its value to userspace. This implements all of this, copying the SCM call from the downstream kernel and kgsl.

So far the only optional feature we use is ray tracing (i.e. the "ray_intersection" instruction) in a pending Mesa MR [1], so that's what we expose to userspace. There's one extra patch to write some missing registers, which depends on the register XML bump but is otherwise unrelated, I just included it to make things easier on myself.

The drm/msm part of this series depends on [2] to avoid conflicts.

[1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28447
[2] https://lore.kernel.org/all/[email protected]/T/

Connor Abbott (6):
arm64: dts: qcom: sm8650: Fix GPU cx_mem size
firmware: qcom_scm: Add gpu_init_regs call

drm/msm: Update a6xx registers
drm/msm/a7xx: Initialize a750 "software fuse" drm/msm: Add MSM_PARAM_RAYTRACING uapi drm/msm/a7xx: Add missing register writes from downstream