FAILED: patch "[PATCH] serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level" failed to apply to 5.10-stable tree
Subsystems (2)
[email protected]
maintainerThe patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.10.y
git checkout FETCH_HEAD
git cherry-pick -x 5208e7ced520a813b4f4774451fbac4e517e78b2
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2024061757-squid-skating-bd26@gregkh' --subject-prefix 'PATCH 5.10.y' HEAD^..
Possible dependencies:
5208e7ced520 ("serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level") cc6628f07e0d ("serial: 8250_pxa: Switch to use uart_read_port_properties()")
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 5208e7ced520a813b4f4774451fbac4e517e78b2 Mon Sep 17 00:00:00 2001
From: Doug Brown <[email protected]>
Date: Sun, 19 May 2024 12:19:30 -0700
Subject: [PATCH] serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level
The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32 bytes when a TX interrupt occurs.
This fixes a problem observed on the PXA168 that dropped a bunch of TX bytes during large transmissions.
drivers/tty/serial/8250/8250_pxa.c +1 -0
@@ -125,6 +125,7 @@ static int serial_pxa_probe(struct platform_device *pdev) uart.port.iotype =UPIO_MEM32 ; uart.port.regshift =2 ; uart.port.fifosize =64 ; + uart.tx_loadsz =32 ; uart.dl_write = serial_pxa_dl_write; ret =serial8250_register_8250_port (&uart);
PATCH 1/1 serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level
The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32 bytes when a TX interrupt occurs.
This fixes a problem observed on the PXA168 that dropped a bunch of TX bytes during large transmissions.
--- drivers/tty/serial/8250/8250_pxa.c | 1 + 1 file changed, 1 insertion(+)
drivers/tty/serial/8250/8250_pxa.c +1 -0
@@ -125,6 +125,7 @@ static int serial_pxa_probe(struct platform_device *pdev) uart.port.regshift =2 ; uart.port.irq = irq; uart.port.fifosize =64 ; + uart.tx_loadsz =32 ; uart.port.flags =UPF_IOREMAP |UPF_SKIP_TEST |UPF_FIXED_TYPE ; uart.port.dev = &pdev->dev; uart.port.uartclk =clk_get_rate (data->clk);
Signature · 1 line
2.34.1