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dt-bindings: PCI: altera: Convert to YAML

PATCH Applied [email protected] 3 participants 3 messages Jul 2, 2024 – Sep 4, 2024

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Device tree bindings PCI PCI native host bridge and endpoint drivers PCI driver for Altera PCIe IP
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PATCH v8 1/1 dt-bindings: PCI: altera: Convert to YAML

From: Matthew Gerlach <[email protected]>

Convert the device tree bindings for the Altera Root Port PCIe controller from text to YAML. Update the entries in the interrupt-map field to have the correct number of address cells for the interrupt parent.

Signed-off-by Matthew Gerlach <[email protected]>

---
v8:
- Precisely constrain the number of items for reg and reg-names properties. Constrain maxItems to 2 for altr,pcie-root-port-1.0. Constrain minItems to 3 for altr,pcie-root-port-2.0.

v7:
- Keep original example dts, but fix warnings of interrupt-map field.

v6:
- Fix dt_binding_check warnings by creating interrupt-controller subnode and fixing interrupt-map.
- Updated filename in MAINTAINERS.

v5:
- add interrupt-controller #interrupt-cells to required field
- don't touch original example dts

v4:
- reorder reg-names to match original binding
- move reg and reg-names to top level with limits.

v3:
- Added years to copyright
- Correct order in file of allOf and unevaluatedProperties
- remove items: in compatible field
- fix reg and reg-names constraints
- replace deprecated pci-bus.yaml with pci-host-bridge.yaml
- fix entries in ranges property
- remove device_type from required

v2:
- Move allOf: to bottom of file, just like example-schema is showing
- add constraint for reg and reg-names
- remove unneeded device_type
- drop #address-cells and #size-cells
- change minItems to maxItems for interrupts:
- change msi-parent to just "msi-parent: true"
- cleaned up required:
- make subject consistent with other commits coverting to YAML
- s/overt/onvert/g

v8 fix

---
 .../devicetree/bindings/pci/altera-pcie.txt   |  50 --------
 .../bindings/pci/altr,pcie-root-port.yaml     | 114 ++++++++++++++++++
 MAINTAINERS                                   |   2 +-
 3 files changed, 115 insertions(+), 51 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
 create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
Documentation/devicetree/bindings/pci/altera-pcie.txt deleted +0 -50
deleted file mode 100644
index 816b244a221e..000000000000
@@ -1,50 +0,0 @@
-* Altera PCIe controller
-
-Required properties:
-- compatible :	should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
-- reg:		a list of physical base address and length for TXS and CRA.
-		For "altr,pcie-root-port-2.0", additional HIP base address and length.
-- reg-names:	must include the following entries:
-		"Txs": TX slave port region
-		"Cra": Control register access region
-		"Hip": Hard IP region (if "altr,pcie-root-port-2.0")
-- interrupts:	specifies the interrupt source of the parent interrupt
-		controller.  The format of the interrupt specifier depends
-		on the parent interrupt controller.
-- device_type:	must be "pci"
-- #address-cells:	set to <3>
-- #size-cells:		set to <2>
-- #interrupt-cells:	set to <1>
-- ranges:	describes the translation of addresses for root ports and
-		standard PCI regions.
-- interrupt-map-mask and interrupt-map: standard PCI properties to define the
-		mapping of the PCIe interface to interrupt numbers.
-
-Optional properties:
-- msi-parent:	Link to the hardware entity that serves as the MSI controller
-		for this PCIe controller.
-- bus-range:	PCI bus numbers covered
-
-Example
-	pcie_0: pcie@c00000000 {
-		compatible = "altr,pcie-root-port-1.0";
-		reg = <0xc0000000 0x20000000>,
-			<0xff220000 0x00004000>;
-		reg-names = "Txs", "Cra";
-		interrupt-parent = <&hps_0_arm_gic_0>;
-		interrupts = <0 40 4>;
-		interrupt-controller;
-		#interrupt-cells = <1>;
-		bus-range = <0x0 0xFF>;
-		device_type = "pci";
-		msi-parent = <&msi_to_gic_gen_0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie_0 1>,
-			            <0 0 0 2 &pcie_0 2>,
-			            <0 0 0 3 &pcie_0 3>,
-			            <0 0 0 4 &pcie_0 4>;
-		ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
-			  0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
-	};
Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml new file +114 -0

114 lines not on this page · raw message

MAINTAINERS +1 -1
index cbc186250383..ff2d2c110e41 100644
@@ -17274,7 +17274,7 @@ PCI DRIVER FOR ALTERA PCIE IP
 M:	Joyce Ooi <[email protected]>
 L:	[email protected]
 S:	Supported
-F:	Documentation/devicetree/bindings/pci/altera-pcie.txt
+F:	Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
 F:	drivers/pci/controller/pcie-altera.c
 
 PCI DRIVER FOR APPLIEDMICRO XGENE
Signature · 1 line
2.34.1
Reviewed-by on v8 1/1
#1 lore raw
Quoted 6 lines · On Tue, Jul 02, 2024 at 11:26:52AM -0500, [email protected] wrote:

From: Matthew Gerlach <[email protected]>

Convert the device tree bindings for the Altera Root Port PCIe controller from text to YAML. Update the entries in the interrupt-map field to have the correct number of address cells for the interrupt parent.

Quoted 6 lines
Signed-off-by Matthew Gerlach <[email protected]>

---
v8:
- Precisely constrain the number of items for reg and reg-names properties. Constrain maxItems to 2 for altr,pcie-root-port-1.0. Constrain minItems to 3 for altr,pcie-root-port-2.0.

Thanks for the update,

Reviewed-by Conor Dooley <[email protected]>

Cheers,
Conor.