powerpc-64e-drop-e500-ifdefs-in-64-bit-code.patch removed from -mm tree
The quilt patch titled
Subject: powerpc/64e: drop E500 ifdefs in 64-bit code
has been removed from the -mm tree. Its filename was
powerpc-64e-drop-e500-ifdefs-in-64-bit-code.patch
This patch was dropped because it was merged into the mm-stable branch of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm
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From: Michael Ellerman <[email protected]>
Subject: powerpc/64e: drop E500 ifdefs in 64-bit code
Date: Tue, 2 Jul 2024 15:51:15 +0200
All 64-bit Book3E have E500=y, so drop the unneeded ifdefs.
Link https://lkml.kernel.org/r/7fb88809c88a1b774063eda602a9333079403f83.1719928057.git.christophe.leroy@csgroup.eu open here
Signed-off-by Michael Ellerman <[email protected]>
Signed-off-by Christophe Leroy <[email protected]>
Cc Jason Gunthorpe <[email protected]>
Cc Nicholas Piggin <[email protected]>
Cc Oscar Salvador <[email protected]>
Cc Peter Xu <[email protected]>
Signed-off-by Andrew Morton <[email protected]>
---
arch/powerpc/mm/nohash/tlb_64e.c | 12 ------------ 1 file changed, 12 deletions(-)
arch/powerpc/mm/nohash/tlb_64e.c renamed from arch/powerpc/mm/nohash/tlb_64e.c~powerpc-64e-drop-e500-ifdefs-in-64-bit-code +0 -12
@@ -85,7 +85,6 @@ static void __init setup_page_sizes(voidunsigned int eptcfg;int psize; -#ifdef CONFIG_PPC_E500 unsigned int mmucfg =mfspr (SPRN_MMUCFG );int fsl_mmu =mmu_has_feature (MMU_FTR_TYPE_FSL_E );
@@ -151,7 +150,6 @@ static void __init setup_page_sizes(void goto out; } -#endif out:/* Cleanup array and print summary */ pr_info ("MMU: Supported page sizes\n" );
@@ -180,13 +178,11 @@ static void __init setup_mmu_htw(void)*/ switch (book3e_htw_mode) { -#ifdef CONFIG_PPC_E500 case PPC_HTW_E6500 : extlb_level_exc =EX_TLB_SIZE ;patch_exception (0x1c0 , exc_data_tlb_miss_e6500_book3e);patch_exception (0x1e0 , exc_instruction_tlb_miss_e6500_book3e);break ; -#endif }pr_info ("MMU: Book3E HW tablewalk %s\n" , book3e_htw_mode !=PPC_HTW_NONE ?"enabled" :"not supported" );
@@ -217,7 +213,6 @@ static void early_init_this_mmu(void) }mtspr (SPRN_MAS4 , mas4); -#ifdef CONFIG_PPC_E500 if (mmu_has_feature (MMU_FTR_TYPE_FSL_E )) {unsigned int num_cams;bool map = true;
@@ -238,7 +233,6 @@ static void early_init_this_mmu(void) linear_map_top =map_mem_in_cams (linear_map_top, num_cams, false, true); } -#endif /* A sync won't hurt us after mucking around with * the MMU configuration
@@ -270,7 +264,6 @@ static void __init early_init_mmu_global/* Look for HW tablewalk support */ setup_mmu_htw (); -#ifdef CONFIG_PPC_E500 if (mmu_has_feature (MMU_FTR_TYPE_FSL_E )) {if (book3e_htw_mode ==PPC_HTW_NONE ) { extlb_level_exc =EX_TLB_SIZE ;
@@ -279,7 +272,6 @@ static void __init early_init_mmu_global exc_instruction_tlb_miss_bolted_book3e); } } -#endif /* Set the global containing the top of the linear mapping * for use by the TLB miss code
@@ -291,7 +283,6 @@ static void __init early_init_mmu_globalstatic void __init early_mmu_set_memory_limit (void ) { -#ifdef CONFIG_PPC_E500 if (mmu_has_feature (MMU_FTR_TYPE_FSL_E )) {/* * Limit memory so we dont have linear faults.
@@ -302,7 +293,6 @@ static void __init early_mmu_set_memory_*/ memblock_enforce_memory_limit (linear_map_top); } -#endif memblock_set_current_limit (linear_map_top); }
@@ -340,7 +330,6 @@ void setup_initial_memory_limit(phys_add* We crop it to the size of the first MEMBLOCK to * avoid going over total available memory just in case... */ -#ifdef CONFIG_PPC_E500 if (early_mmu_has_feature (MMU_FTR_TYPE_FSL_E )) {unsigned long linear_sz;unsigned int num_cams;
@@ -353,7 +342,6 @@ void setup_initial_memory_limit(phys_add ppc64_rma_size =min_t (u64, linear_sz,0x40000000 ); }else -#endif ppc64_rma_size =min_t (u64, first_memblock_size,0x40000000 );/* Finally limit subsequent allocations */
_
Patches currently in -mm which might be from [email protected] are