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pinctrl: npcm8xx: pin configuration changes

PATCH Superseded Tomer Maimon 2 participants 11 messages Jul 18, 2024 – Jul 26, 2024

Subsystems (3)
Device tree bindings Pin control Arm/nuvoton npcm architecture

v2 of 3 Superseded Latest is v3 →

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Tomer Maimon

author maintainer
#0 lore raw

v2 cover pinctrl: npcm8xx: pin configuration changes

This patch set addresses various pin configuration changes for the Nuvoton NPCM8XX BMC SoC. The patches aim to enhance functionality, remove unused pins, and improve overall pin management.

This patchset is on the upstream process to the Linux vanilla.
https://lore.kernel.org/lkml/[email protected]/

Changes since version 1:
- Squash the non-existent pins, groups and functions.
- Remove non-existent groups and functions from dt-bindings.
- Modify the commit message.

Tomer Maimon (7):
dt-bindings: pinctrl: npcm8xx: remove non-existent groups and
functions
pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions
pinctrl: nuvoton: npcm8xx: clear polarity before set both edge
pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36
pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group
pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration
pinctrl: nuvoton: npcm8xx: modify pins flags

 .../pinctrl/nuvoton,npcm845-pinctrl.yaml      | 74 +++++++++----------
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c     | 64 ++++++++--------
 2 files changed, 67 insertions(+), 71 deletions(-)
Signature · 1 line
2.34.1
author maintainer
#1 lore raw

PATCH v2 1/7 dt-bindings: pinctrl: npcm8xx: remove non-existent groups and functions

Remove non-existent smb4den and lpcclk groups and functions from Nuvoton NPCM8XX Pin controller binding documentation.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../pinctrl/nuvoton,npcm845-pinctrl.yaml      | 74 +++++++++----------
 1 file changed, 36 insertions(+), 38 deletions(-)
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +36 -38
index e4b9f3da2cf0..4496658006ab 100644
@@ -70,49 +70,47 @@ patternProperties:
           One or more groups of pins to mux to a certain function
         items:
           enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
-                  smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
-                  smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
-                  smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
-                  spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
-                  spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
-                  bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
-                  r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
-                  fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
-                  fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
-                  pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
-                  ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
-                  smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
-                  sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
-                  mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
-                  scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
-                  spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
-                  smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
-                  spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
-                  hgpio5, hgpio6, hgpio7 ]
+                  smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
+                  smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
+                  smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
+                  spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
+                  smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
+                  bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
+                  fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
+                  fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
+                  fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
+                  r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
+                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
+                  smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
+                  pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
+                  mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
+                  faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
+                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1 
+                  wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
+                  hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
 
       function:
         description:
           The function that a group of pins is muxed to
         enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
-                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b,
-                smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21,
-                smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3,
-                spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2,
-                spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2,
-                bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen,
-                r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3,
-                fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
-                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
-                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
-                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
-                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
-                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
-                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk,
-                scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1,
-                spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den,
-                smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix,
-                spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
-                hgpio5, hgpio6, hgpio7 ]
+                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
+                smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
+                smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
+                spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
+                smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
+                bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
+                fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
+                fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
+                fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
+                r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
+                i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
+                smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
+                pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
+                mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
+                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
+                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1 
+                wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
+                hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
 
     dependencies:
       groups: [ function ]
Signature · 1 line
2.34.1
author maintainer
#2 lore raw

PATCH v2 2/7 pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions

In reply to Tomer Maimon

Remove non-existent smb4den abd lpcclk pins, groups and functions on the Nuvoton NPCM8XX BMC SoC.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +2 -10
index da21f6a45888..e146c161076c 100644
@@ -442,7 +442,6 @@ static const int smb4_pins[]  = { 28, 29 };
 static const int smb4b_pins[] = { 18, 19 };
 static const int smb4c_pins[] = { 20, 21 };
 static const int smb4d_pins[] = { 22, 23 };
-static const int smb4den_pins[] = { 17 };
 static const int smb5_pins[]  = { 26, 27 };
 static const int smb5b_pins[] = { 13, 12 };
 static const int smb5c_pins[] = { 15, 14 };

@@ -575,7 +574,6 @@ static const int spi3cs3_pins[] = { 189 };
 static const int ddc_pins[] = { 204, 205, 206, 207 };
 
 static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };
-static const int lpcclk_pins[] = { 168 };
 static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };
 
 static const int lkgpo0_pins[] = { 16 };

@@ -704,7 +702,6 @@ struct npcm8xx_pingroup {
 	NPCM8XX_GRP(smb4b), \
 	NPCM8XX_GRP(smb4c), \
 	NPCM8XX_GRP(smb4d), \
-	NPCM8XX_GRP(smb4den), \
 	NPCM8XX_GRP(smb5), \
 	NPCM8XX_GRP(smb5b), \
 	NPCM8XX_GRP(smb5c), \

@@ -813,7 +810,6 @@ struct npcm8xx_pingroup {
 	NPCM8XX_GRP(spi3cs3), \
 	NPCM8XX_GRP(spi0cs1), \
 	NPCM8XX_GRP(lpc), \
-	NPCM8XX_GRP(lpcclk), \
 	NPCM8XX_GRP(espi), \
 	NPCM8XX_GRP(lkgpo0), \
 	NPCM8XX_GRP(lkgpo1), \

@@ -953,7 +949,6 @@ NPCM8XX_SFUNC(smb4);
 NPCM8XX_SFUNC(smb4b);
 NPCM8XX_SFUNC(smb4c);
 NPCM8XX_SFUNC(smb4d);
-NPCM8XX_SFUNC(smb4den);
 NPCM8XX_SFUNC(smb5);
 NPCM8XX_SFUNC(smb5b);
 NPCM8XX_SFUNC(smb5c);

@@ -1061,7 +1056,6 @@ NPCM8XX_SFUNC(spi3cs2);
 NPCM8XX_SFUNC(spi3cs3);
 NPCM8XX_SFUNC(spi0cs1);
 NPCM8XX_SFUNC(lpc);
-NPCM8XX_SFUNC(lpcclk);
 NPCM8XX_SFUNC(espi);
 NPCM8XX_SFUNC(lkgpo0);
 NPCM8XX_SFUNC(lkgpo1);

@@ -1177,7 +1171,6 @@ static struct npcm8xx_func npcm8xx_funcs[] = {
 	NPCM8XX_MKFUNC(smb4b),
 	NPCM8XX_MKFUNC(smb4c),
 	NPCM8XX_MKFUNC(smb4d),
-	NPCM8XX_MKFUNC(smb4den),
 	NPCM8XX_MKFUNC(smb5),
 	NPCM8XX_MKFUNC(smb5b),
 	NPCM8XX_MKFUNC(smb5c),

@@ -1285,7 +1278,6 @@ static struct npcm8xx_func npcm8xx_funcs[] = {
 	NPCM8XX_MKFUNC(spi3cs3),
 	NPCM8XX_MKFUNC(spi0cs1),
 	NPCM8XX_MKFUNC(lpc),
-	NPCM8XX_MKFUNC(lpcclk),
 	NPCM8XX_MKFUNC(espi),
 	NPCM8XX_MKFUNC(lkgpo0),
 	NPCM8XX_MKFUNC(lkgpo1),

@@ -1352,7 +1344,7 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(14,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(15,	gspi, MFSEL1, 24,	smb5c, I2CSEGSEL, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(16,	lkgpo0, FLOCKR1, 0,	smb7b, I2CSEGSEL, 27,	tp_gpio2b, MFSEL7, 10,	none, NONE, 0,		none, NONE, 0,		SLEW),
-	NPCM8XX_PINCFG(17,	pspi, MFSEL3, 13,	cp1gpio5, MFSEL6, 7,	smb4den, I2CSEGSEL, 23,	none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(17,	pspi, MFSEL3, 13,	cp1gpio5, MFSEL6, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(18,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(19,	pspi, MFSEL3, 13,	smb4b, I2CSEGSEL, 14,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(20,	hgpio0,	MFSEL2, 24,	smb15, MFSEL3, 8,	smb4c, I2CSEGSEL, 15,	none, NONE, 0,		none, NONE, 0,		SLEW),

@@ -1501,7 +1493,7 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(165,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(166,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(167,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(168,	lpcclk, MFSEL1, 31,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
+	NPCM8XX_PINCFG(168,	none, NONE, 0,		espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(169,	scipme, MFSEL3, 0,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(170,	smi, MFSEL1, 22,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(171,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
Signature · 1 line
2.34.1
author maintainer
#3 lore raw

PATCH v2 3/7 pinctrl: nuvoton: npcm8xx: clear polarity before set both edge

In reply to Tomer Maimon

Clear polarity before setting both edges to ensure that the polarity is in the same state before configuring events for both edges

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1 +
 1 file changed, 1 insertion(+)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -0
index e146c161076c..ea36b044240a 100644
@@ -246,6 +246,7 @@ static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)
 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
 		break;
 	case IRQ_TYPE_EDGE_BOTH:
+		npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio);
 		npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio);
 		break;
 	case IRQ_TYPE_LEVEL_LOW:
Signature · 1 line
2.34.1
author maintainer
#4 lore raw

PATCH v2 4/7 pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36

In reply to Tomer Maimon

This patch adds support for GPIO pins GPI35 and GPI36 on the Nuvoton NPCM8xx BMC SoC.

The pins are configured for only for input.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +7 -3
index ea36b044240a..fe9d18b10dd1 100644
@@ -321,8 +321,8 @@ static struct irq_chip npcmgpio_irqchip = {
 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
-static const int gpi36_pins[] = { 58 };
-static const int gpi35_pins[] = { 58 };
+static const int gpi36_pins[] = { 36 };
+static const int gpi35_pins[] = { 35 };
 
 static const int tp_jtag3_pins[] = { 44, 62, 45, 46 };
 static const int tp_uart_pins[] = { 50, 51 };

@@ -1363,6 +1363,8 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(32,	spi0cs1, MFSEL1, 3,	smb14b, MFSEL7, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(33,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(34,	i3c4, MFSEL6, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(35,	gpi35, MFSEL5, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
+	NPCM8XX_PINCFG(36,	gpi36, MFSEL5, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(37,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(38,	smb3c, I2CSEGSEL, 12,	smb23, MFSEL5, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(39,	smb3b, I2CSEGSEL, 11,	smb22, MFSEL5, 30,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),

@@ -1608,6 +1610,8 @@ static const struct pinctrl_pin_desc npcm8xx_pins[] = {
 	PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"),
 	PINCTRL_PIN(33, "GPIO33/I3C4_SCL"),
 	PINCTRL_PIN(34, "GPIO34/I3C4_SDA"),
+	PINCTRL_PIN(35, "MCBPCK/GPI35_AHB2PCI_DIS"),
+	PINCTRL_PIN(36, "SYSBPCK/GPI36"),
 	PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"),
 	PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"),
 	PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"),

@@ -2042,7 +2046,7 @@ static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev,
 	const unsigned int *pin = &offset;
 	int mode = fn_gpio;
 
-	if (pin[0] >= 183 && pin[0] <= 189)
+	if ((pin[0] >= 183 && pin[0] <= 189) || pin[0] == 35 || pin[0] == 36)
 		mode = pincfg[pin[0]].fn0;
 
 	npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode);
Signature · 1 line
2.34.1
author maintainer
#5 lore raw

PATCH v2 5/7 pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group

In reply to Tomer Maimon

Add pin 250 to DDR pins group on the Nuvoton NPCM8xx BMC SoC.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +2 -1
index fe9d18b10dd1..87830ae15be2 100644
@@ -520,7 +520,7 @@ static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
 static const int rg2mdio_pins[] = { 216, 217 };
 
 static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,
-	213, 214, 215, 216, 217 };
+	213, 214, 215, 216, 217, 250 };
 
 static const int iox1_pins[] = { 0, 1, 2, 3 };
 static const int iox2_pins[] = { 4, 5, 6, 7 };

@@ -1567,6 +1567,7 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(245,	i3c2, MFSEL5, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(246,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(247,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(250,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(251,	jm2, MFSEL5, 1,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(253,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC1 power */
 	NPCM8XX_PINCFG(254,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC2 power */
Signature · 1 line
2.34.1
author maintainer
#6 lore raw

PATCH v2 6/7 pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration

In reply to Tomer Maimon

Modify clkrun and serirq pin configuration on the Nuvoton NPCM8XX BMC SoC.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +2 -2
index 87830ae15be2..bcaf5c9f3c37 100644
@@ -1490,13 +1490,13 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(159,	mmc, MFSEL3, 10,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(160,	clkout, MFSEL1, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(161,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(162,	serirq, MFSEL1, 31,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
+	NPCM8XX_PINCFG(162,	clkrun, MFSEL3, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
 	NPCM8XX_PINCFG(163,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(164,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(165,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(166,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(167,	lpc, MFSEL1, 26,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(168,	none, NONE, 0,		espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
+	NPCM8XX_PINCFG(168,	serirq, MFSEL1, 31,	espi, MFSEL4, 8,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(169,	scipme, MFSEL3, 0,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(170,	smi, MFSEL1, 22,	smb21, MFSEL5, 29,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(171,	smb6, MFSEL3, 1,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
Signature · 1 line
2.34.1
author maintainer
#7 lore raw

PATCH v2 7/7 pinctrl: nuvoton: npcm8xx: modify pins flags

In reply to Tomer Maimon

Modify the following pins flags on the Nuvoton NPCM8XX BMC:
- Add pins 110-113, 187, 191, 192, 194-199, 202 SLEW flag
- Add pins 229 and 230 GPO flag.
- Remove pin 233 SLEWLPC flag.
- Remove pin 251 SLEW flag.

Signed-off-by Tomer Maimon <[email protected]>
---
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 36 +++++++++++------------
 1 file changed, 18 insertions(+), 18 deletions(-)
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +18 -18
index bcaf5c9f3c37..607960fdbc40 100644
@@ -1438,10 +1438,10 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(107,	i3c5, MFSEL3, 22,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(108,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(109,	sg1mdio, MFSEL4, 21,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
-	NPCM8XX_PINCFG(110,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(111,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(112,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(113,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
+	NPCM8XX_PINCFG(110,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(111,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(112,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(113,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(114,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(115,	smb0, MFSEL1, 6,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(116,	smb1, MFSEL1, 7,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),

@@ -1515,22 +1515,22 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(184,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(185,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(186,	gpio1836, MFSEL6, 19,	spi3, MFSEL4, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
-	NPCM8XX_PINCFG(187,	gpo187, MFSEL7, 24,	smb14b, MFSEL7, 26,	spi3cs1, MFSEL4, 17,	none, NONE, 0,		none, NONE, 0,		0),
+	NPCM8XX_PINCFG(187,	gpo187, MFSEL7, 24,	smb14b, MFSEL7, 26,	spi3cs1, MFSEL4, 17,	none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(188,	gpio1889, MFSEL7, 25,	spi3cs2, MFSEL4, 18,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(189,	gpio1889, MFSEL7, 25,	spi3cs3, MFSEL4, 19,	spi3quad, MFSEL4, 20,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(190,	nprd_smi, FLOCKR1, 20,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(2, 4)),
-	NPCM8XX_PINCFG(191,	spi1d23, MFSEL5, 3,	spi1cs2, MFSEL5, 4,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		DSTR(0, 2)),  /* XX */
-	NPCM8XX_PINCFG(192,	spi1d23, MFSEL5, 3,	spi1cs3, MFSEL5, 5,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		DSTR(0, 2)),  /* XX */
+	NPCM8XX_PINCFG(191,	spi1d23, MFSEL5, 3,	spi1cs2, MFSEL5, 4,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		SLEW),  /* XX */
+	NPCM8XX_PINCFG(192,	spi1d23, MFSEL5, 3,	spi1cs3, MFSEL5, 5,	fm1, MFSEL6, 17,	smb15, MFSEL7, 27,	none, NONE, 0,		SLEW),  /* XX */
 	NPCM8XX_PINCFG(193,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
-	NPCM8XX_PINCFG(194,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
-	NPCM8XX_PINCFG(195,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
-	NPCM8XX_PINCFG(196,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
-	NPCM8XX_PINCFG(197,	smb0den, I2CSEGSEL, 22,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
-	NPCM8XX_PINCFG(198,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
-	NPCM8XX_PINCFG(199,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
+	NPCM8XX_PINCFG(194,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(195,	smb0b, I2CSEGSEL, 0,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(196,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(197,	smb0den, I2CSEGSEL, 22,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(198,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(199,	smb0d, I2CSEGSEL, 2,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(200,	r2, MFSEL1, 14,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
 	NPCM8XX_PINCFG(201,	r1, MFSEL3, 9,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO),
-	NPCM8XX_PINCFG(202,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(0, 1)),
+	NPCM8XX_PINCFG(202,	smb0c, I2CSEGSEL, 1,	fm0, MFSEL6, 16,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(203,	faninx, MFSEL3, 3,	spi1cs0, MFSEL3, 4,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		DSTR(8, 12)),
 	NPCM8XX_PINCFG(208,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */
 	NPCM8XX_PINCFG(209,	rg2, MFSEL4, 24,	ddr, MFSEL3, 26,	rmii3, MFSEL5, 11,	none, NONE, 0,		none, NONE, 0,		SLEW), /* DSCNT */

@@ -1553,10 +1553,10 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(226,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(227,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(228,	spixcs1, MFSEL4, 28,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
-	NPCM8XX_PINCFG(229,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
-	NPCM8XX_PINCFG(230,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
+	NPCM8XX_PINCFG(229,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
+	NPCM8XX_PINCFG(230,	spix, MFSEL4, 27,	fm2, MFSEL6, 18,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPO | DSTR(8, 12) | SLEW),
 	NPCM8XX_PINCFG(231,	clkreq, MFSEL4, 9,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(4, 12) | SLEW),
-	NPCM8XX_PINCFG(233,	spi1cs1, MFSEL5, 0,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEWLPC), /* slewlpc ? */
+	NPCM8XX_PINCFG(233,	spi1cs1, MFSEL5, 0,	fm1, MFSEL6, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0), /* slewlpc ? */
 	NPCM8XX_PINCFG(234,	pwm10, MFSEL6, 13,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(235,	pwm11, MFSEL6, 14,	smb20, MFSEL5, 28,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(240,	i3c0, MFSEL5, 17,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),

@@ -1568,7 +1568,7 @@ static const struct npcm8xx_pincfg pincfg[] = {
 	NPCM8XX_PINCFG(246,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(247,	i3c3, MFSEL5, 23,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
 	NPCM8XX_PINCFG(250,	ddr, MFSEL3, 26,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		DSTR(8, 12) | SLEW),
-	NPCM8XX_PINCFG(251,	jm2, MFSEL5, 1,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		SLEW),
+	NPCM8XX_PINCFG(251,	jm2, MFSEL5, 1,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		0),
 	NPCM8XX_PINCFG(253,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC1 power */
 	NPCM8XX_PINCFG(254,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* SDHC2 power */
 	NPCM8XX_PINCFG(255,	none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		none, NONE, 0,		GPI), /* DACOSEL */
Signature · 1 line
2.34.1
maintainer
#8 lore raw
In reply to Tomer Maimon

Hi Tomer,

Quoted 22 lines · Tomer Maimon

This patch set addresses various pin configuration changes for the Nuvoton NPCM8XX BMC SoC. The patches aim to enhance functionality, remove unused pins, and improve overall pin management.

This patchset is on the upstream process to the Linux vanilla.
https://lore.kernel.org/lkml/[email protected]/

Changes since version 1:
- Squash the non-existent pins, groups and functions.
- Remove non-existent groups and functions from dt-bindings.
- Modify the commit message.

Tomer Maimon (7):
dt-bindings: pinctrl: npcm8xx: remove non-existent groups and
functions
pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions
pinctrl: nuvoton: npcm8xx: clear polarity before set both edge
pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36
pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group
pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration
pinctrl: nuvoton: npcm8xx: modify pins flags

Quoted 4 lines
 .../pinctrl/nuvoton,npcm845-pinctrl.yaml      | 74 +++++++++----------
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c     | 64 ++++++++--------
 2 files changed, 67 insertions(+), 71 deletions(-)

I looked at applying this series. A few notes:

1. I did get some whitespace warnings during patch application:

```
...
Applying: pinctrl: nuvoton: npcm8xx: modify pins flags                                                                                                         
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:47: trailing whitespace.                                                            
                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1  
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:89: trailing whitespace.                                                            
                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1                                                                                    
warning: 2 lines add whitespace errors.
```

2. There's a reasonable difference to the patches upstream. The devicetree binding in particular seems to have some odd differences in the enums that make me wonder whether we're missing other patches there. There are also some minor differences in the driver which I assume are explained by intervening changes between v6.6 and upstream. Here's the diff, can you give a quick comment on each hunk?

```
$ git diff <backported patches on dev-6.6> <patches proposed upstream on c33ffdb70cc6 ("Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy")> -- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
index 4496658006ab..8cd1f442240e 100644
--- a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
@@ -35,6 +35,7 @@ properties:
 patternProperties:
   '^gpio@':
     type: object
+    additionalProperties: false

     description:
       Eight GPIO banks that each contain 32 GPIOs.
@@ -80,37 +81,39 @@ patternProperties:
                   fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
                   fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
                   r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                  smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                  pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                  mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                  faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                  wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                  hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
+                  smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
+                  pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
+                  mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
+                  smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
+                  spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
+                  smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
+                  spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
+                  hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]

       function:
         description:
           The function that a group of pins is muxed to
-        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
-                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
-                smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
-                smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
-                spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
-                smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
-                bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
-                fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
-                fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
-                fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
-                r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
+                smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
+                smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
+                smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
+                spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
+                uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
+                r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
+                fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
+                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
+                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,
+                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
+                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
+                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
+                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
+                smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
+                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
+                smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
+                smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
+                hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
+                bu6, gpo187 ]

     dependencies:
       groups: [ function ]
@@ -149,7 +152,6 @@ patternProperties:
         description:
           Debouncing periods in microseconds, one period per interrupt
           bank found in the controller
-        $ref: /schemas/types.yaml#/definitions/uint32-array
         minItems: 1
         maxItems: 4

@@ -157,7 +159,6 @@ patternProperties:
         description: |
           0: Low rate
           1: High rate
-        $ref: /schemas/types.yaml#/definitions/uint32
         enum: [0, 1]

       drive-strength:
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
index 607960fdbc40..471f644c5eef 100644
--- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -173,7 +173,7 @@ static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;

-       ret = pinctrl_gpio_direction_input(offset + chip->base);
+       ret = pinctrl_gpio_direction_input(chip, offset);
        if (ret)
                return ret;

@@ -186,7 +186,7 @@ static int npcmgpio_direction_output(struct gpio_chip *chip,
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;

-       ret = pinctrl_gpio_direction_output(offset + chip->base);
+       ret = pinctrl_gpio_direction_output(chip, offset);
        if (ret)
                return ret;

@@ -198,18 +198,13 @@ static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;

-       ret = pinctrl_gpio_request(offset + chip->base);
+       ret = pinctrl_gpio_request(chip, offset);
        if (ret)
                return ret;

        return bank->request(chip, offset);
 }

-static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
-{
-       pinctrl_gpio_free(offset + chip->base);
-}
-
 static void npcmgpio_irq_handler(struct irq_desc *desc)
 {
        unsigned long sts, en, bit;
@@ -2386,7 +2381,7 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
                pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
                pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
                pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
-               pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
+               pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;
                for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
                        pctrl->gpio_bank[id].debounce.set_val[i] = false;
                pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;
```

Andrew

author maintainer
#9 lore raw

Hi Andrew,

Thanks for your comments

Quoted 35 lines · Andrew Jeffery

Hi Tomer,

Quoted 22 lines · Tomer Maimon

This patch set addresses various pin configuration changes for the Nuvoton NPCM8XX BMC SoC. The patches aim to enhance functionality, remove unused pins, and improve overall pin management.

This patchset is on the upstream process to the Linux vanilla.
https://lore.kernel.org/lkml/[email protected]/

Changes since version 1:
- Squash the non-existent pins, groups and functions.
- Remove non-existent groups and functions from dt-bindings.
- Modify the commit message.

Tomer Maimon (7):
dt-bindings: pinctrl: npcm8xx: remove non-existent groups and
functions
pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions
pinctrl: nuvoton: npcm8xx: clear polarity before set both edge
pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36
pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group
pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration
pinctrl: nuvoton: npcm8xx: modify pins flags

Quoted 4 lines
 .../pinctrl/nuvoton,npcm845-pinctrl.yaml      | 74 +++++++++----------
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c     | 64 ++++++++--------
 2 files changed, 67 insertions(+), 71 deletions(-)

I looked at applying this series. A few notes:

1. I did get some whitespace warnings during patch application:

Quoted 10 lines
```
...
Applying: pinctrl: nuvoton: npcm8xx: modify pins flags
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:47: trailing whitespace.
                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:89: trailing whitespace.
                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
warning: 2 lines add whitespace errors.
```

will fixed in V3

Quoted 75 lines

2. There's a reasonable difference to the patches upstream. The devicetree binding in particular seems to have some odd differences in the enums that make me wonder whether we're missing other patches there. There are also some minor differences in the driver which I assume are explained by intervening changes between v6.6 and upstream. Here's the diff, can you give a quick comment on each hunk?

```

$ git diff <backported patches on dev-6.6> <patches proposed upstream on c33ffdb70cc6 ("Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy")> -- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +20 -27
index 4496658006ab..8cd1f442240e 100644
@@ -35,6 +35,7 @@ properties:
 patternProperties:
   '^gpio@':
     type: object
+    additionalProperties: false
 
     description:
       Eight GPIO banks that each contain 32 GPIOs.

@@ -80,37 +81,39 @@ patternProperties:
                   fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
                   fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
                   r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                  smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                  pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                  mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                  faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                  wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                  hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
+                  smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
+                  pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
+                  mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
+                  smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
+                  spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
+                  smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
+                  spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
+                  hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
 
       function:
         description:
           The function that a group of pins is muxed to
-        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
-                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
-                smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
-                smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
-                spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
-                smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
-                bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
-                fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
-                fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
-                fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
-                r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
+                smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
+                smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
+                smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
+                spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
+                uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
+                r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
+                fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
+                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
+                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 116

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +10 -0
+                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
+                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
+                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
+                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
+                smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
+                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
+                smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
+                smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
+                hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
+                bu6, gpo187 ]

Thanks for raising I have an error here, I will fixed it in the vanilla and the OpenBMC, I should remove and add enums.

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 152

Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -1
     dependencies:
       groups: [ function ]

@@ -149,7 +152,6 @@ patternProperties:
         description:
           Debouncing periods in microseconds, one period per interrupt
           bank found in the controller
-        $ref: /schemas/types.yaml#/definitions/uint32-array

it removed in the newer version, we can keep it

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 160

Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -1
         minItems: 1
         maxItems: 4
 

@@ -157,7 +159,6 @@ patternProperties:
         description: |
           0: Low rate
           1: High rate
-        $ref: /schemas/types.yaml#/definitions/uint32

it removed in the newer version, we can keep it

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) · line 176

Quoted 13 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -0
         enum: [0, 1]
 
       drive-strength:
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -1
index 607960fdbc40..471f644c5eef 100644
@@ -173,7 +173,7 @@ static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;
 
-       ret = pinctrl_gpio_direction_input(offset + chip->base);
+       ret = pinctrl_gpio_direction_input(chip, offset);

Modify in newer version, will revert the change in V3. since kernel 6.6 doesn't support it

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcmgpio_direction_output(struct gpio_chip *chip, · line 189

Quoted 9 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -1
        if (ret)
                return ret;
 

@@ -186,7 +186,7 @@ static int npcmgpio_direction_output(struct gpio_chip *chip,
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;
 
-       ret = pinctrl_gpio_direction_output(offset + chip->base);
+       ret = pinctrl_gpio_direction_output(chip, offset);

same as above

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) · line 201

Quoted 9 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -1
        if (ret)
                return ret;
 

@@ -198,18 +198,13 @@ static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;
 
-       ret = pinctrl_gpio_request(offset + chip->base);
+       ret = pinctrl_gpio_request(chip, offset);

same as above

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) · line 212

Quoted 11 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +0 -5
        if (ret)
                return ret;
 
        return bank->request(chip, offset);
 }
 
-static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset)
-{
-       pinctrl_gpio_free(offset + chip->base);
-}
-

same as above

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) · line 2384

Quoted 9 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -1
 static void npcmgpio_irq_handler(struct irq_desc *desc)
 {
        unsigned long sts, en, bit;

@@ -2386,7 +2381,7 @@ static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl)
                pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output;
                pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request;
                pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request;
-               pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free;
+               pctrl->gpio_bank[id].gc.free = pinctrl_gpio_free;

same as above

Quoted 6 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +0 -0
                for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++)
                        pctrl->gpio_bank[id].debounce.set_val[i] = false;
                pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges;

```

Andrew

Best regards,

Tomer

maintainer
#10 lore raw
Quoted 140 lines · Tomer Maimon

Hi Andrew,

Thanks for your comments

Quoted 35 lines · Andrew Jeffery

Hi Tomer,

Quoted 22 lines · Tomer Maimon

This patch set addresses various pin configuration changes for the Nuvoton NPCM8XX BMC SoC. The patches aim to enhance functionality, remove unused pins, and improve overall pin management.

This patchset is on the upstream process to the Linux vanilla.
https://lore.kernel.org/lkml/[email protected]/

Changes since version 1:
- Squash the non-existent pins, groups and functions.
- Remove non-existent groups and functions from dt-bindings.
- Modify the commit message.

Tomer Maimon (7):
dt-bindings: pinctrl: npcm8xx: remove non-existent groups and
functions
pinctrl: nuvoton: npcm8xx: remove non-existent pins, groups, functions
pinctrl: nuvoton: npcm8xx: clear polarity before set both edge
pinctrl: nuvoton: npcm8xx: add gpi35 and gpi36
pinctrl: nuvoton: npcm8xx: add pin 250 to DDR pins group
pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configuration
pinctrl: nuvoton: npcm8xx: modify pins flags

Quoted 4 lines
 .../pinctrl/nuvoton,npcm845-pinctrl.yaml      | 74 +++++++++----------
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c     | 64 ++++++++--------
 2 files changed, 67 insertions(+), 71 deletions(-)

I looked at applying this series. A few notes:

1. I did get some whitespace warnings during patch application:

Quoted 10 lines
```
...
Applying: pinctrl: nuvoton: npcm8xx: modify pins flags
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:47: trailing whitespace.
                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
/home/andrew/src/kernel.org/linux.git/worktrees/openbmc/rebase-apply/patch:89: trailing whitespace.
                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
warning: 2 lines add whitespace errors.
```

will fixed in V3

Quoted 75 lines

2. There's a reasonable difference to the patches upstream. The devicetree binding in particular seems to have some odd differences in the enums that make me wonder whether we're missing other patches there. There are also some minor differences in the driver which I assume are explained by intervening changes between v6.6 and upstream. Here's the diff, can you give a quick comment on each hunk?

```

$ git diff <backported patches on dev-6.6> <patches proposed upstream on c33ffdb70cc6 ("Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy")> -- drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +20 -27
index 4496658006ab..8cd1f442240e 100644
@@ -35,6 +35,7 @@ properties:
 patternProperties:
   '^gpio@':
     type: object
+    additionalProperties: false
 
     description:
       Eight GPIO banks that each contain 32 GPIOs.

@@ -80,37 +81,39 @@ patternProperties:
                   fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
                   fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
                   r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                  smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                  pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                  mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                  faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                  nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                  wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                  hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+                  i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c,
+                  smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5,
+                  pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd,
+                  mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c,
+                  smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3,
+                  spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c,
+                  smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13,
+                  spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4,
+                  hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ]
 
       function:
         description:
           The function that a group of pins is muxed to
-        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi,
-                smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15,
-                smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23,
-                smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2,
-                spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c,
-                smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio,
-                bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d,
-                fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6,
-                fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13,
-                fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md,
-                r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1,
-                i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b,
-                smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4,
-                pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp,
-                mmccd, mmcrst, clkout, serirq, scipme, smi, smb6, smb7, spi1,
-                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3,
-                nprd_smi, smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1
-                wdog2, smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1,
-                hgpio2, hgpio3, hgpio4, hgpio5, hgpio6, hgpio7 ]
+        enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b,
+                smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16,
+                smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d,
+                smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0,
+                spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a,
+                uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md,
+                r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2,
+                fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10,
+                fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2,
+                pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2,

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 116

Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +10 -0
+                ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2,
+                smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1,
+                sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11,
+                mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi,
+                smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1,
+                faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi,
+                smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2,
+                smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2,
+                hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b,
+                bu6, gpo187 ]

Thanks for raising I have an error here, I will fixed it in the vanilla and the OpenBMC, I should remove and add enums.

Quoted 1 line
Quoted 8 lines

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 152

Quoted 7 lines

dependencies:
groups: [ function ]

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -1
@@ -149,7 +152,6 @@ patternProperties:
         description:
           Debouncing periods in microseconds, one period per interrupt
           bank found in the controller
-        $ref: /schemas/types.yaml#/definitions/uint32-array

it removed in the newer version, we can keep it

The outcome I'm after is we have the least difference in the patches for dev-6.6 to those upstream. If it's correct to remove it, and that is what you've done in the upstream patches, then we should remove it in the dev-6.6 patches as well.

Quoted 20 lines

Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml patternProperties: · line 160

Quoted 8 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -1
         minItems: 1
         maxItems: 4
 

@@ -157,7 +159,6 @@ patternProperties:
         description: |
           0: Low rate
           1: High rate
-        $ref: /schemas/types.yaml#/definitions/uint32

it removed in the newer version, we can keep it

Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml +0 -0
         enum: [0, 1]
 
       drive-strength:
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +0 -0
index 607960fdbc40..471f644c5eef 100644
@@ -173,7 +173,7 @@ static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)
        struct npcm8xx_gpio *bank = gpiochip_get_data(chip);
        int ret;
Quoted 4 lines

drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) · line 176

Quoted 2 lines
drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +1 -1
-       ret = pinctrl_gpio_direction_input(offset + chip->base);
+       ret = pinctrl_gpio_direction_input(chip, offset);

Modify in newer version, will revert the change in V3. since kernel 6.6 doesn't support it

Just to clarify, the dev-6.6 patches have the "-" content, and the upstream patches have the "+" content. Perhaps how I generated the diff is the confusing bit here. If you need me to unpack that a bit more please ask, it's important that we both have the same understanding of what's going on :D

Andrew