arm64: dts: rockchip: Add missing pinctrl for PCIe30x4 node

Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state.

PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization.

WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state.

CLKREQ signal is also an active-low signal and is used to request the reference clock.

Rename node from 'pcie3' to 'pcie30x4' to align with schematic nomenclature.

Signed-off-by Anand Moon <[email protected]>

---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN number.

V3: use pinctrl local to board
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctrl dtsi

---
 .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +12 -6

index 966bbc582d89..1c7080cca11f 100644
@@ -338,7 +338,7 @@ &pcie30phy {
 
 &pcie3x4 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3_rst>;
+	pinctrl-0 = <&pcie30x4_pins>;
 	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";

@@ -377,14 +377,20 @@ pcie2_2_rst: pcie2-2-rst {
 		};
 	};
 
-	pcie3 {
-		pcie3_rst: pcie3-rst {
-			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
+	pcie30x4 {
 		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
 			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie30x4_pins: pcie30x4-pins {
+			rockchip,pins =
+				/* PCIE30X4_CLKREQn_M1_L */
+				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+				/* PCIE30X4_PERSTn_M1_L */
+				<4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>,
+				/* PCIE30X4_WAKEn_M1_L */
+				<4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b

Hi Anand,

Sorry for no reply to your v3.

Quoted 17 lines · Anand Moon

Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state.

PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization.

WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state.

CLKREQ signal is also an active-low signal and is used to request the reference clock.

Quoted 7 lines

Rename node from 'pcie3' to 'pcie30x4' to align with schematic nomenclature.

Signed-off-by Anand Moon <[email protected]>

---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN number.

Why this change? Only reset should use gpio function, if I am not mistaken. Also how come you change the internal pull-up/down on these pins?, and why do they differ for each pcie node in this series?

Please see [1] for some discussion related to these pins.

"""
The PERST is for sure should work as GPIO, and the same as WAKE;

for CLKREQ, only those board want to support L1SS need to work as function IO,
"""

As stated earlier only the reset pin need to be muxed to GPIO function, and that should also matches the only pin controlled with gpio in the driver, if I am not mistaken.

[1] https://lore.kernel.org/u-boot/[email protected]/

Regards,
Jonas

Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state.

PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization.

WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state.

CLKREQ signal is also an active-low signal and is used to request the reference clock.

Rename node from 'pcie3' to 'pcie30x4' to align with schematic nomenclature.

Signed-off-by Anand Moon <[email protected]>

---
v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN number.
V3: use pinctrl local to board
V2: Update the commit messge to describe the changs.
use pinctl group as its pre define in pinctrl dtsi

---
 .../arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +12 -6

index 966bbc582d89..1c7080cca11f 100644
@@ -338,7 +338,7 @@ &pcie30phy {
 
 &pcie3x4 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie3_rst>;
+	pinctrl-0 = <&pcie30x4_pins>;
 	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie30>;
 	status = "okay";

@@ -377,14 +377,20 @@ pcie2_2_rst: pcie2-2-rst {
 		};
 	};
 
-	pcie3 {
-		pcie3_rst: pcie3-rst {
-			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-
+	pcie30x4 {
 		pcie3_vcc3v3_en: pcie3-vcc3v3-en {
 			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+
+		pcie30x4_pins: pcie30x4-pins {
+			rockchip,pins =
+				/* PCIE30X4_CLKREQn_M1_L */
+				<4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+				/* PCIE30X4_PERSTn_M1_L */
+				<4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>,
+				/* PCIE30X4_WAKEn_M1_L */
+				<4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
+		};
 	};
 
 	usb {

base-commit: 1722389b0d863056d78287a120a1d6cadb8d4f7b

Hello Anand,

Quoted 20 lines · Anand Moon

Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake signals. Each component of PCIe communication have the following control
signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate
high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state.

PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable.
A transition from low to high in this signal usually indicates the beginning of link initialization.

WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state.

CLKREQ signal is also an active-low signal and is used to request the reference clock.

Quoted 2 lines

Rename node from 'pcie3' to 'pcie30x4' to align with schematic nomenclature.

I wonder why the three patches in this series cannot be squashed into a single patch, because they target the same thing for the same board dts file? I don't think that having these three separate patches may help with possible regression tracking in the future, for example.