drm/xe/vram: fix ccs offset calculation
Subsystems (3)
PATCH 1/1 drm/xe/vram: fix ccs offset calculation
Spec says SW is expected to round up to the nearest 128K, if not already aligned. We are seeing the assert sometimes pop on BMG to tell us that there is a hole between GSM and CCS, as well as popping other asserts with having a vram size with strange alignment, which is likely caused by misaligned offset here.
BSpec: 68023
Fixes b5c2ca0372dc ("drm/xe/xe2hpg: Determine flat ccs offset for vram")
Signed-off-by Matthew Auld <[email protected]>
Cc Himal Prasad Ghimiray <[email protected]>
Cc Akshata Jahagirdar <[email protected]>
Cc Shuicheng Lin <[email protected]>
Cc Matt Roper <[email protected]>
Cc <[email protected]> # v6.10+
--- drivers/gpu/drm/xe/xe_vram.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpu/drm/xe/xe_vram.c +1 -0
@@ -181,6 +181,7 @@ static inline u64 get_flat_ccs_offset(struct xe_gt *gt, u64 tile_size) offset = offset_hi <<32 ;/* HW view bits 39:32 */ offset |= offset_lo <<6 ;/* HW view bits 31:6 */ + offset =round_up (offset,SZ_128K );/* SW must round up to nearest 128K */ offset *= num_enabled;/* convert to SW view */ /* We don't expect any holes */
Signature · 1 line
2.46.0