arm64: Clean up and simplify PA space size handling
Subsystems (4)
v2 cover arm64: Clean up and simplify PA space size handling
From: Ard Biesheuvel <[email protected]>
This series addresses a number of buglets related to how we handle the size of the physical address space when building LPA2 capable kernels:
- reject 52-bit physical addressess in the mapping routines when LPA2 is configured but not available at runtime
- ensure that TCR.IPS is not set to 52-bits if LPA2 is not supported
- ensure that TCR_EL2.PS and DS match the host, regardless of whether LPA2 is available at stage 2
- don't rely on kvm_get_parange() and invalid physical addresses as control flags in the pKVM page donation APIs
Finally, the configurable 48-bit physical address space limit is dropped entirely, as it doesn't buy us a lot now that all the PARange and {I}PS handling is done at runtime.
Changes since v1:
- rebase onto v6.13-rc1
- add Anshuman's ack to patch #1
- incorporate Anshuman's feedback on patches #1 and #2
- tweak owner_update logic in patch #4
Ard Biesheuvel (6):
arm64/mm: Reduce PA space to 48 bits when LPA2 is not enabled arm64/mm: Override PARange for !LPA2 and use it consistently arm64/kvm: Configure HYP TCR.PS/DS based on host stage1 arm64/kvm: Avoid invalid physical addresses to signal owner updates
arm64: Kconfig: force ARM64_PAN=y when enabling TTBR0 sw PAN arm64/mm: Drop configurable 48-bit physical address space limit
arch/arm64/Kconfig | 37 ++------------------ arch/arm64/include/asm/assembler.h | 14 +++----- arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/kvm_pgtable.h | 3 +- arch/arm64/include/asm/pgtable-hwdef.h | 12 +------ arch/arm64/include/asm/pgtable-prot.h | 7 ++++ arch/arm64/include/asm/pgtable.h | 11 +----- arch/arm64/include/asm/sparsemem.h | 4 ++- arch/arm64/include/asm/sysreg.h | 6 ---- arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/pi/idreg-override.c | 9 +++++ arch/arm64/kernel/pi/map_kernel.c | 6 ++++ arch/arm64/kvm/arm.c | 8 ++--- arch/arm64/kvm/hyp/pgtable.c | 33 ++++++----------- arch/arm64/mm/init.c | 7 +++- arch/arm64/mm/pgd.c | 9 ++--- arch/arm64/mm/proc.S | 2 -- scripts/gdb/linux/constants.py.in | 1 - tools/arch/arm64/include/asm/sysreg.h | 6 ---- 19 files changed, 63 insertions(+), 117 deletions(-)
Signature · 1 line
2.47.0.338.g60cca15819-goog
PATCH v2 1/6 arm64/mm: Reduce PA space to 48 bits when LPA2 is not enabled
From: Ard Biesheuvel <[email protected]>
Currently, LPA2 kernel support implies support for up to 52 bits of physical addressing, and this is reflected in global definitions such as PHYS_MASK_SHIFT and MAX_PHYSMEM_BITS.
This is potentially problematic, given that LPA2 hardware support is modeled as a CPU feature which can be overridden, and with LPA2 hardware support turned off, attempting to map physical regions with address bits [51:48] set (which may exist on LPA2 capable systems booting with arm64.nolva) will result in corrupted mappings with a truncated output address and bogus shareability attributes.
This means that the accepted physical address range in the mapping routines should be at most 48 bits wide when LPA2 support is configured but not enabled at runtime.
--- arch/arm64/include/asm/pgtable-hwdef.h | 6 ------ arch/arm64/include/asm/pgtable-prot.h | 7 +++++++ arch/arm64/include/asm/sparsemem.h | 4 +++- 3 files changed, 10 insertions(+), 7 deletions(-)
arch/arm64/include/asm/pgtable-hwdef.h +0 -6
@@ -222,12 +222,6 @@*/ #define S1_TABLE_AP (_AT(pmdval_t, 3) << 61) -/* -* Highest possible physical address supported. -*/ -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) -#define TTBR_CNP_BIT (UL(1) << 0)/*
arch/arm64/include/asm/pgtable-prot.h +7 -0
@@ -81,6 +81,7 @@ extern unsigned long prot_ns_shared;#define lpa2_is_enabled () false#define PTE_MAYBE_SHARED PTE_SHARED#define PMD_MAYBE_SHARED PMD_SECT_S +#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)#else static inline bool __pure lpa2_is_enabled (void ) {
@@ -89,8 +90,14 @@ static inline bool __pure lpa2_is_enabled(void)#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S) +#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)#endif +/* +* Highest possible physical address supported. +*/ +#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) +/* * If we have userspace only BTI we don't want to mark kernel pages * guarded even if the system does support BTI.
arch/arm64/include/asm/sparsemem.h +3 -1
@@ -5,7 +5,9 @@#ifndef __ASM_SPARSEMEM_H#define __ASM_SPARSEMEM_H -#define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS +#include <asm/pgtable-prot.h> + +#define MAX_PHYSMEM_BITS PHYS_MASK_SHIFT/* * Section size must be at least 512MB for 64K base
Signature · 1 line
2.47.0.338.g60cca15819-goog
Re: [PATCH v2 1/6] arm64/mm: Reduce PA space to 48 bits when LPA2 is not enabled
Quoted 77 lines · Ard Biesheuvel
From: Ard Biesheuvel <[email protected]>
Currently, LPA2 kernel support implies support for up to 52 bits of physical addressing, and this is reflected in global definitions such as
PHYS_MASK_SHIFTandMAX_PHYSMEM_BITS.This is potentially problematic, given that LPA2 hardware support is modeled as a CPU feature which can be overridden, and with LPA2 hardware support turned off, attempting to map physical regions with address bits [51:48] set (which may exist on LPA2 capable systems booting with arm64.nolva) will result in corrupted mappings with a truncated output address and bogus shareability attributes.
This means that the accepted physical address range in the mapping routines should be at most 48 bits wide when LPA2 support is configured but not enabled at runtime.
Fixes 352b0395b505 ("arm64: Enable 52-bit virtual addressing for 4k and 16k granule configs")Cc <[email protected]>Reviewed-by Anshuman Khandual <[email protected]>Signed-off-by Ard Biesheuvel <[email protected]>--- arch/arm64/include/asm/pgtable-hwdef.h | 6 ------ arch/arm64/include/asm/pgtable-prot.h | 7 +++++++ arch/arm64/include/asm/sparsemem.h | 4 +++- 3 files changed, 10 insertions(+), 7 deletions(-)arch/arm64/include/asm/pgtable-hwdef.h +0
-6@@ -222,12 +222,6 @@*/ #define S1_TABLE_AP (_AT(pmdval_t, 3) << 61) -/* -* Highest possible physical address supported. -*/ -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) -#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) -#define TTBR_CNP_BIT (UL(1) << 0)/* arch/arm64/include/asm/pgtable-prot.h +7
-0@@ -81,6 +81,7 @@ extern unsigned long prot_ns_shared;#define lpa2_is_enabled () false#define PTE_MAYBE_SHARED PTE_SHARED#define PMD_MAYBE_SHARED PMD_SECT_S +#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)#else static inline bool __pure lpa2_is_enabled (void ) {@@ -89,8 +90,14 @@ static inline bool __pure lpa2_is_enabled(void)#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S) +#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48)#endif +/* +* Highest possible physical address supported. +*/ +#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1) +/* * If we have userspace only BTI we don't want to mark kernel pages * guarded even if the system does support BTI. arch/arm64/include/asm/sparsemem.h +0
-0
arch/arm64/include/asm/sparsemem.h line 11
Quoted 8 lines
arch/arm64/include/asm/sparsemem.h +3
-1@@ -5,7 +5,9 @@#ifndef __ASM_SPARSEMEM_H#define __ASM_SPARSEMEM_H -#define MAX_PHYSMEM_BITS CONFIG_ARM64_PA_BITS +#include <asm/pgtable-prot.h> + +#define MAX_PHYSMEM_BITS PHYS_MASK_SHIFT
This needs
arch/arm64/include/asm/sparsemem.h +2 -1
@@ -7,7 +7,8 @@#include <asm/pgtable-prot.h> -#define MAX_PHYSMEM_BITS PHYS_MASK_SHIFT +#define MAX_PHYSMEM_BITS PHYS_MASK_SHIFT +#define MAX_POSSIBLE_PHYSMEM_BITS (52)/* * Section size must be at least 512MB for 64K base
applied on top to make the ZSMALLOC code happy.
PATCH v2 2/6 arm64/mm: Override PARange for !LPA2 and use it consistently
In reply to Ard BiesheuvelFrom: Ard Biesheuvel <[email protected]>
When FEAT_LPA{,2} are not implemented, the ID_AA64MMFR0_EL1.PARange and TCR.IPS values corresponding with 52-bit physical addressing are reserved.
Setting the TCR.IPS field to 0b110 (52-bit physical addressing) has side effects, such as how the TTBRn_ELx.BADDR fields are interpreted, and so it is important that disabling FEAT_LPA2 (by overriding the ID_AA64MMFR0.TGran fields) also presents a PARange field consistent with that.
So limit the field to 48 bits unless LPA2 is enabled, and update existing references to use the override consistently.
--- arch/arm64/include/asm/assembler.h | 5 +++++ arch/arm64/kernel/cpufeature.c | 2 +- arch/arm64/kernel/pi/idreg-override.c | 9 +++++++++ arch/arm64/kernel/pi/map_kernel.c | 6 ++++++ arch/arm64/mm/init.c | 7 ++++++- 5 files changed, 27 insertions(+), 2 deletions(-)
arch/arm64/include/asm/assembler.h +5 -0
@@ -343,6 +343,11 @@ alternative_cb_end// Narrow PARange to fit the PS field in TCR_ELx ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX +#ifdef CONFIG_ARM64_LPA2 +alternative_if_not ARM64_HAS_VA52 + mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48 +alternative_else_nop_endif +#endif cmp \tmp0, \tmp1 csel \tmp0, \tmp1, \tmp0, hi bfi \tcr, \tmp0, \pos, #3
arch/arm64/kernel/cpufeature.c +1 -1
@@ -3478,7 +3478,7 @@ static void verify_hyp_capabilities(void)return ; safe_mmfr1 =read_sanitised_ftr_reg (SYS_ID_AA64MMFR1_EL1 ); - mmfr0 =read_cpuid (ID_AA64MMFR0_EL1 ); + mmfr0 =read_sanitised_ftr_reg (SYS_ID_AA64MMFR0_EL1 ); mmfr1 =read_cpuid (ID_AA64MMFR1_EL1 );/* Verify VMID bits */
arch/arm64/kernel/pi/idreg-override.c +9 -0
@@ -83,6 +83,15 @@ static bool __init mmfr2_varange_filter(u64 val) id_aa64mmfr0_override.val |= (ID_AA64MMFR0_EL1_TGRAN_LPA2 -1 ) <<ID_AA64MMFR0_EL1_TGRAN_SHIFT ; id_aa64mmfr0_override.mask |=0xfU <<ID_AA64MMFR0_EL1_TGRAN_SHIFT ; + +/* +* Override PARange to 48 bits - the override will just be +* ignored if the actual PARange is smaller, but this is +* unlikely to be the case for LPA2 capable silicon. +*/ + id_aa64mmfr0_override.val |= +ID_AA64MMFR0_EL1_PARANGE_48 <<ID_AA64MMFR0_EL1_PARANGE_SHIFT ; + id_aa64mmfr0_override.mask |= 0xfU << ID_AA64MMFR0_EL1_PARANGE_SHIFT; }#endif return true;
arch/arm64/kernel/pi/map_kernel.c +6 -0
@@ -136,6 +136,12 @@ static void noinline __section(".idmap.text") set_ttbr0_for_lpa2(u64 ttbr) {u64 sctlr =read_sysreg (sctlr_el1);u64 tcr =read_sysreg (tcr_el1) |TCR_DS ; +u64 mmfr0 =read_sysreg (id_aa64mmfr0_el1); +u64 parange =cpuid_feature_extract_unsigned_field (mmfr0, +ID_AA64MMFR0_EL1_PARANGE_SHIFT ); + + tcr &= ~TCR_IPS_MASK ; + tcr |= parange <<TCR_IPS_SHIFT ; asm(" msr sctlr_el1, %0 ;" " isb ;"
arch/arm64/mm/init.c +6 -1
@@ -280,7 +280,12 @@ void __init arm64_memblock_init(void)if (IS_ENABLED (CONFIG_RANDOMIZE_BASE )) {extern u16 memstart_offset_seed; -u64 mmfr0 =read_cpuid (ID_AA64MMFR0_EL1 ); + +/* +* Use the sanitised version of id_aa64mmfr0_el1 so that linear +* map randomization can be enabled by shrinking the IPA space. +*/ +u64 mmfr0 =read_sanitised_ftr_reg (SYS_ID_AA64MMFR0_EL1 );int parange =cpuid_feature_extract_unsigned_field ( mmfr0,ID_AA64MMFR0_EL1_PARANGE_SHIFT ); s64 range = linear_region_size -
Signature · 1 line
2.47.0.338.g60cca15819-goog
PATCH v2 3/6 arm64/kvm: Configure HYP TCR.PS/DS based on host stage1
In reply to Ard BiesheuvelFrom: Ard Biesheuvel <[email protected]>
When the host stage1 is configured for LPA2, the value currently being programmed into TCR_EL2.T0SZ may be invalid unless LPA2 is configured at HYP as well. This means kvm_lpa2_is_enabled() is not the right condition to test when setting TCR_EL2.DS, as it will return false if LPA2 is only available for stage 1 but not for stage 2.
Similary, programming TCR_EL2.PS based on a limited IPA range due to lack of stage2 LPA2 support could potentially result in problems.
So use lpa2_is_enabled() instead, and set the PS field according to the host's IPS, which is capped at 48 bits if LPA2 support is absent or disabled. Whether or not we can make meaningful use of such a configuration is a different question.
--- arch/arm64/kvm/arm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
arch/arm64/kvm/arm.c +4 -4
@@ -1990,8 +1990,7 @@ static int kvm_init_vector_slots(void)static void __init cpu_prepare_hyp_mode (int cpu,u32 hyp_va_bits) {struct kvm_nvhe_init_params *params =per_cpu_ptr_nvhe_sym (kvm_init_params, cpu); -u64 mmfr0 =read_sanitised_ftr_reg (SYS_ID_AA64MMFR0_EL1 ); -unsigned long tcr; +unsigned long tcr, ips;/* * Calculate the raw per-cpu offset without a translation from the
@@ -2005,6 +2004,7 @@ static void __init cpu_prepare_hyp_mode(int cpu, u32 hyp_va_bits) params->mair_el2 =read_sysreg (mair_el1); tcr =read_sysreg (tcr_el1); + ips =FIELD_GET (TCR_IPS_MASK , tcr);if (cpus_have_final_cap (ARM64_KVM_HVHE )) { tcr |=TCR_EPD1_MASK ; }else {
@@ -2014,8 +2014,8 @@ static void __init cpu_prepare_hyp_mode(int cpu, u32 hyp_va_bits) tcr &= ~TCR_T0SZ_MASK ; tcr |=TCR_T0SZ (hyp_va_bits); tcr &= ~TCR_EL2_PS_MASK ; - tcr |=FIELD_PREP (TCR_EL2_PS_MASK ,kvm_get_parange (mmfr0)); -if (kvm_lpa2_is_enabled ()) + tcr |=FIELD_PREP (TCR_EL2_PS_MASK , ips); +if (lpa2_is_enabled ()) tcr |=TCR_EL2_DS ; params->tcr_el2 = tcr;
Signature · 1 line
2.47.0.338.g60cca15819-goog
PATCH v2 4/6 arm64/kvm: Avoid invalid physical addresses to signal owner updates
In reply to Ard BiesheuvelFrom: Ard Biesheuvel <[email protected]>
The pKVM stage2 mapping code relies on an invalid physical address to signal to the internal API that only the owner_id fields of descriptors should be updated, and these are stored in the high bits of invalid descriptors covering memory that has been donated to protected guests, and is therefore unmapped from the host stage-2 page tables.
Given that these invalid PAs are never stored into the descriptors, it is better to rely on an explicit flag, to clarify the API and to avoid confusion regarding whether or not the output address of a descriptor can ever be invalid to begin with (which is not the case with LPA2).
That removes a dependency on the logic that reasons about the maximum PA range, which differs on LPA2 capable CPUs based on whether LPA2 is enabled or not, and will be further clarified in subsequent patches.
--- arch/arm64/kvm/hyp/pgtable.c | 33 ++++++-------------- 1 file changed, 10 insertions(+), 23 deletions(-)
arch/arm64/kvm/hyp/pgtable.c +10 -23
@@ -35,14 +35,6 @@ static bool kvm_pgtable_walk_skip_cmo(const struct kvm_pgtable_visit_ctx *ctx)return unlikely (ctx->flags &KVM_PGTABLE_WALK_SKIP_CMO ); } -static bool kvm_phys_is_valid (u64 phys) -{ -u64 parange_max =kvm_get_parange_max (); -u8 shift =id_aa64mmfr0_parange_to_phys_shift (parange_max); - -return phys <BIT (shift); -} -static bool kvm_block_mapping_supported (const struct kvm_pgtable_visit_ctx *ctx,u64 phys) {u64 granule =kvm_granule_size (ctx->level);
@@ -53,7 +45,7 @@ static bool kvm_block_mapping_supported(const struct kvm_pgtable_visit_ctx *ctx,if (granule > (ctx->end - ctx->addr))return false; -if (kvm_phys_is_valid (phys) && !IS_ALIGNED (phys, granule)) +if (!IS_ALIGNED (phys, granule))return false;return IS_ALIGNED (ctx->addr, granule);
@@ -587,6 +579,9 @@ struct stage2_map_data {/* Force mappings to page granularity */ bool force_pte; + +/* Walk should update owner_id only */ +bool owner_update; };u64 kvm_get_vtcr (u64 mmfr0,u64 mmfr1,u32 phys_shift)
@@ -885,18 +880,7 @@ static u64 stage2_map_walker_phys_addr(const struct kvm_pgtable_visit_ctx *ctx, {u64 phys = data->phys; -/* -* Stage-2 walks to update ownership data are communicated to the map -* walker using an invalid PA. Avoid offsetting an already invalid PA, -* which could overflow and make the address valid again. -*/ -if (!kvm_phys_is_valid (phys)) -return phys; - -/* -* Otherwise, work out the correct PA based on how far the walk has -* gotten. -*/ +/* Work out the correct PA based on how far the walk has gotten */ return phys + (ctx->addr - ctx->start); }
@@ -908,6 +892,9 @@ static bool stage2_leaf_mapping_allowed(const struct kvm_pgtable_visit_ctx *ctx,if (data->force_pte && ctx->level <KVM_PGTABLE_LAST_LEVEL )return false; +if (data->owner_update && ctx->level ==KVM_PGTABLE_LAST_LEVEL ) +return true; +return kvm_block_mapping_supported (ctx, phys); }
@@ -923,7 +910,7 @@ static int stage2_map_walker_try_leaf(const struct kvm_pgtable_visit_ctx *ctx,if (!stage2_leaf_mapping_allowed (ctx, data))return -E2BIG ; -if (kvm_phys_is_valid (phys)) +if (!data->owner_update) new =kvm_init_valid_leaf_pte (phys, data->attr, ctx->level);else new =kvm_init_invalid_leaf_owner (data->owner_id);
@@ -1085,11 +1072,11 @@ int kvm_pgtable_stage2_set_owner(struct kvm_pgtable *pgt, u64 addr, u64 size, {int ret;struct stage2_map_data map_data = { - .phys =KVM_PHYS_INVALID , .mmu = pgt->mmu, .memcache = mc, .owner_id = owner_id, .force_pte = true, + .owner_update = true, };struct kvm_pgtable_walker walker = { .cb = stage2_map_walker,
Signature · 1 line
2.47.0.338.g60cca15819-goog
Will Deacon
maintainerRe: [PATCH v2 4/6] arm64/kvm: Avoid invalid physical addresses to signal owner updates
Hi Ard,
Quoted 17 lines · Ard Biesheuvel
From: Ard Biesheuvel <[email protected]>
The pKVM stage2 mapping code relies on an invalid physical address to signal to the internal API that only the
owner_idfields of descriptors should be updated, and these are stored in the high bits of invalid descriptors covering memory that has been donated to protected guests, and is therefore unmapped from the host stage-2 page tables.Given that these invalid PAs are never stored into the descriptors, it is better to rely on an explicit flag, to clarify the API and to avoid confusion regarding whether or not the output address of a descriptor can ever be invalid to begin with (which is not the case with LPA2).
That removes a dependency on the logic that reasons about the maximum PA range, which differs on LPA2 capable CPUs based on whether LPA2 is enabled or not, and will be further clarified in subsequent patches.
Quoted 5 lines
Cc Quentin Perret <[email protected]>Signed-off-by Ard Biesheuvel <[email protected]>--- arch/arm64/kvm/hyp/pgtable.c | 33 ++++++-------------- 1 file changed, 10 insertions(+), 23 deletions(-)
Sorry that I didn't reply again on v1, but I have an annoying request that would make this a little easier for me to follow (since I'm tainted with the pKVM stack in Android that we're gradually landing upstream):
Quoted 29 lines
arch/arm64/kvm/hyp/pgtable.c +1
-9@@ -35,14 +35,6 @@ static bool kvm_pgtable_walk_skip_cmo(const struct kvm_pgtable_visit_ctx *ctx)return unlikely (ctx->flags &KVM_PGTABLE_WALK_SKIP_CMO ); } -static bool kvm_phys_is_valid (u64 phys) -{ -u64 parange_max =kvm_get_parange_max (); -u8 shift =id_aa64mmfr0_parange_to_phys_shift (parange_max); - -return phys <BIT (shift); -} -static bool kvm_block_mapping_supported (const struct kvm_pgtable_visit_ctx *ctx,u64 phys) {u64 granule =kvm_granule_size (ctx->level);@@ -53,7 +45,7 @@ static bool kvm_block_mapping_supported(const struct kvm_pgtable_visit_ctx *ctx,if (granule > (ctx->end - ctx->addr))return false; -if (kvm_phys_is_valid (phys) && !IS_ALIGNED (phys, granule)) +if (!IS_ALIGNED (phys, granule))return false;return IS_ALIGNED (ctx->addr, granule);
arch/arm64/kvm/hyp/pgtable.c struct stage2_map_data { · line 584
Quoted 6 lines
arch/arm64/kvm/hyp/pgtable.c +3
-0@@ -587,6 +579,9 @@ struct stage2_map_data {/* Force mappings to page granularity */ bool force_pte; + +/* Walk should update owner_id only */ +bool owner_update;
Can you rename this to "annotation", please? We'll eventually land other types of invalid pte than ownership (e.g. MMIO_GUARD) and, given that the ownership walker is caught by the 'force_pte' flag, it's a little more generic.
Again, apologies I didn't ask for this earlier.
Will
PATCH v2 5/6 arm64: Kconfig: force ARM64_PAN=y when enabling TTBR0 sw PAN
In reply to Ard BiesheuvelFrom: Ard Biesheuvel <[email protected]>
There are a couple of instances of Kconfig constraints where PAN must be enabled too if TTBR0 sw PAN is enabled, primarily to avoid dealing with the modified TTBR0_EL1 sysreg format that is used when 52-bit physical addressing and/or CnP are enabled (support for either implies support for hardware PAN as well, which will supersede PAN emulation if both are available)
Let's simplify this, and always enable ARM64_PAN when enabling TTBR0 sw PAN. This decouples the PAN configuration from the VA size selection, permitting us to simplify the latter in subsequent patches. (Note that PAN and TTBR0 sw PAN can still be disabled after this patch, but not independently)
To avoid a convoluted circular Kconfig dependency involving KCSAN, make ARM64_MTE select ARM64_PAN too, instead of depending on it.
--- arch/arm64/Kconfig | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
arch/arm64/Kconfig +2 -4
@@ -1379,7 +1379,6 @@ config ARM64_VA_BITS_48 config ARM64_VA_BITS_52 bool "52-bit" - depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN help Enable 52-bit virtual addressing for userspace when explicitly requested via a hint to mmap(). The kernel will also use 52-bit
@@ -1431,7 +1430,6 @@ config ARM64_PA_BITS_48 config ARM64_PA_BITS_52 bool "52-bit" depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 - depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN help Enable support for a 52-bit physical address space, introduced as part of the ARMv8.2-LPA extension.
@@ -1681,6 +1679,7 @@ config RODATA_FULL_DEFAULT_ENABLED config ARM64_SW_TTBR0_PAN bool "Emulate Privileged Access Never using TTBR0_EL1 switching" depends on !KCSAN + select ARM64_PAN help Enabling this option prevents the kernel from accessing user-space memory directly by pointing TTBR0_EL1 to a reserved
@@ -1937,7 +1936,6 @@ config ARM64_RAS_EXTN config ARM64_CNP bool "Enable support for Common Not Private (CNP) translations" default y - depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN help Common Not Private (CNP) allows translation table entries to be shared between different PEs in the same inner shareable
@@ -2132,7 +2130,7 @@ config ARM64_MTE depends on AS_HAS_ARMV8_5 depends on AS_HAS_LSE_ATOMICS # Required for tag checking in the uaccess routines - depends on ARM64_PAN + select ARM64_PAN select ARCH_HAS_SUBPAGE_FAULTS select ARCH_USES_HIGH_VMA_FLAGS select ARCH_USES_PG_ARCH_2
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2.47.0.338.g60cca15819-goog
PATCH v2 6/6 arm64/mm: Drop configurable 48-bit physical address space limit
In reply to Ard BiesheuvelFrom: Ard Biesheuvel <[email protected]>
Currently, the maximum supported physical address space can be configured as either 48 bits or 52 bits. The only remaining difference between these in practice is that the former omits the masking and shifting required to construct TTBR and PTE values, which carry bits #48 and higher disjoint from the rest of the physical address.
The overhead of performing these additional calculations is negligible, and so there is little reason to retain support for two different configurations, and we can simply support whatever the hardware supports.
--- arch/arm64/Kconfig | 31 +------------------- arch/arm64/include/asm/assembler.h | 13 ++------ arch/arm64/include/asm/cpufeature.h | 3 +- arch/arm64/include/asm/kvm_pgtable.h | 3 +- arch/arm64/include/asm/pgtable-hwdef.h | 6 +--- arch/arm64/include/asm/pgtable-prot.h | 4 +-- arch/arm64/include/asm/pgtable.h | 11 +------ arch/arm64/include/asm/sysreg.h | 6 ---- arch/arm64/mm/pgd.c | 9 +++--- arch/arm64/mm/proc.S | 2 -- scripts/gdb/linux/constants.py.in | 1 - tools/arch/arm64/include/asm/sysreg.h | 6 ---- 12 files changed, 14 insertions(+), 81 deletions(-)
arch/arm64/Kconfig +1 -30
@@ -1416,38 +1416,9 @@ config ARM64_VA_BITS default 48 if ARM64_VA_BITS_48 default 52 if ARM64_VA_BITS_52 -choice - prompt "Physical address space size" - default ARM64_PA_BITS_48 - help - Choose the maximum physical address range that the kernel will - support. - -config ARM64_PA_BITS_48 - bool "48-bit" - depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 - -config ARM64_PA_BITS_52 - bool "52-bit" - depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 - help - Enable support for a 52-bit physical address space, introduced as - part of the ARMv8.2-LPA extension. - - With this enabled, the kernel will also continue to work on CPUs that - do not support ARMv8.2-LPA, but with some added memory overhead (and - minor performance overhead). - -endchoice - -config ARM64_PA_BITS - int - default 48 if ARM64_PA_BITS_48 - default 52 if ARM64_PA_BITS_52 - config ARM64_LPA2 def_bool y - depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES + depends on !ARM64_64K_PAGES choice prompt "Endianness"
arch/arm64/include/asm/assembler.h +2 -11
@@ -342,14 +342,13 @@ alternative_cb_end mrs \tmp0, ID_AA64MMFR0_EL1// Narrow PARange to fit the PS field in TCR_ELx ubfx \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3 - mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX #ifdef CONFIG_ARM64_LPA2 alternative_if_not ARM64_HAS_VA52 mov \tmp1, #ID_AA64MMFR0_EL1_PARANGE_48 -alternative_else_nop_endif -#endif cmp \tmp0, \tmp1 csel \tmp0, \tmp1, \tmp0, hi +alternative_else_nop_endif +#endif bfi \tcr, \tmp0, \pos, #3 .endm
@@ -599,21 +598,13 @@ alternative_endif* ttbr: returns the TTBR value */ .macro phys_to_ttbr, ttbr, phys -#ifdef CONFIG_ARM64_PA_BITS_52 orr \ttbr, \phys, \phys, lsr #46 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 -#else - mov \ttbr, \phys -#endif .endm .macro phys_to_pte, pte, phys -#ifdef CONFIG_ARM64_PA_BITS_52 orr \pte, \phys, \phys, lsr #PTE_ADDR_HIGH_SHIFT and \pte, \pte, #PHYS_TO_PTE_ADDR_MASK -#else - mov \pte, \phys -#endif .endm/*
arch/arm64/include/asm/cpufeature.h +1 -2
@@ -885,9 +885,8 @@ static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)* However, by the "D10.1.4 Principles of the ID scheme * for fields in ID registers", ARM DDI 0487C.a, any new * value is guaranteed to be higher than what we know already. -* As a safe limit, we return the limit supported by the kernel. */ -default :return CONFIG_ARM64_PA_BITS ; +default :return 52 ; } }
arch/arm64/include/asm/kvm_pgtable.h +1 -2
@@ -30,8 +30,7 @@static inline u64 kvm_get_parange_max (void ) { -if (kvm_lpa2_is_enabled () || - (IS_ENABLED (CONFIG_ARM64_PA_BITS_52 ) &&PAGE_SHIFT ==16 )) +if (kvm_lpa2_is_enabled () ||PAGE_SHIFT ==16 )return ID_AA64MMFR0_EL1_PARANGE_52 ;else return ID_AA64MMFR0_EL1_PARANGE_48 ;
arch/arm64/include/asm/pgtable-hwdef.h +1 -5
@@ -176,7 +176,6 @@#define PTE_SWBITS_MASK _AT(pteval_t, (BIT(63) | GENMASK(58, 55)))#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (50 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) -#ifdef CONFIG_ARM64_PA_BITS_52 #ifdef CONFIG_ARM64_64K_PAGES #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12)#define PTE_ADDR_HIGH_SHIFT 36
@@ -186,7 +185,6 @@#define PTE_ADDR_HIGH_SHIFT 42#define PHYS_TO_PTE_ADDR_MASK GENMASK_ULL(49, 8)#endif -#endif /* * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
@@ -327,12 +325,10 @@/* * TTBR. */ -#ifdef CONFIG_ARM64_PA_BITS_52 /* -* TTBR_ELx[1] is RES0 in this configuration. +* TTBR_ELx[1] is RES0 when using 52-bit physical addressing */ #define TTBR_BADDR_MASK_52 GENMASK_ULL(47, 2) -#endif #ifdef CONFIG_ARM64_VA_BITS_52 /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
arch/arm64/include/asm/pgtable-prot.h +2 -2
@@ -81,7 +81,7 @@ extern unsigned long prot_ns_shared;#define lpa2_is_enabled () false#define PTE_MAYBE_SHARED PTE_SHARED#define PMD_MAYBE_SHARED PMD_SECT_S -#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS) +#define PHYS_MASK_SHIFT (52)#else static inline bool __pure lpa2_is_enabled (void ) {
@@ -90,7 +90,7 @@ static inline bool __pure lpa2_is_enabled(void)#define PTE_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PTE_SHARED)#define PMD_MAYBE_SHARED (lpa2_is_enabled() ? 0 : PMD_SECT_S) -#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? CONFIG_ARM64_PA_BITS : 48) +#define PHYS_MASK_SHIFT (lpa2_is_enabled() ? 52 : 48)#endif /*
arch/arm64/include/asm/pgtable.h +1 -10
@@ -69,10 +69,9 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];pr_err ("%s:%d: bad pte %016llx.\n" , __FILE__, __LINE__,pte_val (e))/* -* Macros to convert between a physical address and its placement in a +* Helpers to convert between a physical address and its placement in a * page table entry, taking care of 52-bit addresses. */ -#ifdef CONFIG_ARM64_PA_BITS_52 static inline phys_addr_t __pte_to_phys (pte_t pte) {pte_val (pte) &= ~PTE_MAYBE_SHARED ;
@@ -83,10 +82,6 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) {return (phys | (phys >>PTE_ADDR_HIGH_SHIFT )) &PHYS_TO_PTE_ADDR_MASK ; } -#else -#define __pte_to_phys (pte) (pte_val(pte) & PTE_ADDR_LOW) -#define __phys_to_pte_val (phys) (phys) -#endif #define pte_pfn (pte) (__pte_to_phys(pte) >> PAGE_SHIFT)#define pfn_pte (pfn,prot) \
@@ -1495,11 +1490,7 @@ static inline void update_mmu_cache_range(struct vm_fault *vmf, update_mmu_cache_range(NULL, vma, addr, ptep, 1)#define update_mmu_cache_pmd (vma, address, pmd) do { } while (0) -#ifdef CONFIG_ARM64_PA_BITS_52 #define phys_to_ttbr (addr) (((addr) | ((addr) >> 46)) & TTBR_BADDR_MASK_52) -#else -#define phys_to_ttbr (addr) (addr) -#endif /* * On arm64 without hardware Access Flag, copying from user will fail because
arch/arm64/include/asm/sysreg.h +0 -6
@@ -916,12 +916,6 @@#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 -#ifdef CONFIG_ARM64_PA_BITS_52 -#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 -#else -#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 -#endif -#if defined(CONFIG_ARM64_4K_PAGES )#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT#define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT
arch/arm64/mm/pgd.c +5 -4
@@ -48,20 +48,21 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)void __init pgtable_cache_init (void ) { +unsigned int pgd_size =PGD_SIZE ; +if (pgdir_is_page_size ())return ; -#ifdef CONFIG_ARM64_PA_BITS_52 /* * With 52-bit physical addresses, the architecture requires the * top-level table to be aligned to at least 64 bytes. */ -BUILD_BUG_ON (PGD_SIZE <64 ); -#endif +if (PHYS_MASK_SHIFT >=52 ) + pgd_size =max (pgd_size,64 );/* * Naturally aligned pgds required by the architecture. */ - pgd_cache =kmem_cache_create ("pgd_cache" ,PGD_SIZE ,PGD_SIZE , + pgd_cache =kmem_cache_create ("pgd_cache" , pgd_size, pgd_size,SLAB_PANIC ,NULL ); }
arch/arm64/mm/proc.S +0 -2
@@ -197,10 +197,8 @@ SYM_FUNC_ALIAS(__pi_idmap_cpu_replace_ttbr1, idmap_cpu_replace_ttbr1) .macro pte_to_phys, phys, pte and \phys, \pte, #PTE_ADDR_LOW -#ifdef CONFIG_ARM64_PA_BITS_52 and \pte, \pte, #PTE_ADDR_HIGH orr \phys, \phys, \pte, lsl #PTE_ADDR_HIGH_SHIFT -#endif .endm .macro kpti_mk_tbl_ng, type, num_entries
scripts/gdb/linux/constants.py.in +0 -1
@@ -141,7 +141,6 @@ LX_CONFIG(CONFIG_ARM64_4K_PAGES) LX_CONFIG(CONFIG_ARM64_16K_PAGES) LX_CONFIG(CONFIG_ARM64_64K_PAGES) if IS_BUILTIN(CONFIG_ARM64): - LX_VALUE(CONFIG_ARM64_PA_BITS) LX_VALUE(CONFIG_ARM64_VA_BITS) LX_VALUE(CONFIG_PAGE_SHIFT) LX_VALUE(CONFIG_ARCH_FORCE_MAX_ORDER)
tools/arch/arm64/include/asm/sysreg.h +0 -6
@@ -574,12 +574,6 @@#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 -#ifdef CONFIG_ARM64_PA_BITS_52 -#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 -#else -#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 -#endif -#if defined(CONFIG_ARM64_4K_PAGES )#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
Signature · 1 line
2.47.0.338.g60cca15819-goog