Add pinctrl support for mt7988
Subsystems (5)
v6 cover Add pinctrl support for mt7988
From: Frank Wunderlich <[email protected]>
This series adds pinctrl driver, dt-bindings and dts node for pinctrl on mediatek mt7988 SoC.
changes in v6:
- some fixes to binding
- changed title and fixed typo in bpi-r4 patch
- added RB's
changes in v5:
- rebased to 6.13-rc1
- moved dt nodes with mutliple options to BPI-R4 board
- changes suggested by angelo in v4
- changed example in binding and dt node to not using const MTK_DRIVE_8mA
changes in v4:
- fixed fixed string binding error
changes in v3:
- rebase on rafals dts patches
- update binding to have mux subnode as fixed string and conf with optional suffix
changes in v2:
binding:
- drop gpio-cells description
- move ref in mux subnode up
- order uart-functions alphanumeric and fix typo dts:
- fix indentation of reg-values
Daniel Golle (2):
pinctrl: mediatek: add support for MTK_PULL_PD_TYPE
pinctrl: mediatek: add MT7988 pinctrl driver
Frank Wunderlich (3):
dt-bindings: pinctrl: add binding for MT7988 SoC
arm64: dts: mediatek: mt7988: Add pinctrl support
arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl subnodes for bpi-r4
.../pinctrl/mediatek,mt7988-pinctrl.yaml | 575 ++++++ .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++ arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 + drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 +- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + 8 files changed, 2445 insertions(+), 11 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
Signature · 1 line
2.43.0
PATCH v6 1/5 pinctrl: mediatek: add support for MTK_PULL_PD_TYPE
From: Daniel Golle <[email protected]>
The MediaTek MT7988 SoC got some pins which only got configurable pull-down but unlike previous designs there is no pull-up option. Add new type MTK_PULL_PD_TYPE to support configuring such pins.
Signed-off-by Daniel Golle <[email protected]>
Signed-off-by Frank Wunderlich <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
---
v5:
- add changes suggested by angelo (pd_only), long version, tested with emmc
--- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 73 ++++++++++++++++--- .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + 2 files changed, 63 insertions(+), 11 deletions(-)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +62 -11
@@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);*/ static int mtk_pinconf_bias_set_pu_pd (struct mtk_pinctrl *hw,const struct mtk_pin_desc *desc, -u32 pullup,u32 arg) +u32 pullup,u32 arg,bool pd_only) {int err, pu, pd;
@@ -587,18 +587,34 @@ static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw, pu =0 ; pd =1 ; }else { - err = -EINVAL ; - goto out; +return -EINVAL ; } - err =mtk_hw_set_value (hw, desc,PINCTRL_PIN_REG_PU , pu); -if (err) - goto out; +if (!pd_only) { + err =mtk_hw_set_value (hw, desc,PINCTRL_PIN_REG_PU , pu); +if (err) +return err; + } - err =mtk_hw_set_value (hw, desc,PINCTRL_PIN_REG_PD , pd); +return mtk_hw_set_value (hw, desc,PINCTRL_PIN_REG_PD , pd); +} + +static int mtk_pinconf_bias_set_pd (struct mtk_pinctrl *hw, +const struct mtk_pin_desc *desc, +u32 pullup,u32 arg) +{ +int err, pd; + +if (arg !=MTK_DISABLE && arg !=MTK_ENABLE ) +return -EINVAL ; + +if (arg ==MTK_DISABLE || pullup) + pd =0 ; +else if (!pullup) + pd =1 ; + +return mtk_hw_set_value (hw, desc,PINCTRL_PIN_REG_PD , pd); -out: -return err; } static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
@@ -737,7 +753,7 @@ static int mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl *hw,return err; } -return mtk_pinconf_bias_set_pu_pd (hw, desc, pullup, enable); +return mtk_pinconf_bias_set_pu_pd (hw, desc, pullup, enable, false); } int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
@@ -758,8 +774,14 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,return 0 ; } +if (try_all_type &MTK_PULL_PD_TYPE ) { + err =mtk_pinconf_bias_set_pu_pd (hw, desc, pullup, arg, true); +if (!err) +return err; + } +if (try_all_type &MTK_PULL_PU_PD_TYPE ) { - err =mtk_pinconf_bias_set_pu_pd (hw, desc, pullup, arg); + err =mtk_pinconf_bias_set_pu_pd (hw, desc, pullup, arg, false);if (!err)return 0 ; }
@@ -878,6 +900,29 @@ static int mtk_pinconf_bias_get_pu_pd(struct mtk_pinctrl *hw,return err; } +static int mtk_pinconf_bias_get_pd (struct mtk_pinctrl *hw, +const struct mtk_pin_desc *desc, +u32 *pullup,u32 *enable) +{ +int err, pd; + + err =mtk_hw_get_value (hw, desc,PINCTRL_PIN_REG_PD , &pd); +if (err) + goto out; + +if (pd ==0 ) { + *pullup =0 ; + *enable =MTK_DISABLE ; + }else if (pd ==1 ) { + *pullup =0 ; + *enable =MTK_ENABLE ; + }else + err = -EINVAL ; + +out: +return err; +} +static int mtk_pinconf_bias_get_pullsel_pullen (struct mtk_pinctrl *hw,const struct mtk_pin_desc *desc,u32 *pullup,u32 *enable)
@@ -947,6 +992,12 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,return 0 ; } +if (try_all_type &MTK_PULL_PD_TYPE ) { + err =mtk_pinconf_bias_get_pd (hw, desc, pullup, enable); +if (!err) +return err; + } +if (try_all_type &MTK_PULL_PU_PD_TYPE ) { err =mtk_pinconf_bias_get_pu_pd (hw, desc, pullup, enable);if (!err)
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +1 -0
@@ -24,6 +24,7 @@* turned on/off itself. But it can't be selected pull up/down */ #define MTK_PULL_RSEL_TYPE BIT(3) +#define MTK_PULL_PD_TYPE BIT(4)/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by * MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE. */
Signature · 1 line
2.43.0
PATCH v6 2/5 pinctrl: mediatek: add MT7988 pinctrl driver
In reply to Frank WunderlichFrom: Daniel Golle <[email protected]>
Add pinctrl driver for the MediaTek MT7988 SoC.
Signed-off-by Sam Shih <[email protected]>
Signed-off-by Daniel Golle <[email protected]>
[correctly initialise for the function_desc structure]
Signed-off-by Arınç ÜNAL <[email protected]>
Signed-off-by Frank Wunderlich <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
---
v5:
- changes requested by angelo
- lowercase mt7988_pinctrl_reg_page
- compatible match in one line
- HW debounce is only available for pins 0 to 15 and does not support pins with numbers 16 or higher.
- add additional PWM pingroups
--- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1556 +++++++++++++++++++++ 3 files changed, 1564 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7988.c
drivers/pinctrl/mediatek/Kconfig +7 -0
@@ -202,6 +202,13 @@ config PINCTRL_MT7986 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT7988 + bool "Mediatek MT7988 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_MOORE + config PINCTRL_MT8167 bool "MediaTek MT8167 pin control" depends on OF
drivers/pinctrl/mediatek/Makefile +1 -0
@@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o +obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
drivers/pinctrl/mediatek/pinctrl-mt7988.c new file +1556 -0
1,556 lines not on this page · raw message
Signature · 1 line
2.43.0
PATCH v6 3/5 dt-bindings: pinctrl: add binding for MT7988 SoC
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
This adds bindings for MT7988 pinctrl driver.
Signed-off-by Frank Wunderlich <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
---
changes in v6:
changes suggested by rob
- remove quotes around mux
- use const instead of enum if only one value is possible
changes in v5 (so not adding RB from Rob given in v4):
- do not use MTK_DRIVE_8mA in example
- add _0 functions for pwm
changes in v4:
- dt-binding: pinctrl: fix dt_binding_check fixed-string error
'^mux$' should not be valid under {'pattern': '^\\^[a-zA-Z0-9,\\-._#@]+\\$$'}
hint: Fixed strings belong in 'properties', not 'patternProperties'
changes in v3:
- limit conf subnode name with optional suffix like mmc on mt7986
- match mux subnode without wildcards
changes in v2:
- drop gpio-cells description
- move ref in mux subnode up
- order uart-functions alphanumeric and fix typo
--- .../pinctrl/mediatek,mt7988-pinctrl.yaml | 575 ++++++++++++++++++ 1 file changed, 575 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml new file +575 -0
@@ -0,0 +1,575 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7988 Pin Controller + +maintainers: + - Sean Wang <[email protected]> + +description: + The MediaTek's MT7988 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7988-pinctrl + + reg: + minItems: 7 + maxItems: 7 + + reg-names: + items: + - const: gpio + - const: iocfg_tr + - const: iocfg_br + - const: iocfg_rb + - const: iocfg_lb + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + properties: + mux: + type: object + additionalProperties: false + $ref: /schemas/pinctrl/pinmux-node.yaml + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "tops_jtag0_0" "jtag" 0, 1, 2, 3, 4 + "wo0_jtag" "jtag" 50, 51, 52, 53, 54 + "wo1_jtag" "jtag" 50, 51, 52, 53, 54 + "wo2_jtag" "jtag" 50, 51, 52, 53, 54 + "jtag" "jtag" 58, 59, 60, 61, 62 + "tops_jtag0_1" "jtag" 58, 59, 60, 61, 62 + "int_usxgmii" "int_usxgmii" 2, 3 + "pwm0" "pwm" 57 + "pwm1" "pwm" 21 + "pwm2" "pwm" 80 + "pwm2_0" "pwm" 58 + "pwm3" "pwm" 81 + "pwm3_0" "pwm" 59 + "pwm4" "pwm" 82 + "pwm4_0" "pwm" 60 + "pwm5" "pwm" 83 + "pwm5_0" "pwm" 61 + "pwm6" "pwm" 69 + "pwm6_0" "pwm" 62 + "pwm7" "pwm" 70 + "pwm7_0" "pwm" 4 + "dfd" "dfd" 0, 1, 2, 3, 4 + "xfi_phy0_i2c0" "i2c" 0, 1 + "xfi_phy1_i2c0" "i2c" 0, 1 + "xfi_phy_pll_i2c0" "i2c" 3, 4 + "xfi_phy_pll_i2c1" "i2c" 3, 4 + "i2c0_0" "i2c" 5, 6 + "i2c1_sfp" "i2c" 5, 6 + "xfi_pextp_phy0_i2c" "i2c" 5, 6 + "xfi_pextp_phy1_i2c" "i2c" 5, 6 + "i2c0_1" "i2c" 15, 16 + "u30_phy_i2c0" "i2c" 15, 16 + "u32_phy_i2c0" "i2c" 15, 16 + "xfi_phy0_i2c1" "i2c" 15, 16 + "xfi_phy1_i2c1" "i2c" 15, 16 + "xfi_phy_pll_i2c2" "i2c" 15, 16 + "i2c1_0" "i2c" 17, 18 + "u30_phy_i2c1" "i2c" 17, 18 + "u32_phy_i2c1" "i2c" 17, 18 + "xfi_phy_pll_i2c3" "i2c" 17, 18 + "sgmii0_i2c" "i2c" 17, 18 + "sgmii1_i2c" "i2c" 17, 18 + "i2c1_2" "i2c" 69, 70 + "i2c2_0" "i2c" 69, 70 + "i2c2_1" "i2c" 71, 72 + "mdc_mdio0" "eth" 5, 6 + "2p5g_ext_mdio" "eth" 28, 29 + "gbe_ext_mdio" "eth" 30, 31 + "mdc_mdio1" "eth" 69, 70 + "pcie_wake_n0_0" "pcie" 7 + "pcie_clk_req_n0_0" "pcie" 8 + "pcie_wake_n3_0" "pcie" 9 + "pcie_clk_req_n3" "pcie" 10 + "pcie_clk_req_n0_1" "pcie" 10 + "pcie_p0_phy_i2c" "pcie" 7, 8 + "pcie_p1_phy_i2c" "pcie" 7, 8 + "pcie_p3_phy_i2c" "pcie" 9, 10 + "pcie_p2_phy_i2c" "pcie" 7, 8 + "ckm_phy_i2c" "pcie" 9, 10 + "pcie_wake_n0_1" "pcie" 13 + "pcie_wake_n3_1" "pcie" 14 + "pcie_2l_0_pereset" "pcie" 19 + "pcie_1l_1_pereset" "pcie" 20 + "pcie_clk_req_n2_1" "pcie" 63 + "pcie_2l_1_pereset" "pcie" 73 + "pcie_1l_0_pereset" "pcie" 74 + "pcie_wake_n1_0" "pcie" 75 + "pcie_clk_req_n1" "pcie" 76 + "pcie_wake_n2_0" "pcie" 77 + "pcie_clk_req_n2_0" "pcie" 78 + "pcie_wake_n2_1" "pcie" 79 + "pmic" "pmic" 11 + "watchdog" "watchdog" 12 + "spi0_wp_hold" "spi" 22, 23 + "spi0" "spi" 24, 25, 26, 27 + "spi1" "spi" 28, 29, 30, 31 + "spi2" "spi" 32, 33, 34, 35 + "spi2_wp_hold" "spi" 36, 37 + "snfi" "flash" 22, 23, 24, 25, 26, 27 + "emmc_45" "flash" 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 + "sdcard" "flash" 32, 33, 34, 35, 36, 37 + "emmc_51" "flash" 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 + "uart2" "uart" 0, 1, 2, 3 + "tops_uart0_0" "uart" 22, 23 + "uart2_0" "uart" 28, 29, 30, 31 + "uart1_0" "uart" 32, 33, 34, 35 + "uart2_1" "uart" 32, 33, 34, 35 + "net_wo0_uart_txd_0" "uart" 28 + "net_wo1_uart_txd_0" "uart" 29 + "net_wo2_uart_txd_0" "uart" 30 + "tops_uart1_0" "uart" 28, 29 + "tops_uart0_1" "uart" 30, 31 + "tops_uart1_1" "uart" 36, 37 + "uart0" "uart" 55, 56 + "tops_uart0_2" "uart" 55, 56 + "uart2_2" "uart" 50, 51, 52, 53 + "uart1_1" "uart" 58, 59, 60, 61 + "uart2_3" "uart" 58, 59, 60, 61 + "uart1_2" "uart" 80, 81, 82, 83 + "uart1_2_lite" "uart" 80, 81 + "tops_uart1_2" "uart" 80, 81 + "net_wo0_uart_txd_1" "uart" 80 + "net_wo1_uart_txd_1" "uart" 81 + "net_wo2_uart_txd_1" "uart" 82 + "udi" "udi" 32, 33, 34, 35, 36 + "i2s" "audio" 50, 51, 52, 53, 54 + "pcm" "audio" 50, 51, 52, 53 + "gbe0_led1" "led" 58 + "gbe1_led1" "led" 59 + "gbe2_led1" "led" 60 + "gbe3_led1" "led" 61 + "2p5gbe_led1" "led" 62 + "gbe0_led0" "led" 64 + "gbe1_led0" "led" 65 + "gbe2_led0" "led" 66 + "gbe3_led0" "led" 67 + "2p5gbe_led0" "led" 68 + "drv_vbus_p1" "usb" 63 + "drv_vbus" "usb" 79 + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi, + uart, udi, usb, watchdog] + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: audio + then: + properties: + groups: + enum: [i2s, pcm] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag] + - if: + properties: + function: + const: int_usxgmii + then: + properties: + groups: + const: int_usxgmii + - if: + properties: + function: + const: dfd + then: + properties: + groups: + const: dfd + - if: + properties: + function: + const: flash + then: + properties: + groups: + enum: [emmc_45, emmc_51, sdcard, snfi] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0, + xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c, + xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0, + xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0, + u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c, + sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1, + gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1] + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0, + pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c, + pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c, + pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset, + pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset, + pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1, + pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1, + pcie_clk_req_n0_1] + maxItems: 3 + - if: + properties: + function: + const: pmic + then: + properties: + groups: + const: pmic + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0, + pwm6, pwm6_0, pwm7, pwm7_0] + maxItems: 2 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold] + maxItems: 2 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0, + net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1, + tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0, + tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2, + uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3] + maxItems: 2 + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + const: watchdog + - if: + properties: + function: + const: udi + then: + properties: + groups: + const: udi + - if: + properties: + function: + const: usb + then: + properties: + groups: + items: + enum: [drv_vbus, drv_vbus_p1] + maxItems: 1 + + patternProperties: + '^conf(-[-a-z]*)?$': + type: object + additionalProperties: false + description: + pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC, + SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N, + PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG, + GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL, + I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1, + SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK, + SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL, + EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5, + EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1, + EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK, + PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK, + UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS, + JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C, + LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA, + PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N, + PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N, + PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0, + UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS] + maxItems: 84 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 84>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + pins = "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength = <8>; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + }; + };
Signature · 1 line
2.43.0
PATCH v6 4/5 arm64: dts: mediatek: mt7988: Add pinctrl support
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add mt7988a pinctrl node.
Signed-off-by Frank Wunderlich <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
---
v5:
- drop pins with second function
v2:
- fix wrong alignment of reg values
--- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+)
arch/arm64/boot/dts/mediatek/mt7988a.dtsi +54 -0
@@ -3,6 +3,7 @@ #include <dt-bindings/clock/mediatek,mt7988-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/mt65xx.h> / { compatible = "mediatek,mt7988a";
@@ -105,6 +106,59 @@ clock-controller@1001e000 { #clock-cells = <1>; }; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 84>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; + }; + pwm@10048000 { compatible = "mediatek,mt7988-pwm"; reg = <0 0x10048000 0 0x1000>;
Signature · 1 line
2.43.0
PATCH v6 5/5 arm64: dts: mediatek: mt7988a-bpi-r4: Add pinctrl subnodes for bpi-r4
In reply to Frank WunderlichFrom: Frank Wunderlich <[email protected]>
Add board specific pinctrl configurations on Bananapi R4.
Signed-off-by Frank Wunderlich <[email protected]>
Reviewed-by AngeloGioacchino Del Regno <[email protected]>
---
changes in v6:
- fix typo
- start title uppercase
- use bpi-r4 prefix
--- .../dts/mediatek/mt7988a-bananapi-bpi-r4.dts | 189 ++++++++++++++++++ 1 file changed, 189 insertions(+)
arch/arm64/boot/dts/mediatek/mt7988a-bananapi-bpi-r4.dts +189 -0
@@ -9,3 +9,192 @@ / { model = "Banana Pi BPI-R4"; chassis-type = "embedded"; }; + +&pio { + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + pins = "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength = <8>; + }; + }; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + i2c1_pins: i2c1-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_0"; + }; + }; + + i2c1_sfp_pins: i2c1-sfp-g0-pins { + mux { + function = "i2c"; + groups = "i2c1_sfp"; + }; + }; + + i2c2_0_pins: i2c2-g0-pins { + mux { + function = "i2c"; + groups = "i2c2_0"; + }; + }; + + i2c2_1_pins: i2c2-g1-pins { + mux { + function = "i2c"; + groups = "i2c2_1"; + }; + }; + + gbe0_led0_pins: gbe0-led0-pins { + mux { + function = "led"; + groups = "gbe0_led0"; + }; + }; + + gbe1_led0_pins: gbe1-led0-pins { + mux { + function = "led"; + groups = "gbe1_led0"; + }; + }; + + gbe2_led0_pins: gbe2-led0-pins { + mux { + function = "led"; + groups = "gbe2_led0"; + }; + }; + + gbe3_led0_pins: gbe3-led0-pins { + mux { + function = "led"; + groups = "gbe3_led0"; + }; + }; + + gbe0_led1_pins: gbe0-led1-pins { + mux { + function = "led"; + groups = "gbe0_led1"; + }; + }; + + gbe1_led1_pins: gbe1-led1-pins { + mux { + function = "led"; + groups = "gbe1_led1"; + }; + }; + + gbe2_led1_pins: gbe2-led1-pins { + mux { + function = "led"; + groups = "gbe2_led1"; + }; + }; + + gbe3_led1_pins: gbe3-led1-pins { + mux { + function = "led"; + groups = "gbe3_led1"; + }; + }; + + i2p5gbe_led0_pins: 2p5gbe-led0-pins { + mux { + function = "led"; + groups = "2p5gbe_led0"; + }; + }; + + i2p5gbe_led1_pins: 2p5gbe-led1-pins { + mux { + function = "led"; + groups = "2p5gbe_led1"; + }; + }; + + mmc0_pins_emmc_45: mmc0-emmc-45-pins { + mux { + function = "flash"; + groups = "emmc_45"; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + + snfi_pins: snfi-pins { + mux { + function = "flash"; + groups = "snfi"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0"; + }; + }; + + spi0_flash_pins: spi0-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spi1_pins: spi1-pins { + mux { + function = "spi"; + groups = "spi1"; + }; + }; + + spi2_pins: spi2-pins { + mux { + function = "spi"; + groups = "spi2"; + }; + }; + + spi2_flash_pins: spi2-flash-pins { + mux { + function = "spi"; + groups = "spi2", "spi2_wp_hold"; + }; + }; +};
Signature · 1 line
2.43.0