Add support for AD4170

From: Ana-Maria Cusco <[email protected]>

Add defines to improve readability of AD4170 device tree nodes.

Signed-off-by Ana-Maria Cusco <[email protected]>

Co-developed-by Marcelo Schmitt <[email protected]>

Signed-off-by Marcelo Schmitt <[email protected]>

---
 include/dt-bindings/iio/adc/adi,ad4170.h | 96 ++++++++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 include/dt-bindings/iio/adc/adi,ad4170.h

include/dt-bindings/iio/adc/adi,ad4170.h new file +0 -0

new file mode 100644
index 000000000000..a508b37e9a46

Add device tree documentation for AD4170 sigma-delta ADCs.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4170.yaml          | 473 ++++++++++++++++++
 1 file changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml

Add device tree documentation for AD4170 sigma-delta ADCs.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4170.yaml          | 473 ++++++++++++++++++
 1 file changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +44 -0

new file mode 100644
index 000000000000..8c5defc614ee
@@ -0,0 +1,473 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4170 Analog to Digital Converter
+
+maintainers:
+  - Marcelo Schmitt <[email protected]>
+
+description: |
+  Analog Devices AD4170 Analog to Digital Converter.
+  Specifications can be found at:
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    enum:
+      - adi,ad4170
+
+  avss-supply:
+    description:
+      Referece voltage supply for AVDD. AVSS can be set below 0V to provide a
+      bipolar power supply to AD4170-4. Must be −2.625V at minimum, 0V maximum.
+      If not specified, this is assumed to be analog ground.
+
+  avdd-supply:
+    description:
+      A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
+
+  iovdd-supply:
+    description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
+
+  refin1p-supply:
+    description: REFIN+ supply that can be used as reference for conversion.
+
+  refin1n-supply:
+    description: REFIN- supply that can be used as reference for conversion.
+
+  refin2p-supply:
+    description: REFIN2+ supply that can be used as reference for conversion.

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +164 -0

+      Optional external clock source. Can include one clock source: external
+      clock or external crystal.
+
+  clock-names:
+    enum:
+      - ext-clk
+      - xtal
+
+  '#clock-cells':
+    const: 0
+
+  adi,gpio0-power-down-switch:
+    type: boolean
+    description:
+      Describes whether GPIO0 is used as a switch to disconnect bridge circuits
+      from AVSS. Pin defaults to GPIO if this property is not present.
+
+  adi,gpio1-power-down-switch:
+    type: boolean
+    description:
+      Describes whether GPIO1 is used as a switch to disconnect bridge circuits
+      from AVSS. Pin defaults to GPIO if this property is not present.
+
+  adi,vbias-pins:
+    description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 1
+    maxItems: 9
+    items:
+      minimum: 0
+      maximum: 8
+
+  adi,dig-aux1:
+    description:
+      Describes whether DIG_AUX1 pin will operate as data ready output,
+      synchronization output signal (SYNC_OUT), or if it will be disabled.
+      A value of 0 indicates DIG_AUX1 pin disabled. High impedance.
+      A value of 1 indicates DIG_AUX1 is configured as ADC data ready output.
+      A value of 1 indicates DIG_AUX1 is configured as SYNC_OUT output.
+      If this property is absent, DIG_AUX1 pin is disabled.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2]
+    default: 0
+
+  adi,dig-aux2:
+    description:
+      Describes whether DIG_AUX2 pin will function as DAC LDAC input,
+      synchronization start input (START), or if it will be disabled.
+      A value of 0 indicates DIG_AUX2 pin is disabled. High impedance.
+      A value of 1 indicates DIG_AUX2 pin is configured as active-low LDAC input
+      for the DAC.
+      A value of 2 indicates DIG_AUX2 pin is configured as START input.
+      If this property is absent, DIG_AUX2 pin is disabled.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2]
+    default: 0
+
+  adi,sync-option:
+    description:
+      Describes how ADC conversions are going to be synchronized. A value of 1
+      indicates the SYNC_IN pin will function as a synchronization input that
+      allows the user to control the start of sampling by pulling SYNC_IN high.
+      Use option number 2 to set the alternate synchronization functionality
+      which allows per channel conversion start control when multiple channels
+      are enabled. Option number 0 disables synchronization.
+      A value of 0 indicates no synchronization. SYNC_IN pin disabled.
+      A value of 1 indicates standard synchronization functionality.
+      A value of 2 indicates alternate synchronization functionality.
+      If this property is absent, no synchronization is performed.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2]
+    default: 1
+
+  adi,excitation-pin-0:
+    description: |
+      Specifies the pin to apply excitation current 0 (IOUT0). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT0 to GPIO0.
+      18: Output excitation current IOUT0 to GPIO1.
+      19: Output excitation current IOUT0 to GPIO2.
+      20: Output excitation current IOUT0 to GPIO3.
+      If this property is absent, IOUT0 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-pin-1:
+    description: |
+      Specifies the pin to apply excitation current 1 (IOUT1). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT1 to GPIO0.
+      18: Output excitation current IOUT1 to GPIO1.
+      19: Output excitation current IOUT1 to GPIO2.
+      20: Output excitation current IOUT1 to GPIO3.
+      If this property is absent, IOUT1 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-pin-2:
+    description: |
+      Specifies the pin to apply excitation current 2 (IOUT2). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT2 to GPIO0.
+      18: Output excitation current IOUT2 to GPIO1.
+      19: Output excitation current IOUT2 to GPIO2.
+      20: Output excitation current IOUT2 to GPIO3.
+      If this property is absent, IOUT2 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-pin-3:
+    description: |
+      Specifies the pin to apply excitation current 3 (IOUT3). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT3 to GPIO0.
+      18: Output excitation current IOUT3 to GPIO1.
+      19: Output excitation current IOUT3 to GPIO2.
+      20: Output excitation current IOUT3 to GPIO3.
+      If this property is absent, IOUT3 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-current-0-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT0 output pin
+      specified in adi,excitation-pin-0.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-1-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT1 output pin
+      specified in adi,excitation-pin-1.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-2-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT2 output pin
+      specified in adi,excitation-pin-2.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-3-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT3 output pin
+      specified in adi,excitation-pin-3.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,chop-iexc:
+    description: |
+      Specifies the chopping/swapping functionality for excitation currents.
+      0: No Chopping of Excitation Currents.
+      1: Chop/swap IOUT0 and IOUT1 (pair AB) excitation currents.
+      2: Chop/swap IOUT2 and IOUT3 (pair CD) excitation currents.
+      3: Chop/swap both pairs (pair AB and pair CD) of excitation currents.
+      If this property is absent, no chopping is performed.
+      There are macros for the above values in dt-bindings/iio/adi,ad4170.h.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2, 3]

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +234 -0

+        items:
+          minimum: 0
+          maximum: 15
+
+      diff-channels:
+        description: |
+          This property is used for defining the inputs of a differential
+          voltage channel. The first value is the positive input and the second
+          value is the negative input of the channel.
+
+          Besides the analog input pins AIN0 to AIN8, there are special inputs
+          that can be selected with the following values:
+            17: Temperature sensor input
+            18: (AVDD-AVSS)/5
+            19: (IOVDD-DGND)/5
+            20: DAC output
+            21: ALDO
+            22: DLDO
+            23: AVSS
+            24: DGND
+            25: REFIN+
+            26: REFIN-
+            27: REFIN2+
+            28: REFIN2-
+            29: REFOUT
+
+          There are macros for those values in dt-bindings/iio/adi,ad4170.h.
+
+        items:
+          minimum: 0
+          maximum: 31
+
+      single-channel: true
+
+      common-mode-channel: true
+
+      bipolar: true
+
+      adi,config-setup-number:
+        description: |
+          Specifies which of the 8 setups are used to configure the channel.
+          A setup comprises of: AFE, FILTER, FILTER_FS, MISC, OFFSET, and GAIN
+          registers. More than one channel can use the same configuration setup
+          number in which case they will share the settings of the above
+          mentioned registers.
+        items:
+          minimum: 0
+          maximum: 7
+
+      adi,chop-adc:
+        description: |
+          Specifies the chopping/swapping functionality for a channel setup.
+          Macros for adi,chop-adc values are available in
+          dt-bindings/iio/adi,ad4170.h. When enabled, the analog inputs are
+          continuously swapped and a conversion is generated for each time a
+          swap occurs. The analog input pins are connected in one direction,
+          sampled, swapped, sampled again, and then the conversion results are
+          averaged. The input swap minimizes system offset and offset drift.
+          This property also specifies whether AC excitation using 2 or 4 GPIOs
+          are going to be used.
+          0: No channel chop.
+          1: Chop/swap the channel inputs.
+          2: AC Excitation using 4 GPIOs.
+          3: AC Excitation using 2 GPIOs.
+          If this property is absent, no chopping is performed.
+        $ref: /schemas/types.yaml#/definitions/uint16
+        enum: [0, 1, 2, 3]
+        default: 0
+
+      adi,burnout-current-nanoamp:
+        description: |
+          Current in nanoamps to be applied for this channel. Burnout currents
+          are only active when the channel is selected for conversion.
+        enum: [0, 100, 2000, 10000]
+        default: 0
+
+      adi,buffered-negative:
+        description: Enable precharge buffer, full buffer, or skip reference
+          buffering of the negative voltage reference. Because the output
+          impedance of the source driving the voltage reference inputs may be
+          dynamic, RC combinations of those inputs can cause DC gain errors if
+          the reference inputs go unbuffered into the ADC. Enable reference
+          buffering if the provided reference source has dynamic high impedance
+          output.
+        enum: [0, 1, 2]
+        default: 0
+
+      adi,buffered-positive:
+        description: Enable precharge buffer, full buffer, or skip reference
+          buffering of the positive voltage reference. Because the output
+          impedance of the source driving the voltage reference inputs may be
+          dynamic, RC combinations of those inputs can cause DC gain errors if
+          the reference inputs go unbuffered into the ADC. Enable reference
+          buffering if the provided reference source has dynamic high impedance
+          output.
+        enum: [0, 1, 2]
+        default: 0
+
+      adi,reference-select:
+        description: |
+          Select the reference source to use when converting on the specific
+          channel. Valid values are:
+          0: Differential reference voltage REFIN+ - REFIN−.
+          1: Differential reference voltage REFIN2+ - REFIN2−.
+          2: Internal 2.5V referece (REFOUT) relative to AVSS.
+          3: Analog supply voltage (AVDD) relative relative AVSS.
+          If this field is left empty, the internal reference is selected.
+        $ref: /schemas/types.yaml#/definitions/uint8
+        enum: [0, 1, 2, 3]
+        default: 2
+
+    required:
+      - reg
+      - adi,config-setup-number
+
+    allOf:
+      - oneOf:
+          - required: [single-channel]
+            properties:
+              diff-channels: false
+          - required: [diff-channels]
+            properties:
+              single-channel: false
+              common-mode-channel: false
+
+required:
+  - compatible
+  - reg
+  - avdd-supply
+  - iovdd-supply
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/iio/adc/adi,ad4170.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        adc@0 {
+            compatible = "adi,ad4170";
+            reg = <0>;
+            avdd-supply = <&avdd>;
+            iovdd-supply = <&iovdd>;
+            spi-max-frequency = <20000000>;
+            interrupt-parent = <&gpio_in>;
+            interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+            adi,dig-aux1 = /bits/ 8 <1>;
+            adi,dig-aux2 = /bits/ 8 <0>;
+            adi,sync-option = /bits/ 8 <0>;
+            adi,excitation-pin-0 = <19>;
+            adi,excitation-current-0-microamp = <10>;
+            adi,excitation-pin-1 = <20>;
+            adi,excitation-current-1-microamp = <10>;
+            adi,chop-iexc = /bits/ 8 <1>;
+            adi,vbias-pins = <5 6>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range
+            // Fully differential. If AVSS < 0V, Fully differential true bipolar
+            channel@0 {
+                reg = <0>;
+                bipolar;
+                diff-channels = <AD4170_MAP_AIN0 AD4170_MAP_AIN1>;
+                adi,config-setup-number = <0>;
+                adi,reference-select = /bits/ 8 <3>;
+                adi,burnout-current-nanoamp = <100>;
+            };
+            // Sample AIN2 with respect to DGND throughout AVDD/DGND input range
+            // Peseudo-differential unipolar (fig. 2a)
+            channel@1 {
+                reg = <1>;
+                single-channel = <AD4170_MAP_AIN2>;
+                common-mode-channel = <AD4170_MAP_DGND>;
+                adi,config-setup-number = <1>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range
+            // Pseudo-differential bipolar (fig. 2b)
+            channel@2 {
+                reg = <2>;
+                bipolar;
+                single-channel = <AD4170_MAP_AIN3>;
+                common-mode-channel = <AD4170_MAP_REFOUT>;
+                adi,config-setup-number = <2>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range
+            // Pseudo-differential true bipolar if AVSS < 0V (fig. 2c)
+            channel@3 {
+                reg = <3>;
+                bipolar;
+                single-channel = <AD4170_MAP_AIN4>;
+                common-mode-channel = <AD4170_MAP_DGND>;
+                adi,config-setup-number = <3>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN5 with respect to 2.5V throughout AVDD/REFOUT input range
+            // Pseudo-differential unipolar (AD4170 datasheet page 46 example)
+            channel@4 {
+                reg = <4>;
+                single-channel = <AD4170_MAP_AIN5>;
+                common-mode-channel = <AD4170_MAP_REFOUT>;
+                adi,config-setup-number = <4>;
+                adi,reference-select = /bits/ 8 <2>;
+            };
+            // Sample AIN6 with respect to REFIN+ throughout AVDD/AVSS input range
+            // Pseudo-differential unipolar
+            channel@5 {
+                reg = <5>;
+                single-channel = <AD4170_MAP_AIN6>;
+                common-mode-channel = <AD4170_MAP_REFIN1_P>;
+                adi,config-setup-number = <4>;
+                adi,reference-select = /bits/ 8 <2>;
+            };
+            // Sample AIN7 with respect to DGND throughout REFIN+/REFIN- input range
+            // Pseudo-differential bipolar
+            channel@6 {
+                reg = <6>;
+                bipolar;
+                diff-channels = <AD4170_MAP_AIN7 AD4170_MAP_DGND>;
+                adi,config-setup-number = <5>;
+                adi,reference-select = /bits/ 8 <0>;
+            };
+        };
+    };
+...
+

Signature · 1 line

2.45.2

Quoted 2 lines · Marcelo Schmitt

Add device tree documentation for AD4170 sigma-delta ADCs.

The usual question with long lists of properties. Any of these should be run-time controlled (by userspace) instead? If they might vary by the user for given h/w design, then should be user controlled instead.

Add device tree documentation for AD4170 sigma-delta ADCs.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4170.yaml          | 473 ++++++++++++++++++
 1 file changed, 473 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +60 -0

new file mode 100644
index 000000000000..8c5defc614ee
@@ -0,0 +1,473 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad4170.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD4170 Analog to Digital Converter
+
+maintainers:
+  - Marcelo Schmitt <[email protected]>
+
+description: |
+  Analog Devices AD4170 Analog to Digital Converter.
+  Specifications can be found at:
+    https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf
+
+$ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    enum:
+      - adi,ad4170
+
+  avss-supply:
+    description:
+      Referece voltage supply for AVDD. AVSS can be set below 0V to provide a
+      bipolar power supply to AD4170-4. Must be −2.625V at minimum, 0V maximum.
+      If not specified, this is assumed to be analog ground.
+
+  avdd-supply:
+    description:
+      A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD).
+
+  iovdd-supply:
+    description: 1.7V to 5.25V reference supply to the serial interface (IOVDD).
+
+  refin1p-supply:
+    description: REFIN+ supply that can be used as reference for conversion.
+
+  refin1n-supply:
+    description: REFIN- supply that can be used as reference for conversion.
+
+  refin2p-supply:
+    description: REFIN2+ supply that can be used as reference for conversion.
+
+  refin2n-supply:
+    description: REFIN2- supply that can be used as reference for conversion.
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: |
+      Optional external clock source. Can include one clock source: external
+      clock or external crystal.
+
+  clock-names:
+    enum:
+      - ext-clk

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +9 -0

+    description:
+      Describes whether DIG_AUX1 pin will operate as data ready output,
+      synchronization output signal (SYNC_OUT), or if it will be disabled.
+      A value of 0 indicates DIG_AUX1 pin disabled. High impedance.
+      A value of 1 indicates DIG_AUX1 is configured as ADC data ready output.
+      A value of 1 indicates DIG_AUX1 is configured as SYNC_OUT output.
+      If this property is absent, DIG_AUX1 pin is disabled.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2]

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +6 -0

+      If this property is absent, DIG_AUX2 pin is disabled.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2]
+    default: 0
+
+  adi,sync-option:

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +8 -0

+      17: Output excitation current IOUT0 to GPIO0.
+      18: Output excitation current IOUT0 to GPIO1.
+      19: Output excitation current IOUT0 to GPIO2.
+      20: Output excitation current IOUT0 to GPIO3.
+      If this property is absent, IOUT0 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +24 -0

+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-pin-2:
+    description: |
+      Specifies the pin to apply excitation current 2 (IOUT2). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT2 to GPIO0.
+      18: Output excitation current IOUT2 to GPIO1.
+      19: Output excitation current IOUT2 to GPIO2.
+      20: Output excitation current IOUT2 to GPIO3.
+      If this property is absent, IOUT2 is not routed to any pin.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20]
+    default: 0
+
+  adi,excitation-pin-3:
+    description: |
+      Specifies the pin to apply excitation current 3 (IOUT3). Besides the
+      analog pins 0 to 8, the excitation current can be applied to GPIO pins.
+      17: Output excitation current IOUT3 to GPIO0.
+      18: Output excitation current IOUT3 to GPIO1.
+      19: Output excitation current IOUT3 to GPIO2.

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +59 -0

+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-1-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT1 output pin
+      specified in adi,excitation-pin-1.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-2-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT2 output pin
+      specified in adi,excitation-pin-2.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,excitation-current-3-microamp:
+    description: |
+      Excitation current in microamps to be applied to IOUT3 output pin
+      specified in adi,excitation-pin-3.
+    enum: [0, 10, 50, 100, 250, 500, 1000, 1500]
+    default: 0
+
+  adi,chop-iexc:
+    description: |
+      Specifies the chopping/swapping functionality for excitation currents.
+      0: No Chopping of Excitation Currents.
+      1: Chop/swap IOUT0 and IOUT1 (pair AB) excitation currents.
+      2: Chop/swap IOUT2 and IOUT3 (pair CD) excitation currents.
+      3: Chop/swap both pairs (pair AB and pair CD) of excitation currents.
+      If this property is absent, no chopping is performed.
+      There are macros for the above values in dt-bindings/iio/adi,ad4170.h.
+    $ref: /schemas/types.yaml#/definitions/uint8
+    enum: [0, 1, 2, 3]
+    default: 0
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+patternProperties:
+  "^channel@([0-9]|1[0-5])$":
+    $ref: adc.yaml
+    type: object
+    unevaluatedProperties: false
+    description: |
+      Represents the external channels which are connected to the ADC.
+
+    properties:
+      reg:
+        description: |
+          The channel number. The device can have up to 16 channels numbered
+          from 0 to 15.
+        items:
+          minimum: 0
+          maximum: 15

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +4 -0

+
+      single-channel: true
+
+      common-mode-channel: true

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +18 -0

+        items:
+          minimum: 0
+          maximum: 7
+
+      adi,chop-adc:
+        description: |
+          Specifies the chopping/swapping functionality for a channel setup.
+          Macros for adi,chop-adc values are available in
+          dt-bindings/iio/adi,ad4170.h. When enabled, the analog inputs are
+          continuously swapped and a conversion is generated for each time a
+          swap occurs. The analog input pins are connected in one direction,
+          sampled, swapped, sampled again, and then the conversion results are
+          averaged. The input swap minimizes system offset and offset drift.
+          This property also specifies whether AC excitation using 2 or 4 GPIOs
+          are going to be used.
+          0: No channel chop.
+          1: Chop/swap the channel inputs.
+          2: AC Excitation using 4 GPIOs.

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +9 -0

+        description: Enable precharge buffer, full buffer, or skip reference
+          buffering of the positive voltage reference. Because the output
+          impedance of the source driving the voltage reference inputs may be
+          dynamic, RC combinations of those inputs can cause DC gain errors if
+          the reference inputs go unbuffered into the ADC. Enable reference
+          buffering if the provided reference source has dynamic high impedance
+          output.
+        enum: [0, 1, 2]
+        default: 0

Documentation/devicetree/bindings/iio/adc/adi,ad4170.yaml new file +127 -0

+        $ref: /schemas/types.yaml#/definitions/uint8
+        enum: [0, 1, 2, 3]
+        default: 2
+
+    required:
+      - reg
+      - adi,config-setup-number
+
+    allOf:
+      - oneOf:
+          - required: [single-channel]
+            properties:
+              diff-channels: false
+          - required: [diff-channels]
+            properties:
+              single-channel: false
+              common-mode-channel: false
+
+required:
+  - compatible
+  - reg
+  - avdd-supply
+  - iovdd-supply
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/iio/adc/adi,ad4170.h>
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        adc@0 {
+            compatible = "adi,ad4170";
+            reg = <0>;
+            avdd-supply = <&avdd>;
+            iovdd-supply = <&iovdd>;
+            spi-max-frequency = <20000000>;
+            interrupt-parent = <&gpio_in>;
+            interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+            adi,dig-aux1 = /bits/ 8 <1>;
+            adi,dig-aux2 = /bits/ 8 <0>;
+            adi,sync-option = /bits/ 8 <0>;
+            adi,excitation-pin-0 = <19>;
+            adi,excitation-current-0-microamp = <10>;
+            adi,excitation-pin-1 = <20>;
+            adi,excitation-current-1-microamp = <10>;
+            adi,chop-iexc = /bits/ 8 <1>;
+            adi,vbias-pins = <5 6>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range
+            // Fully differential. If AVSS < 0V, Fully differential true bipolar
+            channel@0 {
+                reg = <0>;
+                bipolar;
+                diff-channels = <AD4170_MAP_AIN0 AD4170_MAP_AIN1>;
+                adi,config-setup-number = <0>;
+                adi,reference-select = /bits/ 8 <3>;
+                adi,burnout-current-nanoamp = <100>;
+            };
+            // Sample AIN2 with respect to DGND throughout AVDD/DGND input range
+            // Peseudo-differential unipolar (fig. 2a)
+            channel@1 {
+                reg = <1>;
+                single-channel = <AD4170_MAP_AIN2>;
+                common-mode-channel = <AD4170_MAP_DGND>;
+                adi,config-setup-number = <1>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range
+            // Pseudo-differential bipolar (fig. 2b)
+            channel@2 {
+                reg = <2>;
+                bipolar;
+                single-channel = <AD4170_MAP_AIN3>;
+                common-mode-channel = <AD4170_MAP_REFOUT>;
+                adi,config-setup-number = <2>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range
+            // Pseudo-differential true bipolar if AVSS < 0V (fig. 2c)
+            channel@3 {
+                reg = <3>;
+                bipolar;
+                single-channel = <AD4170_MAP_AIN4>;
+                common-mode-channel = <AD4170_MAP_DGND>;
+                adi,config-setup-number = <3>;
+                adi,reference-select = /bits/ 8 <3>;
+            };
+            // Sample AIN5 with respect to 2.5V throughout AVDD/REFOUT input range
+            // Pseudo-differential unipolar (AD4170 datasheet page 46 example)
+            channel@4 {
+                reg = <4>;
+                single-channel = <AD4170_MAP_AIN5>;
+                common-mode-channel = <AD4170_MAP_REFOUT>;
+                adi,config-setup-number = <4>;
+                adi,reference-select = /bits/ 8 <2>;
+            };
+            // Sample AIN6 with respect to REFIN+ throughout AVDD/AVSS input range
+            // Pseudo-differential unipolar
+            channel@5 {
+                reg = <5>;
+                single-channel = <AD4170_MAP_AIN6>;
+                common-mode-channel = <AD4170_MAP_REFIN1_P>;
+                adi,config-setup-number = <4>;
+                adi,reference-select = /bits/ 8 <2>;
+            };
+            // Sample AIN7 with respect to DGND throughout REFIN+/REFIN- input range
+            // Pseudo-differential bipolar
+            channel@6 {
+                reg = <6>;
+                bipolar;
+                diff-channels = <AD4170_MAP_AIN7 AD4170_MAP_DGND>;
+                adi,config-setup-number = <5>;
+                adi,reference-select = /bits/ 8 <0>;
+            };
+        };
+    };
+...
+

drivers/iio/adc/ad4170.c line 39

Quoted 12 lines · Marcelo Schmitt

drivers/iio/adc/ad4170.c new file +12 -0

+#include <asm/div64.h>
+#include <linux/unaligned.h>
+
+#include <linux/iio/buffer.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/kfifo_buf.h>
+#include <linux/iio/sysfs.h>
+#include <linux/iio/trigger.h>
+#include <linux/iio/triggered_buffer.h>
+#include <linux/iio/trigger_consumer.h>
+#include "ad4170.h"
+  

No bindings header included? No usage of binding defines (I did look for them in case you have some incorrect include via other header)? So not a binding...

drivers/iio/adc/ad4170.h new file +0 -0

new file mode 100644
index 000000000000..5b24788314b1

Best regards,
Krzysztof

From: Ana-Maria Cusco <[email protected]>

From: Ana-Maria Cusco <[email protected]>

Add support for the AD4170 ADC with the following features:
- Single-shot read (read_raw), scale, sampling freq
- Multi channel buffer support
- Buffered capture in triggered mode
- Gain and offset calibration
- chop_iexc and chop_adc device configuration
- Powerdown switch configuration

Co-developed-by Dragos Bogdan <[email protected]>

Signed-off-by Dragos Bogdan <[email protected]>

Signed-off-by Ana-Maria Cusco <[email protected]>

Co-developed-by Marcelo Schmitt <[email protected]>

Signed-off-by Marcelo Schmitt <[email protected]>

---
 drivers/iio/adc/Kconfig  |   16 +
 drivers/iio/adc/Makefile |    1 +
 drivers/iio/adc/ad4170.c | 2049 ++++++++++++++++++++++++++++++++++++++
 drivers/iio/adc/ad4170.h |  316 ++++++

drivers/iio/adc/ad4170.c new file +0 -0

new file mode 100644
index 000000000000..20b74575f2cb
@@ -0,0 +1,2049 @@

drivers/iio/adc/ad4170.c new file +5 -0

+	"adi,excitation-current-0-microamp",
+	"adi,excitation-current-1-microamp",
+	"adi,excitation-current-2-microamp",
+	"adi,excitation-current-3-microamp",
+};

drivers/iio/adc/ad4170.c new file +36 -0

+static const unsigned int ad4170_filt_fs_tbl[] = {
+	1, /* SINC5 minimum filter_fs */
+	2,
+	4, /* SINC5+AVG and SINC3 minimum filter_fs */
+	8,
+	12,
+	16,
+	20,
+	40,
+	48,
+	80,
+	100,
+	256, /* SINC5 maximum filter_fs */
+	500,
+	1000,
+	5000,
+	8332,
+	10000,
+	25000,
+	50000,
+	65532 /* SINC5+AVG and SINC3 maximum filter_fs */
+};
 
+struct ad4170_state {
+	struct regmap *regmap;
+	struct spi_device *spi;
+	struct regulator_bulk_data supplies[7];
+	struct mutex lock; /* Protect filter, PGA, GPIO, chan read, chan config */
+	struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
+	struct ad4170_chan_info chans_info[AD4170_MAX_CHANNELS];
+	struct ad4170_setup setups[AD4170_MAX_SETUPS];
+	u32 mclk_hz;
+	enum ad4170_pin_function pins_fn[AD4170_NUM_ANALOG_PINS];
+	enum ad4170_gpio_function gpio_fn[AD4170_NUM_GPIO_PINS];
+	unsigned int clock_ctrl;
+	struct clk *ext_clk;
+	struct clk_hw int_clk_hw;

drivers/iio/adc/ad4170.c new file +28 -0

+	 */
+	u8 reg_write_tx_buf[6];
+	__be32 reg_read_rx_buf __aligned(IIO_DMA_MINALIGN);
+	__be16 reg_read_tx_buf;
+};
+
 
+static const struct regmap_config ad4170_regmap_config = {
+	.reg_bits = 14,
+	.val_bits = 32,
+	.reg_format_endian = REGMAP_ENDIAN_BIG,
+	.val_format_endian = REGMAP_ENDIAN_BIG,
+	.reg_read = ad4170_reg_read,
+	.reg_write = ad4170_reg_write,
+};
+
+static int ad4170_set_mode(struct ad4170_state *st, unsigned int mode)
+{
+	return regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+				  AD4170_REG_CTRL_MODE_MSK,
+				  FIELD_PREP(AD4170_REG_CTRL_MODE_MSK, mode));
+}
+
+/* 8 possible setups (0-7)*/
+static int ad4170_write_setup(struct ad4170_state *st, unsigned int setup_num,
+			      struct ad4170_setup *setup)
+{
+	int ret;
+

drivers/iio/adc/ad4170.c new file +16 -0

+		return ret;
+
+	ret = regmap_write(st->regmap, AD4170_AFE_REG(setup_num), setup->afe);
+	if (ret < 0)
+		return ret;
+
+	ret = regmap_write(st->regmap, AD4170_FILTER_REG(setup_num),
+			   setup->filter);
+	if (ret < 0)
+		return ret;
+
+	ret = regmap_write(st->regmap, AD4170_FILTER_FS_REG(setup_num),
+			   setup->filter_fs);
+	if (ret < 0)
+		return ret;
+

drivers/iio/adc/ad4170.c new file +24 -0

+}
 
+static int ad4170_set_filter_type(struct iio_dev *indio_dev,
+				  const struct iio_chan_spec *chan,
+				  unsigned int val)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	struct ad4170_chan_info *chan_info = &st->chans_info[chan->address];
+	struct ad4170_setup *setup = &st->setups[chan_info->setup_num];
+	unsigned int old_filter_fs, old_filter, filter_type_conf;
+	int ret = 0;
+
+	switch (val) {
+	case AD4170_SINC5_AVG:
+		filter_type_conf = AD4170_SINC5_AVG_CONF;
+		break;
+	case AD4170_SINC5:
+		filter_type_conf = AD4170_SINC5_CONF;
+		break;
+	case AD4170_SINC3:
+		filter_type_conf = AD4170_SINC3_CONF;
+		break;
+	default:
+		return -EINVAL;
+	}

drivers/iio/adc/ad4170.c new file +43 -0

+		old_filter = setup->filter;
+		old_filter_fs = setup->filter_fs;
+		if (val == AD4170_SINC5_AVG || val == AD4170_SINC3) {
+			if (setup->filter_fs < AD4170_SINC3_MIN_FS)
+				setup->filter_fs = AD4170_SINC3_MIN_FS;
+			if (setup->filter_fs > AD4170_SINC3_MAX_FS)
+				setup->filter_fs = AD4170_SINC3_MAX_FS;
+
+		} else if (val == AD4170_SINC5) {
+			if (setup->filter_fs < AD4170_SINC5_MIN_FS)
+				setup->filter_fs = AD4170_SINC5_MIN_FS;
+			if (setup->filter_fs > AD4170_SINC5_MAX_FS)
+				setup->filter_fs = AD4170_SINC5_MAX_FS;
+		}
+
+		setup->filter &= ~AD4170_SETUPS_FILTER_TYPE_MSK;
+		setup->filter |= FIELD_PREP(AD4170_SETUPS_FILTER_TYPE_MSK,
+					    filter_type_conf);
+
+		guard(mutex)(&st->lock);
+		ret = ad4170_write_setup(st, chan_info->setup_num, setup);
+		if (ret) {
+			setup->filter = old_filter;
+			setup->filter_fs = old_filter_fs;
+		}
+		return ret;
+	}
+	unreachable();
+}
 
+
+static int ad4170_read_sample(struct iio_dev *indio_dev, unsigned int channel,
+			      int *val)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	struct ad4170_chan_info *chan_info = &st->chans_info[channel];
+	struct ad4170_setup *setup = &st->setups[chan_info->setup_num];
+	int precision_bits = ad4170_channel_template.scan_type.realbits;
+	int ret;
+
+	guard(mutex)(&st->lock);
+	ret = ad4170_set_channel_enable(st, channel, true);
+	if (ret)
+		return ret;

drivers/iio/adc/ad4170.c new file +14 -0

+
+	ret = regmap_read(st->regmap, AD4170_DATA_24b_REG, val);
+	if (ret)
+		return ret;
+
+	if (FIELD_GET(AD4170_AFE_BIPOLAR_MSK, setup->afe))
+		*val = sign_extend32(*val, precision_bits - 1);
+out:
+	ret = ad4170_set_channel_enable(st, channel, false);
+	if (ret)
+		return ret;
+
+	return IIO_VAL_INT;
+}

drivers/iio/adc/ad4170.c new file +21 -0

+/*
+ * Receives the device state, the channel spec, a reference selection, and
+ * returns the magnitude of the allowed input range in µV.
+ * Verifies whether the channel configuration is valid by checking the provided
+ * input type, polarity, and voltage references result in a sane input range.
+ * Returns negative error code on failure.
+ */
+static int ad4170_get_input_range(struct ad4170_state *st,
+				  struct iio_chan_spec const *chan,
+				  unsigned int ref_sel)
+{
+	struct ad4170_chan_info *chan_info = &st->chans_info[chan->address];
+	struct ad4170_setup *setup = &st->setups[chan_info->setup_num];
+	bool bipolar = FIELD_GET(AD4170_AFE_BIPOLAR_MSK, setup->afe);
+	int refp, refn, ain_voltage, ret;
+
+	switch (ref_sel) {
+	case AD4170_AFE_REFIN_REFIN1:
+		refp = regulator_get_voltage(st->supplies[AD4170_REFIN1P_SUP].consumer);
+		refn = regulator_get_voltage(st->supplies[AD4170_REFIN1N_SUP].consumer);
+		break;

drivers/iio/adc/ad4170.c new file +21 -0

+		 */
+		if (ret < 0)
+			ret = 0; /* Assume AVSS at GND if not provided */
+
+		refn = ret;
+		break;
+	case AD4170_AFE_REFIN_REFOUT:
+		refn = regulator_get_voltage(st->supplies[AD4170_AVSS_SUP].consumer);
+		if (refn < 0)
+			refn = 0;
+
+		/* REFOUT is 2.5 V relative to AVSS */
+		/* avss-supply is never above 0V. */
+		refp = AD4170_INT_REF_2_5V - refn;
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (refp < 0)
+		return refp;
+

drivers/iio/adc/ad4170.c new file +44 -0

+		return refp + refn;
+	}
+	/*
+	 * Some configurations can lead to invalid setups.
+	 * For example, if AVSS = -2.5V, REF_SELECT set to REFOUT (REFOUT/AVSS),
+	 * and single-ended channel configuration set, then the input range
+	 * should go from 0V to +VREF (single-ended - datasheet pg 10), but
+	 * REFOUT/AVSS range would be -2.5V to 0V.
+	 * Check the positive reference is higher than 0V for pseudo-diff
+	 * channels.
+	 */
+	if (bipolar) {
+		/* Pseudo-differential bipolar channel */
+		/* Input allowed to swing from GND to +VREF */
+		if (refp <= 0)
+			return dev_err_probe(&st->spi->dev, -EINVAL,
+					     "Invalid setup for channel %lu.\n",
+					     chan->address);
+
+		return refp;
+	}
+
+	/* Pseudo-differential unipolar channel */
+	/* Input allowed to swing from IN- to +VREF */
+	if (refp <= 0)
+		return dev_err_probe(&st->spi->dev, -EINVAL,
+				     "Invalid setup for channel %lu.\n",
+				     chan->address);
+
+	ret = ad4170_get_AINM_voltage(st, chan->channel2, &ain_voltage);
+	if (ret < 0)
+		return ret;
+
+	if (refp - ain_voltage <= 0)
+		return dev_err_probe(&st->spi->dev, -EINVAL,
+				     "Invalid setup for channel %lu.\n",
+				     chan->address);
+
+	return refp - ain_voltage;
+}
+
+static int ad4170_read_raw(struct iio_dev *indio_dev,
+			   struct iio_chan_spec const *chan,
+			   int *val, int *val2, long info)

drivers/iio/adc/ad4170.c new file +28 -0

+			return ad4170_read_sample(indio_dev, chan->address, val);
+		unreachable();
+	case IIO_CHAN_INFO_SCALE:
+		pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+		*val = chan_info->scale_tbl[pga][0];
+		*val2 = chan_info->scale_tbl[pga][1];
+		return IIO_VAL_INT_PLUS_NANO;
+	case IIO_CHAN_INFO_OFFSET:
+		pga = FIELD_GET(AD4170_AFE_PGA_GAIN_MSK, setup->afe);
+		*val = chan_info->offset_tbl[pga];
+		return IIO_VAL_INT;
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		f_type = ad4170_filter_to_filter_type(setup->filter);
+		fs_idx = find_closest(setup->filter_fs, ad4170_filt_fs_tbl,
+				      ARRAY_SIZE(ad4170_filt_fs_tbl));
+		*val = st->sps_tbl[f_type][fs_idx][0];
+		*val2 = st->sps_tbl[f_type][fs_idx][1];
+		return IIO_VAL_INT_PLUS_MICRO;
+	case IIO_CHAN_INFO_CALIBBIAS:
+		*val = setup->offset;
+		return IIO_VAL_INT;
+	case IIO_CHAN_INFO_CALIBSCALE:
+		*val = setup->gain;
+		return IIO_VAL_INT;
+	default:
+		return -EINVAL;
+	}
+}
 

drivers/iio/adc/ad4170.c new file +20 -0

+		switch (info) {
+		case IIO_CHAN_INFO_SCALE:
+			return ad4170_set_pga(indio_dev, st, chan->address, val,
+					      val2);
+		case IIO_CHAN_INFO_SAMP_FREQ:
+			return ad4170_set_channel_freq(st, chan->address, val,
+						       val2);
+		case IIO_CHAN_INFO_CALIBBIAS:
+			return ad4170_set_calib_offset(indio_dev, chan->address,
+						       val);
+		case IIO_CHAN_INFO_CALIBSCALE:
+			return ad4170_set_calib_gain(indio_dev, chan->address,
+						     val);
+		default:
+			return -EINVAL;
+		}
+	}
+	unreachable();
+}
+

drivers/iio/adc/ad4170.c new file +9 -0

+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	struct device *dev = &st->spi->dev;
+	int chan_num, i, ret;
+
+	chan_num = 0;
+	device_for_each_child_node_scoped(dev, child) {
+		ret = ad4170_parse_channel_node(indio_dev, child, chan_num);
+		if (ret)

drivers/iio/adc/ad4170.c new file +8 -0

+	 */
+	if (chan_num > 1 && i == AD4170_MAX_CHANNELS)
+		return dev_err_probe(dev, -EINVAL,
+				     "Channel 0 must be configured\n");
+
+	indio_dev->channels = st->chans;
+	indio_dev->num_channels = chan_num;
+	return 0;

drivers/iio/adc/ad4170.c new file +5 -0

+}
 
+static int ad4170_parse_pw_switch(struct ad4170_state *st, struct device *dev)
+{
+	bool pdsw0, pdsw1;
+

drivers/iio/adc/ad4170.c new file +21 -0

+					     "GPIO 0 already used with fn %u\n",
+					     st->gpio_fn[0]);
+
+		st->gpio_fn[0] = AD4170_GPIO_PW_DOW_SWITCH;
+	}
+	if (pdsw1) {
+		if (st->gpio_fn[1] != AD4170_GPIO_UNASIGNED)
+			return dev_err_probe(&st->spi->dev, -EINVAL,
+					     "GPIO 1 already used with fn %u\n",
+					     st->gpio_fn[1]);
+
+		st->gpio_fn[1] = AD4170_GPIO_PW_DOW_SWITCH;
+	}
+	return regmap_update_bits(st->regmap, AD4170_POWER_DOWN_SW_REG,
+				 AD4170_POWER_DOWN_SW_PDSW0_MSK |
+				 AD4170_POWER_DOWN_SW_PDSW1_MSK,
+				 pdsw0 | pdsw1);
+}
+
+static int ad4170_parse_vbias(struct ad4170_state *st, struct device *dev)
+{

drivers/iio/adc/ad4170.c new file +29 -0

+					     "AIN%d already used with fn %u\n",
+					     vbias_pins[i], st->pins_fn[i]);
+
+		val |= BIT(vbias_pins[i]);
+		st->pins_fn[vbias_pins[i]] = AD4170_PIN_VBIAS;
+	}
+	return regmap_write(st->regmap, AD4170_V_BIAS_REG, val);
+}
+
+static int ad4170_parse_firmware(struct iio_dev *indio_dev)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	struct device *dev = &st->spi->dev;
+	int ret, i;
+	u8 aux;
+
+	ret = ad4170_clock_select(indio_dev);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Failed to setup device clock\n");
+
+	ret = regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl);
+	if (ret < 0)
+		return ret;
+
+	ret = ad4170_parse_pin_muxing(indio_dev);
+	if (ret < 0)
+		return ret;
+
+	for (i = 0; i < AD4170_NUM_ANALOG_PINS; i++)

drivers/iio/adc/ad4170.c new file +33 -0

+
+	ret = ad4170_parse_pw_switch(st, dev);
+	if (ret < 0)
+		return dev_err_probe(dev, ret,
+				     "Failed to config power down switches\n");
+
+	ret = ad4170_parse_vbias(st, dev);
+	if (ret < 0)
+		return ret;
+
+	ret = ad4170_parse_channels(indio_dev);
+	if (ret)
+		return ret;
+
+	aux = AD4170_MISC_CHOP_IEXC_OFF;
+	ret = device_property_read_u8(dev, "adi,chop-iexc", &aux);
+	if (!ret) {
+		ret = ad4170_find_table_index(ad4170_iexc_chop_tbl, aux);
+		if (ret < 0)
+			return dev_err_probe(dev, ret,
+					     "Invalid adi,chop-iexc config: %u\n",
+					      aux);
+	}
+
+	/* Set excitation current chop config to first channel setup config */
+	st->setups[indio_dev->channels[0].address].misc |=
+		FIELD_PREP(AD4170_MISC_CHOP_IEXC_MSK, aux);
+	return 0;
+}
+
+static int ad4170_initial_config(struct iio_dev *indio_dev)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);

drivers/iio/adc/ad4170.c new file +37 -0

+
+		ret = regmap_update_bits(st->regmap,
+					 AD4170_CHAN_SETUP_REG(chan->address),
+					 AD4170_CHANNEL_SETUP_SETUP_MSK,
+					 FIELD_PREP(AD4170_CHANNEL_SETUP_SETUP_MSK,
+						    chan_info->setup_num));
+		if (ret)
+			return ret;
+
+		setup->gain = AD4170_GAIN_REG_DEFAULT;
+		ret = ad4170_write_setup(st, chan_info->setup_num, setup);
+		if (ret)
+			return ret;
+
+		val = FIELD_PREP(AD4170_CHANNEL_MAPN_AINP_MSK, chan->channel) |
+		      FIELD_PREP(AD4170_CHANNEL_MAPN_AINM_MSK, chan->channel2);
+
+		ret = regmap_write(st->regmap, AD4170_CHAN_MAP_REG(i), val);
+		if (ret < 0)
+			return ret;
+
+		ret = ad4170_set_channel_freq(st, chan->address,
+					      AD4170_MAX_SAMP_RATE, 0);
+		if (ret)
+			return ret;
+
+		ret = ad4170_fill_scale_tbl(indio_dev, i);
+		if (ret)
+			return ret;
+	}
+
+	ret = regmap_write(st->regmap, AD4170_CHANNEL_EN_REG, 0);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Configure channels to share the same data output register, i.e. data

drivers/iio/adc/ad4170.c new file +23 -0

+}
 
+static void ad4170_prepare_message(struct ad4170_state *st)
+{
+	/*
+	 * Continuous data register read is enabled on buffer postenable so
+	 * no instruction phase is needed meaning we don't need to send the
+	 * register address to read data. Transfer only needs the read buffer.
+	 */
+	st->xfer.rx_buf = &st->reg_read_rx_buf;
+	st->xfer.bits_per_word = ad4170_channel_template.scan_type.storagebits;
+	st->xfer.len = BITS_TO_BYTES(ad4170_channel_template.scan_type.storagebits);
+
+	spi_message_init_with_transfers(&st->msg, &st->xfer, 1);
+}
+
+static int ad4170_buffer_postenable(struct iio_dev *indio_dev)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	int ret;
+
+	ret = ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_CONT);
+	if (ret < 0)
+		return ret;

drivers/iio/adc/ad4170.c new file +19 -0

+		if (ret)
+			return ret;
+	}
+
+	ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG,
+				 AD4170_REG_CTRL_CONT_READ_MSK,
+				 FIELD_PREP(AD4170_REG_CTRL_CONT_READ_MSK,
+					    AD4170_ADC_CTRL_CONT_READ_DISABLE));
+	if (ret < 0)
+		return ret;
+
+	return ad4170_set_mode(st, AD4170_ADC_CTRL_MODE_IDLE);
+}
+
+static const struct iio_buffer_setup_ops ad4170_buffer_ops = {
+	.postenable = ad4170_buffer_postenable,
+	.predisable = ad4170_buffer_predisable,
+};
+

drivers/iio/adc/ad4170.c new file +10 -0

+
+	st->trig = devm_iio_trigger_alloc(indio_dev->dev.parent, "%s-trig%d",
+					  indio_dev->name,
+					  iio_device_id(indio_dev));
+	if (!st->trig)
+		return -ENOMEM;
+
+	st->trig->ops = &ad4170_trigger_ops;
+	st->trig->dev.parent = indio_dev->dev.parent;
+

drivers/iio/adc/ad4170.c new file +34 -0

+			  indio_dev->name, indio_dev);
+	if (ret)
+		return ret;
+
+	return devm_iio_triggered_buffer_setup(indio_dev->dev.parent, indio_dev,
+					       &iio_pollfunc_store_time,
+					       &ad4170_trigger_handler,
+					       &ad4170_buffer_ops);
+}
+
+static int ad4170_probe(struct spi_device *spi)
+{
+	struct device *dev = &spi->dev;
+	struct iio_dev *indio_dev;
+	struct ad4170_state *st;
+	int ret;
+
+	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
+	if (!indio_dev)
+		return -ENOMEM;
+
+	st = iio_priv(indio_dev);
+	devm_mutex_init(dev, &st->lock);
+
+	indio_dev->name = AD4170_NAME;
+	indio_dev->modes = INDIO_DIRECT_MODE;
+	indio_dev->info = &ad4170_info;
+
+	st->spi = spi;
+	st->regmap = devm_regmap_init(dev, NULL, st, &ad4170_regmap_config);
+
+	st->supplies[AD4170_AVDD_SUP].supply = "avdd";
+	st->supplies[AD4170_AVSS_SUP].supply = "avss";
+	st->supplies[AD4170_IOVDD_SUP].supply = "iovdd";

drivers/iio/adc/ad4170.c new file +13 -0

+	 */
+	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->supplies),
+				      st->supplies);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to get supplies\n");
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(st->supplies), st->supplies);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
+
+	ret = devm_add_action_or_reset(dev, ad4170_disable_supplies, st);
+	if (ret)
+		return dev_err_probe(dev, ret,

drivers/iio/adc/ad4170.c new file +18 -0

+
+	ret = ad4170_initial_config(indio_dev);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to setup device\n");
+
+	init_completion(&st->completion);
+
+	ret = ad4170_triggered_buffer_setup(indio_dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to setup read buffer\n");
+
+	ad4170_prepare_message(st);
+
+	return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct of_device_id ad4170_of_match[] = {

drivers/iio/adc/ad4170.h new file +9 -0

+#define AD4170_STATUS_REG			0x14
+#define AD4170_DATA_24b_REG			0x1c
+#define AD4170_PIN_MUXING_REG			0x68
+#define AD4170_CLOCK_CTRL_REG			0x6A
+#define AD4170_POWER_DOWN_SW_REG		0x6e
+#define AD4170_ADC_CTRL_REG			0x70
+#define AD4170_CHANNEL_EN_REG			0x78
+#define AD4170_CHAN_SETUP_REG(x)		(0x80 + 4 * (x))
+#define AD4170_CHAN_MAP_REG(x)			(0x82 + 4 * (x))

drivers/iio/adc/ad4170.h new file +70 -0

+
+/* AD4170_REG_POWER_DOWN_SW */
+#define AD4170_POWER_DOWN_SW_PDSW1_MSK				BIT(1)
+#define AD4170_POWER_DOWN_SW_PDSW0_MSK				BIT(0)
+
+/* AD4170_REG_ADC_CTRL */
+#define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK			BIT(7)
+#define AD4170_REG_CTRL_CONT_READ_MSK				GENMASK(5, 4)
+#define AD4170_REG_CTRL_MODE_MSK				GENMASK(3, 0)
+
+/* AD4170_REG_CHANNEL_EN */
+#define AD4170_CHANNEL_EN(ch)					BIT(ch)
+
+/* AD4170_REG_ADC_CHANNEL_SETUP */
+#define AD4170_CHANNEL_SETUP_SETUP_MSK				GENMASK(2, 0)
+
+/* AD4170_REG_ADC_CHANNEL_MAP */
+#define AD4170_CHANNEL_MAPN_AINP_MSK				GENMASK(12, 8)
+#define AD4170_CHANNEL_MAPN_AINM_MSK				GENMASK(4, 0)
+
+/* AD4170_REG_ADC_SETUPS_MISC */
+#define AD4170_MISC_CHOP_IEXC_MSK				GENMASK(15, 14)
+#define AD4170_MISC_CHOP_ADC_MSK				GENMASK(9, 8)
+#define AD4170_MISC_BURNOUT_MSK					GENMASK(1, 0)
+
+/* AD4170_REG_ADC_SETUPS_AFE */
+#define AD4170_AFE_REF_BUF_M_MSK				GENMASK(11, 10)
+#define AD4170_AFE_REF_BUF_P_MSK				GENMASK(9, 8)
+#define AD4170_AFE_REF_SELECT_MSK				GENMASK(6, 5)
+#define AD4170_AFE_BIPOLAR_MSK					BIT(4)
+#define AD4170_AFE_PGA_GAIN_MSK					GENMASK(3, 0)
+
+/* AD4170_REG_ADC_SETUPS_FILTER */
+#define AD4170_SETUPS_POST_FILTER_SEL_MSK			GENMASK(7, 4)
+#define AD4170_SETUPS_FILTER_TYPE_MSK				GENMASK(3, 0)
+
+/* AD4170 REG_OFFSET*/
+#define AD4170_OFFSET_MSK					GENMASK(23, 0)
+
+/* AD4170 REG_GAIN*/
+#define AD4170_GAIN_MSK						GENMASK(23, 0)
+#define AD4170_GAIN_REG_DEFAULT					0x555555
+
+/* AD4170_REG_CURRENT_SOURCE */
+#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK			GENMASK(12, 8)
+#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK			GENMASK(2, 0)
+
+/* AD4170_REG_FIR_CONTROL */
+#define AD4170_FIR_CONTROL_IIR_MODE_MSK				BIT(15)
+
+#define AD4170_MAX_CHANNELS				16
+#define AD4170_MAX_ANALOG_PINS				8
+#define AD4170_MAX_SETUPS				8
+#define AD4170_INVALID_SETUP_SLOT			9
+#define AD4170_NUM_CURRENT_SRC				4
+#define AD4170_MAX_SAMP_RATE				125000
+
+#define AD4170_NUM_ANALOG_PINS				9
+#define AD4170_NUM_GPIO_PINS				4
+
+#define AD4170_DIG_AUX1_DISABLED	0
+#define AD4170_DIG_AUX1_RDY		1
+#define AD4170_DIG_AUX1_SYNC		2
+
+#define AD4170_DIG_AUX2_DISABLED	0
+#define AD4170_DIG_AUX2_LDAC		1
+#define AD4170_DIG_AUX2_SYNC		2
+
+#define AD4170_SYNC_DISABLED		0
+#define AD4170_SYNC_STANDARD		1

drivers/iio/adc/ad4170.h new file +16 -0

+
+#define AD4170_BURNOUT_OFF		0
+#define AD4170_BURNOUT_100NA		100
+#define AD4170_BURNOUT_2000NA		2000
+#define AD4170_BURNOUT_10000NA		10000
+
+#define AD4170_PGA_OPTIONS		10
+
+enum ad4170_pin_function {
+	AD4170_PIN_UNASIGNED,
+	AD4170_PIN_ANALOG_IN,
+	AD4170_PIN_CURRENT_OUT,
+	AD4170_PIN_VBIAS
+};
+
+enum ad4170_gpio_function {

drivers/iio/adc/ad4170.h new file +32 -0

+	AD4170_REF_BUF_PRE,
+	/** Full Buffer.*/
+	AD4170_REF_BUF_FULL,
+	/** Bypass */
+	AD4170_REF_BUF_BYPASS
+};
+
+/**
+ * @enum ad4170_filter_type
+ * @brief Filter Mode for Sinc-Based Filters.
+ */
+enum ad4170_filter_type {
+	AD4170_SINC5_AVG,
+	AD4170_SINC5,
+	AD4170_SINC3,
+};
+
+/* ADC Register Lengths */
+static const unsigned int ad4170_reg_size[] = {
+	[AD4170_INTERFACE_CONFIG_A_REG] = 1,
+	[AD4170_STATUS_REG]	= 2,
+	[AD4170_DATA_24b_REG]	= 3,
+	[AD4170_PIN_MUXING_REG]	= 2,
+	[AD4170_CLOCK_CTRL_REG]	= 2,
+	[AD4170_POWER_DOWN_SW_REG]	= 2,
+	[AD4170_ADC_CTRL_REG]	= 2,
+	[AD4170_CHANNEL_EN_REG]	= 2,
+	/*
+	 * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and
+	 * their addresses are interleaved such that we have CHANNEL_SETUP0
+	 * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1,
+	 * and so on until CHANNEL_MAP15.

drivers/iio/adc/ad4170.h new file +50 -0

+	[AD4170_MISC_REG(0)] = 2,
+	[AD4170_MISC_REG(1)] = 2,
+	[AD4170_MISC_REG(2)] = 2,
+	[AD4170_MISC_REG(3)] = 2,
+	[AD4170_MISC_REG(4)] = 2,
+	[AD4170_MISC_REG(5)] = 2,
+	[AD4170_MISC_REG(6)] = 2,
+	[AD4170_MISC_REG(7)] = 2,
+	/* Init AFE register size */
+	[AD4170_AFE_REG(0)] = 2,
+	[AD4170_AFE_REG(1)] = 2,
+	[AD4170_AFE_REG(2)] = 2,
+	[AD4170_AFE_REG(3)] = 2,
+	[AD4170_AFE_REG(4)] = 2,
+	[AD4170_AFE_REG(5)] = 2,
+	[AD4170_AFE_REG(6)] = 2,
+	[AD4170_AFE_REG(7)] = 2,
+	/* Init FILTER register size */
+	[AD4170_FILTER_REG(0)]	= 2,
+	[AD4170_FILTER_REG(1)]	= 2,
+	[AD4170_FILTER_REG(2)]	= 2,
+	[AD4170_FILTER_REG(3)]	= 2,
+	[AD4170_FILTER_REG(4)]	= 2,
+	[AD4170_FILTER_REG(5)]	= 2,
+	[AD4170_FILTER_REG(6)]	= 2,
+	[AD4170_FILTER_REG(7)]	= 2,
+	/* Init FILTER_FS register size */
+	[AD4170_FILTER_FS_REG(0)]	= 2,
+	[AD4170_FILTER_FS_REG(1)]	= 2,
+	[AD4170_FILTER_FS_REG(2)]	= 2,
+	[AD4170_FILTER_FS_REG(3)]	= 2,
+	[AD4170_FILTER_FS_REG(4)]	= 2,
+	[AD4170_FILTER_FS_REG(5)]	= 2,
+	[AD4170_FILTER_FS_REG(6)]	= 2,
+	[AD4170_FILTER_FS_REG(7)]	= 2,
+	/* Init OFFSET register size */
+	[AD4170_OFFSET_REG(0)]	= 3,
+	[AD4170_OFFSET_REG(1)]	= 3,
+	[AD4170_OFFSET_REG(2)]	= 3,
+	[AD4170_OFFSET_REG(3)]	= 3,
+	[AD4170_OFFSET_REG(4)]	= 3,
+	[AD4170_OFFSET_REG(5)]	= 3,
+	[AD4170_OFFSET_REG(6)]	= 3,
+	[AD4170_OFFSET_REG(7)]	= 3,
+	/* Init GAIN register size */
+	[AD4170_GAIN_REG(0)]	= 3,
+	[AD4170_GAIN_REG(1)]	= 3,
+	[AD4170_GAIN_REG(2)]	= 3,
+	[AD4170_GAIN_REG(3)]	= 3,
+	[AD4170_GAIN_REG(4)]	= 3,

drivers/iio/adc/ad4170.h new file +4 -0

+	AD4170_BURNOUT_100NA,
+	AD4170_BURNOUT_2000NA,
+	AD4170_BURNOUT_10000NA,
+};

From: Ana-Maria Cusco <[email protected]>

From: Ana-Maria Cusco <[email protected]>

Add support for the AD4170 ADC with the following features:
- Single-shot read (read_raw), scale, sampling freq
- Multi channel buffer support
- Buffered capture in triggered mode
- Gain and offset calibration
- chop_iexc and chop_adc device configuration
- Powerdown switch configuration

Co-developed-by Dragos Bogdan <[email protected]>

Signed-off-by Dragos Bogdan <[email protected]>

Signed-off-by Ana-Maria Cusco <[email protected]>

Co-developed-by Marcelo Schmitt <[email protected]>

Signed-off-by Marcelo Schmitt <[email protected]>

---
 drivers/iio/adc/Kconfig  |   16 +
 drivers/iio/adc/Makefile |    1 +
 drivers/iio/adc/ad4170.c | 2049 ++++++++++++++++++++++++++++++++++++++

 drivers/iio/adc/ad4170.h |  316 ++++++
 4 files changed, 2382 insertions(+)
 create mode 100644 drivers/iio/adc/ad4170.c
 create mode 100644 drivers/iio/adc/ad4170.h

drivers/iio/adc/ad4170.c new file +12 -0

+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>

drivers/iio/adc/ad4170.c new file +19 -0

+#include <linux/unaligned.h>
+
 
 
+struct ad4170_state {
+	struct regmap *regmap;
+	struct spi_device *spi;
+	struct regulator_bulk_data supplies[7];
+	struct mutex lock; /* Protect filter, PGA, GPIO, chan read, chan config */
+	struct iio_chan_spec chans[AD4170_MAX_CHANNELS];
+	struct ad4170_chan_info chans_info[AD4170_MAX_CHANNELS];
+	struct ad4170_setup setups[AD4170_MAX_SETUPS];
+	u32 mclk_hz;
+	enum ad4170_pin_function pins_fn[AD4170_NUM_ANALOG_PINS];
+	enum ad4170_gpio_function gpio_fn[AD4170_NUM_GPIO_PINS];
+	unsigned int clock_ctrl;
+	struct clk *ext_clk;
+	struct clk_hw int_clk_hw;
+	int sps_tbl[ARRAY_SIZE(ad4170_filt_names)][ARRAY_SIZE(ad4170_filt_fs_tbl)][2];
+	struct completion completion;
+	struct iio_trigger *trig;

drivers/iio/adc/ad4170.c new file +17 -0

+	__be16 reg_read_tx_buf;
+};
+
 
 
+static int ad4170_get_input_range(struct ad4170_state *st,
+				  struct iio_chan_spec const *chan,
+				  unsigned int ref_sel)
+{
+	struct ad4170_chan_info *chan_info = &st->chans_info[chan->address];
+	struct ad4170_setup *setup = &st->setups[chan_info->setup_num];
+	bool bipolar = FIELD_GET(AD4170_AFE_BIPOLAR_MSK, setup->afe);
+	int refp, refn, ain_voltage, ret;
+
+	switch (ref_sel) {
+	case AD4170_AFE_REFIN_REFIN1:
+		refp = regulator_get_voltage(st->supplies[AD4170_REFIN1P_SUP].consumer);
+		refn = regulator_get_voltage(st->supplies[AD4170_REFIN1N_SUP].consumer);
+		break;

drivers/iio/adc/ad4170.c new file +11 -0

+		 */
 
 
+
+static int ad4170_clock_select(struct iio_dev *indio_dev)
+{
+	struct ad4170_state *st = iio_priv(indio_dev);
+	struct device *dev = &st->spi->dev;
+	int ret;
+
+	st->mclk_hz = AD4170_INT_FREQ_16MHZ;
+	ret = device_property_match_property_string(dev, "clock-names",
+						    ad4170_clk_sel,

(quoted diff) +98 -0

+
+		return dev_err_probe(dev, PTR_ERR(st->ext_clk),
+				     "Failed to get external clock\n");
+	}
+	st->clock_ctrl |= FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK,
+				     AD4170_EXTERNAL_OSC + ret);
+
+	ret = clk_prepare_enable(st->ext_clk);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to enable external clock\n");
+
+	ret = devm_add_action_or_reset(dev, ad4170_clk_disable_unprepare,
+				       st->ext_clk);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to add clock unwind action\n");
+
+	st->mclk_hz = clk_get_rate(st->ext_clk);
+	if (st->mclk_hz < AD4170_EXT_FREQ_MHZ_MIN ||
+	    st->mclk_hz > AD4170_EXT_FREQ_MHZ_MAX) {
+		return dev_err_probe(dev, -EINVAL,
+				     "Invalid external clock frequency %u\n",
+				     st->mclk_hz);
+	}
+	return 0;
+}
 
 
+
+/* ADC Register Lengths */
+static const unsigned int ad4170_reg_size[] = {
+	[AD4170_INTERFACE_CONFIG_A_REG] = 1,
+	[AD4170_STATUS_REG]	= 2,
+	[AD4170_DATA_24b_REG]	= 3,
+	[AD4170_PIN_MUXING_REG]	= 2,
+	[AD4170_CLOCK_CTRL_REG]	= 2,
+	[AD4170_POWER_DOWN_SW_REG]	= 2,
+	[AD4170_ADC_CTRL_REG]	= 2,
+	[AD4170_CHANNEL_EN_REG]	= 2,
+	/*
+	 * CHANNEL_SETUP and CHANNEL_MAP register are all 2 byte size each and
+	 * their addresses are interleaved such that we have CHANNEL_SETUP0
+	 * address followed by CHANNEL_MAP0 address, followed by CHANNEL_SETUP1,
+	 * and so on until CHANNEL_MAP15.
+	 * Thus, initialize the register size for them only once.
+	 */
+	[AD4170_CHAN_SETUP_REG(0) ... AD4170_CHAN_MAP_REG(AD4170_MAX_CHANNELS - 1)] = 2,
+	/*
+	 * MISC, AFE, FILTER, FILTER_FS, OFFSET, and GAIN register addresses are
+	 * also interleaved but MISC, AFE, FILTER, FILTER_FS, OFFSET are 16-bit
+	 * while OFFSET, GAIN are 24-bit registers so we can't init them all to
+	 * the same size.
+	 */
+	/* Init MISC register size */
+	[AD4170_MISC_REG(0)] = 2,
+	[AD4170_MISC_REG(1)] = 2,
+	[AD4170_MISC_REG(2)] = 2,
+	[AD4170_MISC_REG(3)] = 2,
+	[AD4170_MISC_REG(4)] = 2,
+	[AD4170_MISC_REG(5)] = 2,
+	[AD4170_MISC_REG(6)] = 2,
+	[AD4170_MISC_REG(7)] = 2,
+	/* Init AFE register size */
+	[AD4170_AFE_REG(0)] = 2,
+	[AD4170_AFE_REG(1)] = 2,
+	[AD4170_AFE_REG(2)] = 2,
+	[AD4170_AFE_REG(3)] = 2,
+	[AD4170_AFE_REG(4)] = 2,
+	[AD4170_AFE_REG(5)] = 2,
+	[AD4170_AFE_REG(6)] = 2,
+	[AD4170_AFE_REG(7)] = 2,
+	/* Init FILTER register size */
+	[AD4170_FILTER_REG(0)]	= 2,
+	[AD4170_FILTER_REG(1)]	= 2,
+	[AD4170_FILTER_REG(2)]	= 2,
+	[AD4170_FILTER_REG(3)]	= 2,
+	[AD4170_FILTER_REG(4)]	= 2,
+	[AD4170_FILTER_REG(5)]	= 2,
+	[AD4170_FILTER_REG(6)]	= 2,
+	[AD4170_FILTER_REG(7)]	= 2,
+	/* Init FILTER_FS register size */
+	[AD4170_FILTER_FS_REG(0)]	= 2,
+	[AD4170_FILTER_FS_REG(1)]	= 2,
+	[AD4170_FILTER_FS_REG(2)]	= 2,
+	[AD4170_FILTER_FS_REG(3)]	= 2,
+	[AD4170_FILTER_FS_REG(4)]	= 2,
+	[AD4170_FILTER_FS_REG(5)]	= 2,
+	[AD4170_FILTER_FS_REG(6)]	= 2,
+	[AD4170_FILTER_FS_REG(7)]	= 2,
+	/* Init OFFSET register size */
+	[AD4170_OFFSET_REG(0)]	= 3,
+	[AD4170_OFFSET_REG(1)]	= 3,
+	[AD4170_OFFSET_REG(2)]	= 3,
+	[AD4170_OFFSET_REG(3)]	= 3,
+	[AD4170_OFFSET_REG(4)]	= 3,
+	[AD4170_OFFSET_REG(5)]	= 3,
+	[AD4170_OFFSET_REG(6)]	= 3,
+	[AD4170_OFFSET_REG(7)]	= 3,
+	/* Init GAIN register size */

+};

ADCs can have different input configurations such that developers can get confused when trying to model some of them into IIO channels.

For example, some differential ADCs can have their channels configured as pseudo-differential channels. In that configuration, only one input connects to the signal of interest as opposed to using two inputs of a differential input configuration. Datasheets sometimes also refer to pseudo-differential inputs as single-ended inputs even though they have distinct physical configuration and measurement procedure. There has been some previous discussion in the mailing list about pseudo-differential and single-ended channels [1].

Documenting the many possible ADC channel configurations should provide two benefits:
A) Consolidate the knowledge from [2] and from [1], and hopefully reduce the reviewing time of forthcoming ADC drivers.
B) Help Linux developers figure out quicker how to better support differential ADCs, specially those that can have channels configured as pseudo-differential inputs.

Add documentation about common ADC characteristics and IIO support for them.

[1]: https://lore.kernel.org/linux-iio/[email protected]/
[2]: https://www.analog.com/en/resources/technical-articles/sar-adc-input-types.html.

Signed-off-by Marcelo Schmitt <[email protected]>

---

 Documentation/iio/iio_adc.rst | 280 ++++++++++++++++++++++++++++++++++
 Documentation/iio/index.rst   |   1 +
 2 files changed, 281 insertions(+)
 create mode 100644 Documentation/iio/iio_adc.rst

Documentation/iio/iio_adc.rst new file +16 -0

new file mode 100644
index 000000000000..43b8cad547c9
@@ -0,0 +1,280 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=========================
+IIO Abstractions for ADCs
+=========================
+
+1. Overview
+===========
+
+The IIO subsystem supports many Analog to Digital Converters (ADCs). Some ADCs
+have features and characteristics that are supported in specific ways by IIO
+device drivers. This documentation describes common ADC features and explains
+how they are (should be?) supported by the IIO subsystem.
+
+1. ADC Channel Types
+====================

Documentation/iio/iio_adc.rst new file +69 -0

+pseudo-differential) and two possible polarities (unipolar, bipolar). The input
+type (single-ended, differential, pseudo-differential) is one channel
+characteristic, and is completely independent of the polarity (unipolar,
+bipolar) aspect. A comprehensive article about ADC input types (on which this
+doc is heavily based on) can be found at
+https://www.analog.com/en/resources/technical-articles/sar-adc-input-types.html.
+
+1.1 Single-ended channels
+-------------------------
+
+Single-ended channels digitize the analog input voltage relative to ground and
+can be either unipolar or bipolar.
+
+1.1.1 Single-ended Unipolar Channels
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+::
+
+  ---------- VREF -------------
+      ´ `           ´ `                  _____________
+    /     \       /     \               /             |
+   /       \     /       \         --- <  IN    ADC   |
+            \   /         \   /         \             |
+             `-´           `-´           \       VREF |
+  -------- GND (0V) -----------           +-----------+
+                                                  ^
+                                                  |
+                                             External VREF
+
+The input voltage to a **single-ended unipolar** channel is allowed to swing
+from GND to VREF (where VREF is a voltage reference with electrical potential
+higher than system ground). The maximum input voltage is also called VFS
+(full-scale input voltage), with VFS being determined by VREF. The voltage
+reference may be provided from an external supply or derived from the chip power
+source.
+
+A single-ended unipolar channel could be described in device tree like the
+following example::
+
+    adc@0 {
+        ...
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        channel@0 {
+            reg = <0>;
+        };
+    };
+
+See ``Documentation/devicetree/bindings/iio/adc/adc.yaml`` for the complete
+documentation of ADC specific device tree properties.
+
+
+1.1.2 Single-ended Bipolar Channels
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+::
+
+  ---------- +VREF ------------
+      ´ `           ´ `                  _____________________
+    /     \       /     \               /                     |
+   /       \     /       \         --- <  IN          ADC     |
+            \   /         \   /         \                     |
+             `-´           `-´           \       +VREF  -VREF |
+  ---------- -VREF ------------           +-------------------+
+                                                  ^       ^
+                                                  |       |
+                             External +VREF ------+  External -VREF
+

Documentation/iio/iio_adc.rst new file +9 -0

+
+    adc@0 {
+        ...
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        channel@0 {
+            reg = <0>;
+            bipolar;

Documentation/iio/iio_adc.rst new file +33 -0

+
+1.2.1 Differential Bipolar Channels
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+::
+
+  -------- +VREF ------
+    ´ `       ´ `               +-------------------+
+  /     \   /     \   /        /                    |
+         `-´       `-´    --- <  IN+                |
+  -------- -VREF ------        |                    |
+                               |            ADC     |
+  -------- +VREF ------        |                    |
+        ´ `       ´ `     --- <  IN-                |
+  \   /     \   /     \        \       +VREF  -VREF |
+   `-´       `-´                +-------------------+
+  -------- -VREF ------                  ^       ^
+                                         |       +---- External -VREF
+                                  External +VREF
+
+The analog signals to **differential bipolar** inputs are also allowed to swing
+from -VREF to +VREF. If -VREF is below system GND, these are also called
+differential true bipolar inputs.
+
+Device tree example of a differential bipolar channel::
+
+    adc@0 {
+        ...
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        channel@0 {
+            reg = <0>;