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riscv: dts: allwinner: d1: Add CPU thermal sensor and zone

PATCH In review Alex Studer 2 participants 3 messages Feb 18, 2025 – Feb 19, 2025

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Device tree bindings RISC-V Arm/Allwinner sunXi SoC support
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Alex Studer

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#0 lore raw

PATCH 1/1 riscv: dts: allwinner: d1: Add CPU thermal sensor and zone

The sun20i THS (built in CPU thermal sensor) is supported in code, but was never added to the device tree. So, add it to the device tree, along with a thermal zone for the CPU.

Signed-off-by Alex Studer <[email protected]>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++++
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 16 ++++++++++
 2 files changed, 47 insertions(+)
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +31 -0
index 6367112e6..bdde82aa8 100644
@@ -3,6 +3,8 @@
 
 #define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
 
+#include <dt-bindings/thermal/thermal.h>
+
 #include "sunxi-d1s-t113.dtsi"
 
 / {

@@ -115,4 +117,33 @@ pmu {
 			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
 			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
 	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&ths>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu-crit {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
 };
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +16 -0
index e4175adb0..fcfcaf06c 100644
@@ -426,6 +426,10 @@ sid: efuse@3006000 {
 			reg = <0x3006000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			ths_calibration: thermal-sensor-calibration@14 {
+				reg = <0x14 0x8>;
+			};
 		};
 
 		crypto: crypto@3040000 {

@@ -934,5 +938,17 @@ rtc: rtc@7090000 {
 			clock-names = "bus", "hosc", "ahb";
 			#clock-cells = <1>;
 		};
+
+		ths: thermal-sensor@2009400 {
+			compatible = "allwinner,sun20i-d1-ths";
+			reg = <0x2009400 0x100>;
+			interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_THS>;
+			clock-names = "bus";
+			resets = <&ccu RST_BUS_THS>;
+			nvmem-cells = <&ths_calibration>;
+			nvmem-cell-names = "calibration";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };
Signature · 8 lines
2.48.1



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#1 lore raw

Dne torek, 18. februar 2025 ob 03:06:29 Srednjeevropski standardni čas je Alex Studer napisal(a):

Quoted 15 lines

The sun20i THS (built in CPU thermal sensor) is supported in code, but was never added to the device tree. So, add it to the device tree, along with a thermal zone for the CPU.

Signed-off-by Alex Studer <[email protected]>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++++
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 16 ++++++++++
 2 files changed, 47 insertions(+)
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +0 -0
index 6367112e6..bdde82aa8 100644

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi line 6

Quoted 4 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +1 -0
@@ -3,6 +3,8 @@
 
 #define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
 
+#include <dt-bindings/thermal/thermal.h>

Put above line on top (before SOC_PERIPHERAL_IRQ()).

Quoted 24 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +17 -0
+
 #include "sunxi-d1s-t113.dtsi"
 
 / {

@@ -115,4 +117,33 @@ pmu {
 			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
 			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
 	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&ths>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu_alert: cpu-alert {

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi pmu { · line 145

Quoted 10 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +10 -0
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				cpu-crit {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "critical";
+				};

Where do those limits come from?

Quoted 20 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +3 -0
+			};
+		};
+	};
 };
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4 -0
index e4175adb0..fcfcaf06c 100644
@@ -426,6 +426,10 @@ sid: efuse@3006000 {
 			reg = <0x3006000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			ths_calibration: thermal-sensor-calibration@14 {
+				reg = <0x14 0x8>;
+			};
 		};
 
 		crypto: crypto@3040000 {

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi rtc: rtc@7090000 { · line 944

Quoted 7 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4 -0
@@ -934,5 +938,17 @@ rtc: rtc@7090000 {
 			clock-names = "bus", "hosc", "ahb";
 			#clock-cells = <1>;
 		};
+
+		ths: thermal-sensor@2009400 {
+			compatible = "allwinner,sun20i-d1-ths";
+			reg = <0x2009400 0x100>;

Size should be 0x400.

Best regards,
Jernej

Quoted 11 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +8 -0
+			interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_THS>;
+			clock-names = "bus";
+			resets = <&ccu RST_BUS_THS>;
+			nvmem-cells = <&ths_calibration>;
+			nvmem-cell-names = "calibration";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };
author
#2 lore raw
Quoted 17 lines · Jernej Škrabec

Dne torek, 18. februar 2025 ob 03:06:29 Srednjeevropski standardni čas je Alex Studer napisal(a):

Quoted 16 lines

The sun20i THS (built in CPU thermal sensor) is supported in code, but was never added to the device tree. So, add it to the device tree, along with a thermal zone for the CPU.

Signed-off-by Alex Studer <[email protected]>
---
 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 31 +++++++++++++++++++
 .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 16 ++++++++++
 2 files changed, 47 insertions(+)
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +0 -0
index 6367112e6..bdde82aa8 100644
@@ -3,6 +3,8 @@
Quoted 4 lines

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi line 6

Quoted 3 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +1 -0
 #define SOC_PERIPHERAL_IRQ(nr)	(nr + 16)
 
+#include <dt-bindings/thermal/thermal.h>

Put above line on top (before SOC_PERIPHERAL_IRQ()).

Will fix in v2.

Quoted 27 lines
Quoted 27 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +20 -0
+
 #include "sunxi-d1s-t113.dtsi"
 
 / {

@@ -115,4 +117,33 @@ pmu {
 			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
 			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
 	};
+
+	thermal-zones {
+		cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+			thermal-sensors = <&ths>;
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+
+			trips {
+				cpu_alert: cpu-alert {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
Quoted 8 lines

arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi pmu { · line 145

Quoted 7 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +7 -0
+				};
+
+				cpu-crit {
+					temperature = <100000>;
+					hysteresis = <0>;
+					type = "critical";
+				};

Where do those limits come from?

I took them from the definitions in arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi, which is what I generally based this patch on. I checked the D1s datasheet and it does specify a max "Ambient Operating Temperature" of 70 C and a max "Working Junction Temperature Range" of 110 C. So I could use those, but the dtsi files for the other sunxi chips don't seem to follow their respective datasheets, so I wasn't sure what to do here.

Quoted 18 lines
Quoted 18 lines
arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +3 -0
+			};
+		};
+	};
 };
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4 -0
index e4175adb0..fcfcaf06c 100644
@@ -426,6 +426,10 @@ sid: efuse@3006000 {
 			reg = <0x3006000 0x1000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
+			ths_calibration: thermal-sensor-calibration@14 {
+				reg = <0x14 0x8>;
+			};
 		};
Quoted 10 lines

arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi rtc: rtc@7090000 { · line 944

Quoted 9 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +4 -0
 		crypto: crypto@3040000 {

@@ -934,5 +938,17 @@ rtc: rtc@7090000 {
 			clock-names = "bus", "hosc", "ahb";
 			#clock-cells = <1>;
 		};
+
+		ths: thermal-sensor@2009400 {
+			compatible = "allwinner,sun20i-d1-ths";
+			reg = <0x2009400 0x100>;

Size should be 0x400.

Will fix in v2.

Quoted 3 lines

Best regards,
Jernej

Thanks,
Alex

Quoted 15 lines
Quoted 12 lines
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +8 -0
+			interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_THS>;
+			clock-names = "bus";
+			resets = <&ccu RST_BUS_THS>;
+			nvmem-cells = <&ths_calibration>;
+			nvmem-cell-names = "calibration";
+			#thermal-sensor-cells = <0>;
+		};
 	};
 };