perf/x86/intel: Fix event constraints for LNC
Subsystems (3)
PATCH 1/1 perf/x86/intel: Fix event constraints for LNC
From: Kan Liang <[email protected]>
According to the latest event list, update the event constraint tables for Lion Cove core.
The general rule (the event codes < 0x90 are restricted to counters 0-3.) has been removed. There is no restriction for most of the performance monitoring events.
Fixes a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Reported-by Amiri Khalil <[email protected]>
Signed-off-by Kan Liang <[email protected]>
--- arch/x86/events/intel/core.c | 20 +++++++------------- arch/x86/events/intel/ds.c | 2 +- 2 files changed, 8 insertions(+), 14 deletions(-)
arch/x86/events/intel/core.c +7 -13
@@ -397,34 +397,28 @@ static struct event_constraint intel_lnc_event_constraints[] = {METRIC_EVENT_CONSTRAINT (INTEL_TD_METRIC_FETCH_LAT ,6 ),METRIC_EVENT_CONSTRAINT (INTEL_TD_METRIC_MEM_BOUND ,7 ), +INTEL_EVENT_CONSTRAINT (0x20 ,0xf ), + +INTEL_UEVENT_CONSTRAINT (0x012a ,0xf ), +INTEL_UEVENT_CONSTRAINT (0x012b ,0xf ),INTEL_UEVENT_CONSTRAINT (0x0148 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x0175 ,0x4 ),INTEL_EVENT_CONSTRAINT (0x2e ,0x3ff ),INTEL_EVENT_CONSTRAINT (0x3c ,0x3ff ), -/* -* Generally event codes < 0x90 are restricted to counters 0-3. -* The 0x2E and 0x3C are exception, which has no restriction. -*/ -INTEL_EVENT_CONSTRAINT_RANGE (0x01 ,0x8f ,0xf ), -INTEL_UEVENT_CONSTRAINT (0x01a3 ,0xf ), -INTEL_UEVENT_CONSTRAINT (0x02a3 ,0xf ),INTEL_UEVENT_CONSTRAINT (0x08a3 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x0ca3 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x04a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x08a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x10a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x01b1 ,0x8 ), +INTEL_UEVENT_CONSTRAINT (0x01cd ,0x3fc ),INTEL_UEVENT_CONSTRAINT (0x02cd ,0x3 ), -INTEL_EVENT_CONSTRAINT (0xce ,0x1 ),INTEL_EVENT_CONSTRAINT_RANGE (0xd0 ,0xdf ,0xf ), -/* -* Generally event codes >= 0x90 are likely to have no restrictions. -* The exception are defined as above. -*/ -INTEL_EVENT_CONSTRAINT_RANGE (0x90 ,0xfe ,0x3ff ), + +INTEL_UEVENT_CONSTRAINT (0x00e0 ,0xf ),EVENT_CONSTRAINT_END };
arch/x86/events/intel/ds.c +1 -1
@@ -1199,7 +1199,7 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {INTEL_FLAGS_UEVENT_CONSTRAINT (0x100 ,0x100000000ULL ),/* INST_RETIRED.PREC_DIST */ INTEL_FLAGS_UEVENT_CONSTRAINT (0x0400 ,0x800000000ULL ), -INTEL_HYBRID_LDLAT_CONSTRAINT (0x1cd ,0x3ff ), +INTEL_HYBRID_LDLAT_CONSTRAINT (0x1cd ,0x3fc ),INTEL_HYBRID_STLAT_CONSTRAINT (0x2cd ,0x3 ),INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
Signature · 1 line
2.38.1
The following commit has been merged into the perf/urgent branch of tip:
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 782cffeec9ad96daa64ffb2d527b2a052fb02552 Gitweb: https://git.kernel.org/tip/782cffeec9ad96daa64ffb2d527b2a052fb02552 Author: Kan Liang <[email protected]> AuthorDate: Wed, 19 Feb 2025 06:10:05 -08:00 Committer: Peter Zijlstra <[email protected]> CommitterDate: Thu, 20 Feb 2025 16:07:10 +01:00
perf/x86/intel: Fix event constraints for LNC
According to the latest event list, update the event constraint tables for Lion Cove core.
The general rule (the event codes < 0x90 are restricted to counters 0-3.) has been removed. There is no restriction for most of the performance monitoring events.
Fixes a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Reported-by Amiri Khalil <[email protected]>
Signed-off-by Kan Liang <[email protected]>
Signed-off-by Peter Zijlstra (Intel) <[email protected]>
--- arch/x86/events/intel/core.c | 20 +++++++------------- arch/x86/events/intel/ds.c | 2 +- 2 files changed, 8 insertions(+), 14 deletions(-)
arch/x86/events/intel/core.c +7 -13
@@ -397,34 +397,28 @@ static struct event_constraint intel_lnc_event_constraints[] = {METRIC_EVENT_CONSTRAINT (INTEL_TD_METRIC_FETCH_LAT ,6 ),METRIC_EVENT_CONSTRAINT (INTEL_TD_METRIC_MEM_BOUND ,7 ), +INTEL_EVENT_CONSTRAINT (0x20 ,0xf ), + +INTEL_UEVENT_CONSTRAINT (0x012a ,0xf ), +INTEL_UEVENT_CONSTRAINT (0x012b ,0xf ),INTEL_UEVENT_CONSTRAINT (0x0148 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x0175 ,0x4 ),INTEL_EVENT_CONSTRAINT (0x2e ,0x3ff ),INTEL_EVENT_CONSTRAINT (0x3c ,0x3ff ), -/* -* Generally event codes < 0x90 are restricted to counters 0-3. -* The 0x2E and 0x3C are exception, which has no restriction. -*/ -INTEL_EVENT_CONSTRAINT_RANGE (0x01 ,0x8f ,0xf ), -INTEL_UEVENT_CONSTRAINT (0x01a3 ,0xf ), -INTEL_UEVENT_CONSTRAINT (0x02a3 ,0xf ),INTEL_UEVENT_CONSTRAINT (0x08a3 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x0ca3 ,0x4 ),INTEL_UEVENT_CONSTRAINT (0x04a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x08a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x10a4 ,0x1 ),INTEL_UEVENT_CONSTRAINT (0x01b1 ,0x8 ), +INTEL_UEVENT_CONSTRAINT (0x01cd ,0x3fc ),INTEL_UEVENT_CONSTRAINT (0x02cd ,0x3 ), -INTEL_EVENT_CONSTRAINT (0xce ,0x1 ),INTEL_EVENT_CONSTRAINT_RANGE (0xd0 ,0xdf ,0xf ), -/* -* Generally event codes >= 0x90 are likely to have no restrictions. -* The exception are defined as above. -*/ -INTEL_EVENT_CONSTRAINT_RANGE (0x90 ,0xfe ,0x3ff ), + +INTEL_UEVENT_CONSTRAINT (0x00e0 ,0xf ),EVENT_CONSTRAINT_END };
arch/x86/events/intel/ds.c +1 -1
@@ -1199,7 +1199,7 @@ struct event_constraint intel_lnc_pebs_event_constraints[] = {INTEL_FLAGS_UEVENT_CONSTRAINT (0x100 ,0x100000000ULL ),/* INST_RETIRED.PREC_DIST */ INTEL_FLAGS_UEVENT_CONSTRAINT (0x0400 ,0x800000000ULL ), -INTEL_HYBRID_LDLAT_CONSTRAINT (0x1cd ,0x3ff ), +INTEL_HYBRID_LDLAT_CONSTRAINT (0x1cd ,0x3fc ),INTEL_HYBRID_STLAT_CONSTRAINT (0x2cd ,0x3 ),INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD (0x11d0 ,0xf ),/* MEM_INST_RETIRED.STLB_MISS_LOADS */ INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */