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irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller

PATCH Superseded Inochi Amaoto 3 participants 7 messages Mar 7, 2025 – Apr 8, 2025

Subsystems (3)
Device tree bindings irqchip drivers Sophgo devicetrees and drivers

v2 of 4 Superseded Latest is v4 →

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Inochi Amaoto

author maintainer
#0 lore raw

v2 cover irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller

Like Sophgo SG2042, SG2044 also uses an external interrupt controller to handle MSI/MSI-X. It supports more interrupt and has a different msi message address mapping.

The patch follows tips:irq/drivers, which contains Chen Wang's patch for SG2042 MSI controller [1].

[1]: https://lore.kernel.org/all/[email protected]/

Changed from v1:
- https://lore.kernel.org/all/[email protected]/
1. patch 1: apply Conor's tag
2. patch 1: improve the bindings comments.
3. patch 2: rebased on tips:irq/drivers patch
4. patch 2: remove unused macro "SG2042_MAX_MSI_VECTOR"
5. patch 2: rename generic structure name to match sg204x.
6. patch 2: rename info field name to avoid misunderstanding.

Inochi Amaoto (2):
dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller

 .../sophgo,sg2042-msi.yaml                    |   4 +-
 drivers/irqchip/irq-sg2042-msi.c              | 124 +++++++++++++++---
 2 files changed, 106 insertions(+), 22 deletions(-)

--
2.48.1

author maintainer
#1 lore raw

PATCH v2 1/2 dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller

Like SG2042, SG2044 also uses an external msi controller to provide MSI interrupt for PCIe controllers. The difference between these two msi controlling are summary as follows:

1. SG2044 acks the interrupt by writing 0, as on SG2042 by setting related bit.
2. SG2044 uses interrupt number mod 32 as msi message data, but SG2042 uses setting related bit.

Add support for the SG2044 msi controller.

Signed-off-by Inochi Amaoto <[email protected]>
Acked-by Conor Dooley <[email protected]>
---
 .../bindings/interrupt-controller/sophgo,sg2042-msi.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml +3 -1
index e1ffd55fa7bf..f6b8b1d92f79 100644
@@ -18,7 +18,9 @@ allOf:
 
 properties:
   compatible:
-    const: sophgo,sg2042-msi
+    enum:
+      - sophgo,sg2042-msi
+      - sophgo,sg2044-msi
 
   reg:
     items:

--
2.48.1

Reviewed-by on v2 1/2
#2 lore raw

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller

Quoted 9 lines · Inochi Amaoto

Like SG2042, SG2044 also uses an external msi controller to provide MSI interrupt for PCIe controllers. The difference between these two msi controlling are summary as follows:

1. SG2044 acks the interrupt by writing 0, as on SG2042 by setting related bit.
2. SG2044 uses interrupt number mod 32 as msi message data, but SG2042 uses setting related bit.

Quoted 4 lines

Add support for the SG2044 msi controller.

Signed-off-by Inochi Amaoto <[email protected]>
Acked-by Conor Dooley <[email protected]>
Reviewed-by Chen Wang <[email protected]>
Quoted 22 lines
---
  .../bindings/interrupt-controller/sophgo,sg2042-msi.yaml      | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-msi.yaml +3 -2
index e1ffd55fa7bf..f6b8b1d92f79 100644
@@ -18,7 +18,9 @@ allOf:
 
  properties:
    compatible:
-    const: sophgo,sg2042-msi
+    enum:
+      - sophgo,sg2042-msi
+      - sophgo,sg2044-msi
 
    reg:
      items:
--

2.48.1

author maintainer
#3 lore raw

PATCH v2 2/2 irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller

In reply to Inochi Amaoto

Add support for Sophgo SG2044 MSI interrupt controller.

Signed-off-by Inochi Amaoto <[email protected]>
---
 drivers/irqchip/irq-sg2042-msi.c | 124 +++++++++++++++++++++++++------
 1 file changed, 103 insertions(+), 21 deletions(-)
drivers/irqchip/irq-sg2042-msi.c +103 -21
index ee682e87eb8b..183002efd86c 100644
@@ -19,21 +19,36 @@
 
 #include "irq-msi-lib.h"
 
-#define SG2042_MAX_MSI_VECTOR	32
+struct sg2042_msi_chip_info {
+	const struct irq_chip		*irqchip;
+	const struct msi_parent_ops	*parent_ops;
+};
+
+/**
+ * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller
+ * @reg_clr:		clear reg, see TRM, 10.1.33, GP_INTR0_CLR
+ * @doorbell_addr:	see TRM, 10.1.32, GP_INTR0_SET
+ * @irq_first:		First vectors number that MSIs starts
+ * @num_irqs:		Number of vectors for MSIs
+ * @msi_map:		mapping for allocated MSI vectors.
+ * @msi_map_lock:	Lock for msi_map
+ * @chip_info:		chip specific infomations
+ */
+struct sg204x_msi_chipdata {
+	void __iomem				*reg_clr;
 
-struct sg2042_msi_chipdata {
-	void __iomem	*reg_clr;	// clear reg, see TRM, 10.1.33, GP_INTR0_CLR
+	phys_addr_t				doorbell_addr;
 
-	phys_addr_t	doorbell_addr;	// see TRM, 10.1.32, GP_INTR0_SET
+	u32					irq_first;
+	u32					num_irqs;
 
-	u32		irq_first;	// The vector number that MSIs starts
-	u32		num_irqs;	// The number of vectors for MSIs
+	unsigned long				*msi_map;
+	struct mutex				msi_map_lock;
 
-	DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR);
-	struct mutex	msi_map_lock;	// lock for msi_map
+	const struct sg2042_msi_chip_info	*chip_info;
 };
 
-static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int num_req)
+static int sg2042_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int num_req)
 {
 	int first;
 

@@ -43,7 +58,7 @@ static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int num_r
 	return first >= 0 ? first : -ENOSPC;
 }
 
-static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, int hwirq, int num_req)
+static void sg2042_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hwirq, int num_req)
 {
 	guard(mutex)(&data->msi_map_lock);
 	bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req));

@@ -51,7 +66,7 @@ static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, int hwirq, i
 
 static void sg2042_msi_irq_ack(struct irq_data *d)
 {
-	struct sg2042_msi_chipdata *data  = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data  = irq_data_get_irq_chip_data(d);
 	int bit_off = d->hwirq;
 
 	writel(1 << bit_off, data->reg_clr);

@@ -61,7 +76,7 @@ static void sg2042_msi_irq_ack(struct irq_data *d)
 
 static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 {
-	struct sg2042_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
 
 	msg->address_hi = upper_32_bits(data->doorbell_addr);
 	msg->address_lo = lower_32_bits(data->doorbell_addr);

@@ -79,9 +94,38 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = {
 	.irq_compose_msi_msg	= sg2042_msi_irq_compose_msi_msg,
 };
 
+static void sg2044_msi_irq_ack(struct irq_data *d)
+{
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+
+	writel(0, (unsigned int *)data->reg_clr + d->hwirq);
+	irq_chip_ack_parent(d);
+}
+
+static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
+{
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	phys_addr_t doorbell = data->doorbell_addr +  4 * (d->hwirq / 32);
+
+	msg->address_lo = lower_32_bits(doorbell);
+	msg->address_hi = upper_32_bits(doorbell);
+	msg->data = d->hwirq % 32;
+}
+
+static struct irq_chip sg2044_msi_middle_irq_chip = {
+	.name			= "SG2044 MSI",
+	.irq_ack		= sg2044_msi_irq_ack,
+	.irq_mask		= irq_chip_mask_parent,
+	.irq_unmask		= irq_chip_unmask_parent,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= irq_chip_set_affinity_parent,
+#endif
+	.irq_compose_msi_msg	= sg2044_msi_irq_compose_msi_msg,
+};
+
 static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq)
 {
-	struct sg2042_msi_chipdata *data = domain->host_data;
+	struct sg204x_msi_chipdata *data = domain->host_data;
 	struct irq_fwspec fwspec;
 	struct irq_data *d;
 	int ret;

@@ -102,7 +146,7 @@ static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsigned in
 static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
 					  unsigned int nr_irqs, void *args)
 {
-	struct sg2042_msi_chipdata *data = domain->host_data;
+	struct sg204x_msi_chipdata *data = domain->host_data;
 	int hwirq, err, i;
 
 	hwirq = sg2042_msi_allocate_hwirq(data, nr_irqs);

@@ -115,7 +159,7 @@ static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, unsigned in
 			goto err_hwirq;
 
 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
-					      &sg2042_msi_middle_irq_chip, data);
+					      data->chip_info->irqchip, data);
 	}
 
 	return 0;

@@ -131,7 +175,7 @@ static void sg2042_msi_middle_domain_free(struct irq_domain *domain, unsigned in
 					  unsigned int nr_irqs)
 {
 	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
-	struct sg2042_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
 
 	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 	sg2042_msi_free_hwirq(data, d->hwirq, nr_irqs);

@@ -157,7 +201,22 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = {
 	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
 };
 
-static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
+#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS |	\
+				   MSI_FLAG_USE_DEF_CHIP_OPS)
+
+#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK |	\
+				    MSI_FLAG_PCI_MSIX)
+
+static const struct msi_parent_ops sg2044_msi_parent_ops = {
+	.required_flags		= SG2044_MSI_FLAGS_REQUIRED,
+	.supported_flags	= SG2044_MSI_FLAGS_SUPPORTED,
+	.bus_select_mask	= MATCH_PCI_MSI,
+	.bus_select_token	= DOMAIN_BUS_NEXUS,
+	.prefix			= "SG2044-",
+	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
+};
+
+static int sg2042_msi_init_domains(struct sg204x_msi_chipdata *data,
 				   struct irq_domain *plic_domain, struct device *dev)
 {
 	struct fwnode_handle *fwnode = dev_fwnode(dev);

@@ -173,7 +232,7 @@ static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
 	irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
 
 	middle_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
-	middle_domain->msi_parent_ops = &sg2042_msi_parent_ops;
+	middle_domain->msi_parent_ops = data->chip_info->parent_ops;
 
 	return 0;
 }

@@ -181,16 +240,22 @@ static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
 static int sg2042_msi_probe(struct platform_device *pdev)
 {
 	struct fwnode_reference_args args = { };
-	struct sg2042_msi_chipdata *data;
+	struct sg204x_msi_chipdata *data;
 	struct device *dev = &pdev->dev;
 	struct irq_domain *plic_domain;
 	struct resource *res;
 	int ret;
 
-	data = devm_kzalloc(dev, sizeof(struct sg2042_msi_chipdata), GFP_KERNEL);
+	data = devm_kzalloc(dev, sizeof(struct sg204x_msi_chipdata), GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;
 
+	data->chip_info = device_get_match_data(&pdev->dev);
+	if (!data->chip_info) {
+		dev_err(&pdev->dev, "Failed to get irqchip\n");
+		return -EINVAL;
+	}
+
 	data->reg_clr = devm_platform_ioremap_resource_byname(pdev, "clr");
 	if (IS_ERR(data->reg_clr)) {
 		dev_err(dev, "Failed to map clear register\n");

@@ -231,11 +296,28 @@ static int sg2042_msi_probe(struct platform_device *pdev)
 
 	mutex_init(&data->msi_map_lock);
 
+	data->msi_map = devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERNEL);
+	if (!data->msi_map) {
+		dev_err(&pdev->dev, "Unable to allocate msi mapping\n");
+		return -ENOMEM;
+	}
+
 	return sg2042_msi_init_domains(data, plic_domain, dev);
 }
 
+static const struct sg2042_msi_chip_info sg2042_of_data = {
+	.irqchip	= &sg2042_msi_middle_irq_chip,
+	.parent_ops	= &sg2042_msi_parent_ops,
+};
+
+static const struct sg2042_msi_chip_info sg2044_of_data = {
+	.irqchip	= &sg2044_msi_middle_irq_chip,
+	.parent_ops	= &sg2044_msi_parent_ops,
+};
+
 static const struct of_device_id sg2042_msi_of_match[] = {
-	{ .compatible	= "sophgo,sg2042-msi" },
+	{ .compatible	= "sophgo,sg2042-msi", .data	= &sg2042_of_data },
+	{ .compatible	= "sophgo,sg2044-msi", .data	= &sg2044_of_data },
 	{ }
 };
Signature · 1 line
2.48.1
Reviewed-by on v2 2/2
#4 lore raw
Quoted 12 lines · Inochi Amaoto

Add support for Sophgo SG2044 MSI interrupt controller.

Signed-off-by Inochi Amaoto <[email protected]>
---
  drivers/irqchip/irq-sg2042-msi.c | 124 +++++++++++++++++++++++++------
  1 file changed, 103 insertions(+), 21 deletions(-)
drivers/irqchip/irq-sg2042-msi.c +0 -0
index ee682e87eb8b..183002efd86c 100644

drivers/irqchip/irq-sg2042-msi.c line 26

Quoted 9 lines
drivers/irqchip/irq-sg2042-msi.c +5 -1
@@ -19,21 +19,36 @@
 
  #include "irq-msi-lib.h"
 
-#define SG2042_MAX_MSI_VECTOR	32
+struct sg2042_msi_chip_info {
+	const struct irq_chip		*irqchip;
+	const struct msi_parent_ops	*parent_ops;
+};
+

For this new structure type, recommend to name it as "sg204x_msi_chip_info".

Others LGTM.

Reviewed-by Chen Wang <[email protected]>
Quoted 218 lines
drivers/irqchip/irq-sg2042-msi.c +98 -20
+/**
+ * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller
+ * @reg_clr:		clear reg, see TRM, 10.1.33, GP_INTR0_CLR
+ * @doorbell_addr:	see TRM, 10.1.32, GP_INTR0_SET
+ * @irq_first:		First vectors number that MSIs starts
+ * @num_irqs:		Number of vectors for MSIs
+ * @msi_map:		mapping for allocated MSI vectors.
+ * @msi_map_lock:	Lock for msi_map
+ * @chip_info:		chip specific infomations
+ */
+struct sg204x_msi_chipdata {
+	void __iomem				*reg_clr;
 
-struct sg2042_msi_chipdata {
-	void __iomem	*reg_clr;	// clear reg, see TRM, 10.1.33, GP_INTR0_CLR
+	phys_addr_t				doorbell_addr;
 
-	phys_addr_t	doorbell_addr;	// see TRM, 10.1.32, GP_INTR0_SET
+	u32					irq_first;
+	u32					num_irqs;
 
-	u32		irq_first;	// The vector number that MSIs starts
-	u32		num_irqs;	// The number of vectors for MSIs
+	unsigned long				*msi_map;
+	struct mutex				msi_map_lock;
 
-	DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR);
-	struct mutex	msi_map_lock;	// lock for msi_map
+	const struct sg2042_msi_chip_info	*chip_info;
  };
 
-static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int num_req)
+static int sg2042_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int num_req)
  {
  	int first;
 

@@ -43,7 +58,7 @@ static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int num_r
  	return first >= 0 ? first : -ENOSPC;
  }
 
-static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, int hwirq, int num_req)
+static void sg2042_msi_free_hwirq(struct sg204x_msi_chipdata *data, int hwirq, int num_req)
  {
  	guard(mutex)(&data->msi_map_lock);
  	bitmap_release_region(data->msi_map, hwirq, get_count_order(num_req));

@@ -51,7 +66,7 @@ static void sg2042_msi_free_hwirq(struct sg2042_msi_chipdata *data, int hwirq, i
 
  static void sg2042_msi_irq_ack(struct irq_data *d)
  {
-	struct sg2042_msi_chipdata *data  = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data  = irq_data_get_irq_chip_data(d);
  	int bit_off = d->hwirq;
 
  	writel(1 << bit_off, data->reg_clr);

@@ -61,7 +76,7 @@ static void sg2042_msi_irq_ack(struct irq_data *d)
 
  static void sg2042_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
  {
-	struct sg2042_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
 
  	msg->address_hi = upper_32_bits(data->doorbell_addr);
  	msg->address_lo = lower_32_bits(data->doorbell_addr);

@@ -79,9 +94,38 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = {
  	.irq_compose_msi_msg	= sg2042_msi_irq_compose_msi_msg,
  };
 
+static void sg2044_msi_irq_ack(struct irq_data *d)
+{
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+
+	writel(0, (unsigned int *)data->reg_clr + d->hwirq);
+	irq_chip_ack_parent(d);
+}
+
+static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
+{
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	phys_addr_t doorbell = data->doorbell_addr +  4 * (d->hwirq / 32);
+
+	msg->address_lo = lower_32_bits(doorbell);
+	msg->address_hi = upper_32_bits(doorbell);
+	msg->data = d->hwirq % 32;
+}
+
+static struct irq_chip sg2044_msi_middle_irq_chip = {
+	.name			= "SG2044 MSI",
+	.irq_ack		= sg2044_msi_irq_ack,
+	.irq_mask		= irq_chip_mask_parent,
+	.irq_unmask		= irq_chip_unmask_parent,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= irq_chip_set_affinity_parent,
+#endif
+	.irq_compose_msi_msg	= sg2044_msi_irq_compose_msi_msg,
+};
+
  static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq)
  {
-	struct sg2042_msi_chipdata *data = domain->host_data;
+	struct sg204x_msi_chipdata *data = domain->host_data;
  	struct irq_fwspec fwspec;
  	struct irq_data *d;
  	int ret;

@@ -102,7 +146,7 @@ static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsigned in
  static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, unsigned int virq,
  					  unsigned int nr_irqs, void *args)
  {
-	struct sg2042_msi_chipdata *data = domain->host_data;
+	struct sg204x_msi_chipdata *data = domain->host_data;
  	int hwirq, err, i;
 
  	hwirq = sg2042_msi_allocate_hwirq(data, nr_irqs);

@@ -115,7 +159,7 @@ static int sg2042_msi_middle_domain_alloc(struct irq_domain *domain, unsigned in
  			goto err_hwirq;
 
  		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
-					      &sg2042_msi_middle_irq_chip, data);
+					      data->chip_info->irqchip, data);
  	}
 
  	return 0;

@@ -131,7 +175,7 @@ static void sg2042_msi_middle_domain_free(struct irq_domain *domain, unsigned in
  					  unsigned int nr_irqs)
  {
  	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
-	struct sg2042_msi_chipdata *data = irq_data_get_irq_chip_data(d);
+	struct sg204x_msi_chipdata *data = irq_data_get_irq_chip_data(d);
 
  	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
  	sg2042_msi_free_hwirq(data, d->hwirq, nr_irqs);

@@ -157,7 +201,22 @@ static const struct msi_parent_ops sg2042_msi_parent_ops = {
  	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
  };
 
-static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
+#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS |	\
+				   MSI_FLAG_USE_DEF_CHIP_OPS)
+
+#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK |	\
+				    MSI_FLAG_PCI_MSIX)
+
+static const struct msi_parent_ops sg2044_msi_parent_ops = {
+	.required_flags		= SG2044_MSI_FLAGS_REQUIRED,
+	.supported_flags	= SG2044_MSI_FLAGS_SUPPORTED,
+	.bus_select_mask	= MATCH_PCI_MSI,
+	.bus_select_token	= DOMAIN_BUS_NEXUS,
+	.prefix			= "SG2044-",
+	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
+};
+
+static int sg2042_msi_init_domains(struct sg204x_msi_chipdata *data,
  				   struct irq_domain *plic_domain, struct device *dev)
  {
  	struct fwnode_handle *fwnode = dev_fwnode(dev);

@@ -173,7 +232,7 @@ static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
  	irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS);
 
  	middle_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;
-	middle_domain->msi_parent_ops = &sg2042_msi_parent_ops;
+	middle_domain->msi_parent_ops = data->chip_info->parent_ops;
 
  	return 0;
  }

@@ -181,16 +240,22 @@ static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data,
  static int sg2042_msi_probe(struct platform_device *pdev)
  {
  	struct fwnode_reference_args args = { };
-	struct sg2042_msi_chipdata *data;
+	struct sg204x_msi_chipdata *data;
  	struct device *dev = &pdev->dev;
  	struct irq_domain *plic_domain;
  	struct resource *res;
  	int ret;
 
-	data = devm_kzalloc(dev, sizeof(struct sg2042_msi_chipdata), GFP_KERNEL);
+	data = devm_kzalloc(dev, sizeof(struct sg204x_msi_chipdata), GFP_KERNEL);
  	if (!data)
  		return -ENOMEM;
 
+	data->chip_info = device_get_match_data(&pdev->dev);
+	if (!data->chip_info) {
+		dev_err(&pdev->dev, "Failed to get irqchip\n");
+		return -EINVAL;
+	}
+
  	data->reg_clr = devm_platform_ioremap_resource_byname(pdev, "clr");
  	if (IS_ERR(data->reg_clr)) {
  		dev_err(dev, "Failed to map clear register\n");

@@ -231,11 +296,28 @@ static int sg2042_msi_probe(struct platform_device *pdev)
 
  	mutex_init(&data->msi_map_lock);
 
+	data->msi_map = devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERNEL);
+	if (!data->msi_map) {
+		dev_err(&pdev->dev, "Unable to allocate msi mapping\n");
+		return -ENOMEM;
+	}
+
  	return sg2042_msi_init_domains(data, plic_domain, dev);
  }
 
+static const struct sg2042_msi_chip_info sg2042_of_data = {
+	.irqchip	= &sg2042_msi_middle_irq_chip,
+	.parent_ops	= &sg2042_msi_parent_ops,
+};
+
+static const struct sg2042_msi_chip_info sg2044_of_data = {
+	.irqchip	= &sg2044_msi_middle_irq_chip,
+	.parent_ops	= &sg2044_msi_parent_ops,
+};
+
  static const struct of_device_id sg2042_msi_of_match[] = {
-	{ .compatible	= "sophgo,sg2042-msi" },
+	{ .compatible	= "sophgo,sg2042-msi", .data	= &sg2042_of_data },
+	{ .compatible	= "sophgo,sg2044-msi", .data	= &sg2044_of_data },
  	{ }
  };
#5 lore raw
In reply to Inochi Amaoto

Inochi!

Quoted 1 line · Inochi Amaoto

Add support for Sophgo SG2044 MSI interrupt controller.

I asked you in my reply to V1 to split this up into two patches:

"The conversion of the existing code to this should be a preparatory patch
for ease of review and the support for the new chip built on top."

And yet you come back with a patch doing both things at once. Feel free to ignore me...

Thanks,

tglx

author maintainer
#6 lore raw
Quoted 5 lines · Thomas Gleixner

Inochi!

Quoted 1 line · Inochi Amaoto

Add support for Sophgo SG2044 MSI interrupt controller.

Quoted 8 lines

I asked you in my reply to V1 to split this up into two patches:

"The conversion of the existing code to this should be a preparatory patch
for ease of review and the support for the new chip built on top."

And yet you come back with a patch doing both things at once. Feel free to ignore me...

Sorry for miss this. I will separate this thing in the next version.

Regards,
Inochi