Add SiFive Private L2 cache and PMU driver
Subsystems (6)
v2 cover Add SiFive Private L2 cache and PMU driver
This patch series adds the SiFive Private L2 cache controller driver and Performance Monitoring Unit (PMU) driver.
The Private L2 cache communicates with both the upstream L1 caches and downstream L3 cache or memory, enabling a high- performance cache subsystem. It is also responsible for managing requests from the L1 instruction and data caches of the core.
The Private L2 Performance Monitoring Unit (PMU) consists of a set of event-programmable counters and their event selector registers. The registers are available to control the behavior of the counters.
Changes since v1:
- Rebased on Linux-6.5-rc2
- Change pl2 cache compatible string to lowercase
- Add cpuhp_remove_state() after pl2 cache driver probe fail
- Return 0 instead of return ret at the end of sifive_pl2_cache_init()
- Cut down the pl2 cache config log lines in pl2_config_read()
- Sorting the variable by types in sifive_pl2_cache_dev_probe()
- Change the error message when failing to find the CPU node
- Add pl2 PMU driver to support per-task profile
- Move the pl2 PMU driver implementation to the drivers/perf folder
- Keep only one pl2 cache compatible string suggested by Krzysztof and Conor
- Addressed Krzysztof's and Conor's comments on DT binding
Eric Lin (2):
dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
soc: sifive: Add SiFive private L2 cache driver
Greentime Hu (1):
soc: sifive: Add SiFive private L2 cache PMU driver
.../bindings/cache/sifive,pl2cache.yaml | 62 ++ drivers/perf/Kconfig | 10 + drivers/perf/Makefile | 1 + drivers/perf/sifive_pl2_pmu.c | 602 ++++++++++++++++++ drivers/soc/sifive/Kconfig | 8 + drivers/soc/sifive/Makefile | 1 + drivers/soc/sifive/sifive_pl2.h | 29 + drivers/soc/sifive/sifive_pl2_cache.c | 202 ++++++ include/linux/cpuhotplug.h | 1 + 9 files changed, 916 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml create mode 100644 drivers/perf/sifive_pl2_pmu.c create mode 100644 drivers/soc/sifive/sifive_pl2.h create mode 100644 drivers/soc/sifive/sifive_pl2_cache.c
Signature · 1 line
2.40.1
PATCH v2 1/3 dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
This add YAML DT binding documentation for SiFive Private L2 cache controller
--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +62 -0
@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <[email protected]> + - Eric Lin <[email protected]> + +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1","cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>; + next-level-cache = <&L4>; + };
Signature · 1 line
2.40.1
Rob Herring
maintainerRe: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 11 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: 'interrupts', 'memory-region' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Hi Rob,
Quoted 197 lines · Rob Herring
Quoted 11 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yamlMy bot found errors running 'make DT_CHECKER_FLAGS=-m
dt_binding_check' on your patch (DT_CHECKER_FLAGSis new in v5.13):yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cache/sifive,ccache0.example.dtb: cache-controller@2010000: 'interrupts', 'memory-region' do not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.example.dtb: l3-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'l3-cache' does not match any of the regexes: 'pinctrl-[0-9]+'
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l3-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible:0: 'sifive,pl2cache1' was expected
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: compatible: ['cache'] is too short
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-block-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-sets' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'cache-size' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.example.dtb: l2-cache: 'reg' is a required property
from schema $id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml#doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make
dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
Quoted 6 lines
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that
DT_SCHEMA_FILEScan be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Sorry for the errors. I forgot to run make dt_binding_check. I'll fix it in the next version. Thanks for the review.
Best regards,
Eric Lin
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Conor Dooley
maintainerRe: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
In reply to Eric LinHey Eric,
Quoted 8 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++
btw, your $subject should be "dt-bindings: cache: ...." rather than "riscv: sifive".
Quoted 11 lines
1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yamlDocumentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +2
-0@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <[email protected]> + - Eric Lin <[email protected]>
There's extra spaces in these lines for some reason.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+ +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# +
I'm pretty sure that I pointed out last time around that you need to add something like in the ccache driver:
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccache
otherwise this binding will be used for anything containing "cache" in the dt-binding.
For this binding, I think that the following is sufficient:
select:
properties:
compatible:
contains:
const: sifive,pl2cache1
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 27
Quoted 5 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache
You omitted the pl2cache0 from here, that needs to come back! You'll end up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible, per sifive-blocks-ip-versioning.txt..
Thanks,
Conor.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 78 lines · Conor Dooley
Hey Eric,
Quoted 8 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++btw, your $subject should be "dt-bindings: cache: ...." rather than "riscv: sifive".
Quoted 11 lines
1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yamlDocumentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +2
-0@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc.Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <[email protected]> + - Eric Lin <[email protected]>There's extra spaces in these lines for some reason.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+ +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# +I'm pretty sure that I pointed out last time around that you need to add something like in the ccache driver:
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccacheotherwise this binding will be used for anything containing "cache" in the dt-binding.
For this binding, I think that the following is sufficient:select:
properties:
compatible:
contains:
const: sifive,pl2cache1Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 27
Quoted 5 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache
Quoted 4 lines
You omitted the pl2cache0 from here, that needs to come back! You'll end up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible, per sifive-blocks-ip-versioning.txt..
Further, "sifive,perfmon-counters" is an undocumented property.
Thanks,
Conor.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Hi Conor,
Quoted 14 lines · Conor Dooley
Quoted 12 lines · Conor Dooley
Hey Eric,
Quoted 8 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++
Quoted 3 lines
Quoted 3 lines
btw, your $subject should be "dt-bindings: cache: ...." rather than "riscv: sifive".
OK, I'll fix it in v3.
Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yamlDocumentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +7
-0@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 12
Quoted 5 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <[email protected]> + - Eric Lin <[email protected]>There's extra spaces in these lines for some reason.
OK, I'll fix it in v3.
Quoted 27 lines
Quoted 27 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+ +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# +I'm pretty sure that I pointed out last time around that you need to add something like in the ccache driver:
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccacheotherwise this binding will be used for anything containing "cache" in the dt-binding.
For this binding, I think that the following is sufficient:
Quoted 6 lines
Quoted 6 lines
select:
properties:
compatible:
contains:
const: sifive,pl2cache1
Sorry, I misunderstood your meaning.
To be honest, I'm not quite familiar with the usage of the select property. When should we use the select property?
May I ask, is there a document to detail introduce each property and its usage like the device-tree spec?
I think it would be very helpful for beginners writing correct dt-binding and it can save much reviewers time.
Thanks for your kind explanation, I'll fix it in v3.
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 27
Quoted 5 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cacheYou omitted the pl2cache0 from here, that needs to come back! You'll end up with 2 items entries.
OK, it should be as follows, right?
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: sifive,pl2cache0 + - const: sifive,pl2cache1 + - const: cache
+ - items:
+ - const: sifive,pl2cache1
+ - const: cache
I'll fix it in v3. Thanks.
Quoted 5 lines
Quoted 2 lines
Either way, I can't take this binding without a soc-specific compatible, per sifive-blocks-ip-versioning.txt..
Further, "sifive,perfmon-counters" is an undocumented property.
OK, I'll add "sifive,perfmon-counters" property in v3. Thanks for your kind review.
Best regards,
Eric Lin
Quoted 2 lines
Thanks,
Conor.
_______________________________________________
linux-riscv mailing list
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http://lists.infradead.org/mailman/listinfo/linux-riscv
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 37 lines · Eric Lin
Quoted 29 lines · Conor Dooley
Quoted 28 lines · Conor Dooley
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 22
Quoted 9 lines · Eric Lin
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +9
-0+description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# +I'm pretty sure that I pointed out last time around that you need to add something like in the ccache driver:
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccacheotherwise this binding will be used for anything containing "cache" in the dt-binding.
For this binding, I think that the following is sufficient:Quoted 6 lines
Quoted 6 lines
select:
properties:
compatible:
contains:
const: sifive,pl2cache1
Quoted 7 lines
Sorry, I misunderstood your meaning.
To be honest, I'm not quite familiar with the usage of the select property. When should we use the select property?
May I ask, is there a document to detail introduce each property and its usage like the device-tree spec?
I think it would be very helpful for beginners writing correct dt-binding and it can save much reviewers time.
You need this select because otherwise this binding will match against every other user of "cache" in the tree. It's explained here:
https://docs.kernel.org/devicetree/bindings/writing-schema.html
Thanks,
Conor.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
In reply to Conor DooleyHi Conor and Krzysztof,
Quoted 79 lines · Conor Dooley
Hey Eric,
Quoted 8 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>--- .../bindings/cache/sifive,pl2cache.yaml | 62 +++++++++++++++++++btw, your $subject should be "dt-bindings: cache: ...." rather than "riscv: sifive".
Quoted 11 lines
1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/sifive,pl2cache.yamlDocumentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +2
-0@@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2023 SiFive, Inc.Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/sifive,pl2cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Private L2 Cache Controller + +maintainers: + - Greentime Hu <[email protected]> + - Eric Lin <[email protected]>There's extra spaces in these lines for some reason.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+ +description: + The SiFive Private L2 Cache Controller is per core and + communicates with both the upstream L1 caches and + downstream L3 cache or memory, enabling a high-performance + cache subsystem. + +allOf: + - $ref: /schemas/cache-controller.yaml# +I'm pretty sure that I pointed out last time around that you need to add something like in the ccache driver:
select:
properties:
compatible:
contains:
enum:
- sifive,ccache0
- sifive,fu540-c000-ccache
- sifive,fu740-c000-ccacheotherwise this binding will be used for anything containing "cache" in the dt-binding.
For this binding, I think that the following is sufficient:select:
properties:
compatible:
contains:
const: sifive,pl2cache1Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 27
Quoted 5 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache
Quoted 5 lines
You omitted the pl2cache0 from here, that needs to come back! You'll end up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible, per sifive-blocks-ip-versioning.txt..
Sorry for the late reply.
OK, I will wait until the customer's SoC tape-out before upstreaming the PL2 cache and PMU drivers.
Thank you for your review.
Best regards,
Eric Lin
Quoted 2 lines
Thanks,
Conor.
_______________________________________________
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Conor Dooley
maintainerRe: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
In reply to Conor DooleyQuoted 8 lines · Conor Dooley
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 27
Quoted 5 lines · Eric Lin
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +5
-0+properties: + compatible: + items: + - const: sifive,pl2cache1 + - const: cache
Quoted 4 lines
You omitted the pl2cache0 from here, that needs to come back! You'll end up with 2 items entries.
Either way, I can't take this binding without a soc-specific compatible, per sifive-blocks-ip-versioning.txt..
On this last point, what Nick Hu has done for the clint2 would be acceptable, adding a {} entry to disallow the compatible in isolation without requiring a soc-specific compatible for hardware that does not yet exist:
https://lore.kernel.org/all/[email protected]/
Maybe that'll allow you to submit a v3 of this work?
Cheers,
Conor
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
In reply to Eric LinQuoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>
...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Quoted 18 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +18
-0+ - const: cache + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 54
Quoted 10 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +10
-0+ - cache-size + - cache-unified + - reg + +additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1","cache";
Missing space.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 60
Quoted 6 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +6
-0+ cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>;
reg is after compatible.
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 62
Quoted 2 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +2
-0+ next-level-cache = <&L4>; + };
Best regards,
Krzysztof
_______________________________________________
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[email protected]
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Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1
Quoted 5 lines
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC. The pl2cache1 is utilized in our internal FPGA platform for evaluation; it's our core IP.
Quoted 24 lines
Quoted 24 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +22
-0+ - const: cache + + cache-block-size: true + cache-level: true + cache-sets: true + cache-size: true + cache-unified: true + + reg: + maxItems: 1 + + next-level-cache: true + +required: + - compatible + - cache-block-size + - cache-level + - cache-sets + - cache-size + - cache-unified + - reg +
Quoted 8 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 54
Quoted 6 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +6
-0+additionalProperties: false + +examples: + - | + cache-controller@10104000 { + compatible = "sifive,pl2cache1","cache";Missing space.
OK, I'll fix it in the next version.
Quoted 9 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 60
Quoted 7 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +6
-0+ cache-block-size = <64>; + cache-level = <2>; + cache-sets = <512>; + cache-size = <262144>; + cache-unified; + reg = <0x10104000 0x4000>;reg is after compatible.
OK, I'll fix it in the next version.
Thanks for your review.
Best regards,
Eric Lin
Quoted 7 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 62
Quoted 3 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +2
-0+ next-level-cache = <&L4>; + };Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 27 lines · Eric Lin
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1Quoted 5 lines
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Quoted 3 lines
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC.
Wait a second, does the fu740 on the unmatched not have a ccache as it's L2 cache?
Quoted 3 lines
The pl2cache1 is
utilized in our internal FPGA platform for evaluation; it's our core IP.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 29 lines · Conor Dooley
Quoted 27 lines · Eric Lin
Hi Krzysztof,
Quoted 22 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Quoted 7 lines
Quoted 3 lines
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC.
Wait a second, does the fu740 on the unmatched not have a ccache as it's L2 cache?
Hi Conor,
Sorry, I misremember the L2 cache on the unmatched board. I just check again. The unmatched board L2 cache is ccache not pl2cache0. You are right. Thanks.
Best regards,
Eric Lin
Quoted 3 lines
Quoted 3 lines
The pl2cache1 is
utilized in our internal FPGA platform for evaluation; it's our core IP.
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
In reply to Eric LinQuoted 27 lines · Eric Lin
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1Quoted 5 lines
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Quoted 5 lines
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC. The pl2cache1 is utilized in our internal FPGA platform for evaluation; it's our core IP.
And why do you add bindings for some internal FPGA IP block which does not interface with any SW?
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 29 lines · Krzysztof Kozlowski
Quoted 27 lines · Eric Lin
Hi Krzysztof,
Quoted 22 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?
Quoted 9 lines
Quoted 5 lines
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC. The pl2cache1 is utilized in our internal FPGA platform for evaluation; it's our core IP.
And why do you add bindings for some internal FPGA IP block which does not interface with any SW?
Hi Krzysztof,
The pl2cache has mmio interface for SW. Thanks.
Best regards,
Eric Lin
Quoted 3 lines
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 37 lines · Eric Lin
Quoted 35 lines · Krzysztof Kozlowski
Quoted 32 lines · Eric Lin
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1Quoted 5 lines
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC. The pl2cache1 is utilized in our internal FPGA platform for evaluation; it's our core IP.
Quoted 6 lines
Quoted 3 lines
And why do you add bindings for some internal FPGA IP block which does not interface with any SW?
Hi Krzysztof,
The pl2cache has mmio interface for SW. Thanks.
Then did you mean that FPGA represented some model of your SoC? If so, what are other bindings for that FPGA components?
Best regards,
Krzysztof
Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Quoted 43 lines · Krzysztof Kozlowski
Quoted 41 lines · Eric Lin
Quoted 38 lines · Krzysztof Kozlowski
Quoted 27 lines · Eric Lin
Hi Krzysztof,
Quoted 17 lines · Krzysztof Kozlowski
Quoted 6 lines · Eric Lin
This add YAML DT binding documentation for SiFive Private L2 cache controller
Signed-off-by Eric Lin <[email protected]>Reviewed-by Zong Li <[email protected]>Reviewed-by Nick Hu <[email protected]>...
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml line 26
Quoted 4 lines
Documentation/devicetree/bindings/cache/sifive,pl2cache.yaml new file +4
-0+properties: + compatible: + items: + - const: sifive,pl2cache1Quoted 5 lines
I still have doubts that it is not used in any SoC. This is what you said last time: "is not part of any SoC."
If not part of any SoC, then where is it? Why are you adding it to the kernel?Quoted 5 lines
Sorry for the late reply. I didn't describe it clearly last time. Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1. The pl2cache0 is used in unmatched board SoC. The pl2cache1 is utilized in our internal FPGA platform for evaluation; it's our core IP.
And why do you add bindings for some internal FPGA IP block which does not interface with any SW?
Quoted 6 lines
Quoted 2 lines
Hi Krzysztof,
The pl2cache has mmio interface for SW. Thanks.Then did you mean that FPGA represented some model of your SoC? If so, what are other bindings for that FPGA components?
Hi Krzysztof,
Sorry for the late reply.
Yes, here are the devices dt-binding that we use on the internal FPGA SoC platform. Thanks.
uart:Documentation/devicetree/bindings/serial/sifive-serial.yaml
gpio:Documentation/devicetree/bindings/gpio/sifive,gpio.yaml
dma:Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
spi:Documentation/devicetree/bindings/spi/spi-sifive.yaml
Best regards,
Eric Lin
Quoted 3 lines
Best regards,
Krzysztof
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PATCH v2 2/3 soc: sifive: Add SiFive private L2 cache driver
In reply to Eric LinThis adds SiFive private L2 cache driver which will show cache config information when booting and add cpu hotplug callback functions.
--- drivers/soc/sifive/Kconfig | 8 ++ drivers/soc/sifive/Makefile | 1 + drivers/soc/sifive/sifive_pl2.h | 27 ++++ drivers/soc/sifive/sifive_pl2_cache.c | 194 ++++++++++++++++++++++++++ include/linux/cpuhotplug.h | 1 + 5 files changed, 231 insertions(+) create mode 100644 drivers/soc/sifive/sifive_pl2.h create mode 100644 drivers/soc/sifive/sifive_pl2_cache.c
drivers/soc/sifive/Kconfig +8 -0
@@ -7,4 +7,12 @@ config SIFIVE_CCACHE help Support for the composable cache controller on SiFive platforms. +config SIFIVE_PL2 + bool "Sifive private L2 Cache controller" + help + Support for the private L2 cache controller on SiFive platforms. + The SiFive Private L2 Cache Controller is per hart and communicates + with both the upstream L1 caches and downstream L3 cache or memory, + enabling a high-performance cache subsystem. + endif
drivers/soc/sifive/Makefile +1 -0
@@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o +obj-$(CONFIG_SIFIVE_PL2) += sifive_pl2_cache.o
drivers/soc/sifive/sifive_pl2.h new file +27 -0
@@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (C) 2023 SiFive, Inc. +* +*/ + +#ifndef _SIFIVE_PL2_H +#define _SIFIVE_PL2_H + +#define SIFIVE_PL2_CONFIG1_OFFSET 0x1000 +#define SIFIVE_PL2_CONFIG0_OFFSET 0x1008 +#define SIFIVE_PL2_PMCLIENT_OFFSET 0x2800 + +#define SIFIVE_PL2CACHE_CONFIG 0x00 +#define SIFIVE_PL2CACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_PL2CACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_PL2CACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_PL2CACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + +struct sifive_pl2_state { +void __iomem *pl2_base; +u32 config1; +u64 config0; +u64 pmclientfilter; +}; + +#endif /*_SIFIVE_PL2_H */
drivers/soc/sifive/sifive_pl2_cache.c new file +194 -0
194 lines not on this page · raw message
include/linux/cpuhotplug.h +1 -0
@@ -209,6 +209,7 @@ enum cpuhp_state {CPUHP_AP_IRQ_AFFINITY_ONLINE ,CPUHP_AP_BLK_MQ_ONLINE ,CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS , +CPUHP_AP_RISCV_SIFIVE_PL2_ONLINE ,CPUHP_AP_X86_INTEL_EPB_ONLINE ,CPUHP_AP_PERF_ONLINE , CPUHP_AP_PERF_X86_ONLINE,
Signature · 1 line
2.40.1
Re: [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver
Hey,
Quoted 10 lines · Eric Lin
This adds SiFive private L2 cache driver which will show cache config information when booting and add cpu hotplug callback functions.
Signed-off-by Eric Lin <[email protected]>Co-developed-by Nick Hu <[email protected]>Signed-off-by Nick Hu <[email protected]>Reviewed-by Zong Li <[email protected]>+static void
pl2_config_read(void __iomem *pl2_base, int cpu)
This function's prefix does not match the rest of the driver.
drivers/soc/sifive/sifive_pl2_cache.c line 121
Quoted 11 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +11
-0+{ +u32 cfg, banks, ways, cacheline, sets; + + cfg =readl (pl2_base +SIFIVE_PL2CACHE_CONFIG ); + banks =FIELD_GET (SIFIVE_PL2CACHE_CONFIG_BANK_MASK , cfg); + ways =FIELD_GET (SIFIVE_PL2CACHE_CONFIG_WAYS_MASK , cfg); + cacheline =FIELD_GET (SIFIVE_PL2CACHE_CONFIG_BLKS_MASK , cfg); + sets =FIELD_GET (SIFIVE_PL2CACHE_CONFIG_SETS_MASK , cfg); +pr_info ("%u banks, ways/bank=%u, bytes/block=%llu, sets:%llu, size:%d for CPU:%d\n" , + banks, ways,BIT_ULL (cacheline),BIT_ULL (sets), ways << (sets + cacheline), cpu); +}
My OCD quite dislikes how the formatting here is not consistent. "%u banks"
"ways/bank=%u"
"sets:%llu"
Could you please do me a favour and pick just one style here?
drivers/soc/sifive/sifive_pl2_cache.c line 131
Quoted 10 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +10
-0+ +static int sifive_pl2_cache_dev_probe (struct platform_device *pdev) +{ +struct device_node *cpu_node, *pl2_node; +struct sifive_pl2_state *pl2_state =NULL ; +struct resource *res; +void __iomem *pl2_base; +int cpu; + +/* Traverse all cpu nodes to find the one mapping to its pl2 node. */
While comments like this are somewhat useful...
Quoted 8 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +8
-0+for_each_cpu (cpu, cpu_possible_mask) { + cpu_node =of_cpu_device_node_get (cpu); + pl2_node =of_parse_phandle (cpu_node,"next-level-cache" ,0 ); + +/* Found it! */ +if (dev_of_node (&pdev->dev) == pl2_node) { +/* Use cpu to get its percpu data sifive_pl2_state. */ + pl2_state =per_cpu_ptr (&sifive_pl2_state, cpu);
drivers/soc/sifive/sifive_pl2_cache.c line 149
Quoted 10 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +10
-0+break ; + } + } + +if (!pl2_state) { +pr_err ("Failed to find CPU node for %s.\n" , pdev->name); +return -EINVAL ; + } + +/* Set base address of select and counter registers. */
...something like this just restates what this function always does. It's the same in some other places, with things like:
/* save the state */ save_state();
Could you drop the ones that restate the obvious please?
Quoted 10 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +10
-0+ pl2_base =devm_platform_get_and_ioremap_resource (pdev,0 , &res); +if (IS_ERR (pl2_base)) +return PTR_ERR (pl2_base); + +/* Print pL2 configs. */ +pl2_config_read (pl2_base, cpu); + pl2_state->pl2_base = pl2_base; + +return 0 ; +}
drivers/soc/sifive/sifive_pl2_cache.c line 169
Quoted 10 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +10
-0+ +static struct platform_driver sifive_pl2_cache_driver = { + .driver = { + .name ="SiFive-pL2-cache" , + .of_match_table = sifive_pl2_cache_of_ids, + }, + .probe = sifive_pl2_cache_dev_probe, +}; + +static int __init sifive_pl2_cache_init (void )
Why is the split between initcall and normal probe function required? Does the hotplug stuff require that?
Quoted 13 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +13
-0+{ +int ret; + + ret =cpuhp_setup_state (CPUHP_AP_RISCV_SIFIVE_PL2_ONLINE , +"soc/sifive/pl2:online" , + sifive_pl2_online_cpu, + sifive_pl2_offline_cpu); +if (ret <0 ) { +pr_err ("Failed to register CPU hotplug notifier %d\n" , ret); +return ret; + } + + ret =platform_driver_register (&sifive_pl2_cache_driver);
drivers/soc/sifive/sifive_pl2_cache.c line 192
Quoted 10 lines
drivers/soc/sifive/sifive_pl2_cache.c new file +10
-0+if (ret) { +pr_err ("Failed to register sifive_pl2_cache_driver: %d\n" , ret); +cpuhp_remove_state (CPUHP_AP_RISCV_SIFIVE_PL2_ONLINE ); +return ret; + } + +sifive_pl2_pm_init (); + +return 0 ; +}
Cheers,
Conor.
PATCH v2 3/3 soc: sifive: Add SiFive private L2 cache PMU driver
In reply to Eric LinFrom: Greentime Hu <[email protected]>
The SiFive private L2 cache PMU is per-core and supports per-task profiling and event counting. Users can use the perf tool to profile by event name and event id. Example:
$ perf stat -C 0 -e /sifive_pl2_pmu/inner_acquire_block_btot/
-e /sifive_pl2_pmu/inner_acquire_block_ntob/
-e /sifive_pl2_pmu/inner_acquire_block_ntot/ lsPerformance counter stats for 'CPU(s) 0':
300 sifive_pl2_pmu/inner_acquire_block_btot/
17801 sifive_pl2_pmu/inner_acquire_block_ntob/
5253 sifive_pl2_pmu/inner_acquire_block_ntot/0.088917326 seconds time elapsed
$ perf stat -C 0 -e /sifive_pl2_pmu/event=0x10001/
-e /sifive_pl2_pmu/event=0x4001/
-e /sifive_pl2_pmu/event=0x8001/ lsPerformance counter stats for 'CPU(s) 0':
251 sifive_pl2_pmu/event=0x10001/
2620 sifive_pl2_pmu/event=0x4001/
644 sifive_pl2_pmu/event=0x8001/0.092827110 seconds time elapsed
--- drivers/perf/Kconfig | 10 + drivers/perf/Makefile | 1 + drivers/perf/sifive_pl2_pmu.c | 602 ++++++++++++++++++++++++++ drivers/soc/sifive/sifive_pl2.h | 2 + drivers/soc/sifive/sifive_pl2_cache.c | 10 +- 5 files changed, 624 insertions(+), 1 deletion(-) create mode 100644 drivers/perf/sifive_pl2_pmu.c
drivers/perf/Kconfig +10 -0
@@ -234,4 +234,14 @@ config CXL_PMU If unsure say 'm'. +config SIFIVE_PL2_PMU + bool "Sifive private L2 Cache PMU" + depends on SIFIVE_PL2 && PERF_EVENTS + default y + help + Support for the private L2 cache controller performance monitor unit + (PMU) on SiFive platforms. The SiFive private L2 PMU can monitor the + each hart L2 cache performance and it consists of a set of event + programmable counters and their event selector registers. + endmenu
drivers/perf/Makefile +1 -0
@@ -26,3 +26,4 @@ obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) += alibaba_uncore_drw_pmu.o obj-$(CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU) += arm_cspmu/ obj-$(CONFIG_MESON_DDR_PMU) += amlogic/ obj-$(CONFIG_CXL_PMU) += cxl_pmu.o +obj-$(CONFIG_SIFIVE_PL2_PMU) += sifive_pl2_pmu.o
drivers/perf/sifive_pl2_pmu.c new file +602 -0
602 lines not on this page · raw message
drivers/soc/sifive/sifive_pl2.h +2 -0
@@ -24,4 +24,6 @@ struct sifive_pl2_state { u64 pmclientfilter; }; +int sifive_pl2_pmu_probe (struct device_node *pl2_node, +void __iomem *pl2_base,int cpu);#endif /*_SIFIVE_PL2_H */
drivers/soc/sifive/sifive_pl2_cache.c +9 -1
@@ -126,7 +126,7 @@ static int sifive_pl2_cache_dev_probe(struct platform_device *pdev)struct sifive_pl2_state *pl2_state =NULL ;struct resource *res;void __iomem *pl2_base; -int cpu; +int cpu, ret;/* Traverse all cpu nodes to find the one mapping to its pl2 node. */ for_each_cpu (cpu, cpu_possible_mask) {
@@ -155,6 +155,14 @@ static int sifive_pl2_cache_dev_probe(struct platform_device *pdev)pl2_config_read (pl2_base, cpu); pl2_state->pl2_base = pl2_base; +if (IS_ENABLED (CONFIG_SIFIVE_PL2_PMU )) { + ret =sifive_pl2_pmu_probe (pl2_node, pl2_base, cpu); +if (ret) { +pr_err ("Failed to probe sifive_pl2_pmu driver.\n" ); +return -EINVAL ; + } + } +return 0 ; }
Signature · 7 lines
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