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arm64: dts: qcom: sm8650: add the missing l2 cache node

PATCH Applied Pengyu Luo 4 participants 4 messages Apr 5, 2025 – May 14, 2025

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Pengyu Luo

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#0 lore raw

PATCH 1/1 arm64: dts: qcom: sm8650: add the missing l2 cache node

Only two little a520s share the same L2, every a720 has their own L2 cache.

Fixes d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by Pengyu Luo <[email protected]>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/sm8650.dtsi +8 -1
index a2b3d97ab..f47f29ec8 100644
@@ -187,7 +187,7 @@ cpu3: cpu@300 {
 			power-domain-names = "psci";
 
 			enable-method = "psci";
-			next-level-cache = <&l2_200>;
+			next-level-cache = <&l2_300>;
 			capacity-dmips-mhz = <1792>;
 			dynamic-power-coefficient = <238>;
 

@@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
 					 &epss_l3 SLAVE_EPSS_L3_SHARED>;
 
 			#cooling-cells = <2>;
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
 		};
 
 		cpu4: cpu@400 {
Signature · 1 line
2.49.0
Reviewed-by on v1 1/1
#1 lore raw
Quoted 26 lines · Pengyu Luo

Only two little a520s share the same L2, every a720 has their own L2 cache.

Fixes d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by Pengyu Luo <[email protected]>
---
  arch/arm64/boot/dts/qcom/sm8650.dtsi | 9 ++++++++-
  1 file changed, 8 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/qcom/sm8650.dtsi +1 -1
index a2b3d97ab..f47f29ec8 100644
@@ -187,7 +187,7 @@ cpu3: cpu@300 {
  			power-domain-names = "psci";
 
  			enable-method = "psci";
-			next-level-cache = <&l2_200>;
+			next-level-cache = <&l2_300>;
  			capacity-dmips-mhz = <1792>;
  			dynamic-power-coefficient = <238>;
 

@@ -203,6 +203,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
  					 &epss_l3 SLAVE_EPSS_L3_SHARED>;
 
  			#cooling-cells = <2>;

arch/arm64/boot/dts/qcom/sm8650.dtsi &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, · line 215

Quoted 10 lines
arch/arm64/boot/dts/qcom/sm8650.dtsi +7 -0
+
+			l2_300: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&l3_0>;
+			};
  		};
 
  		cpu4: cpu@400 {
Reviewed-by Neil Armstrong <[email protected]>
maintainer Applied
#3 lore raw
In reply to Pengyu Luo
Quoted 4 lines · Pengyu Luo

Only two little a520s share the same L2, every a720 has their own L2 cache.

Applied, thanks!

[1/1] arm64: dts: qcom: sm8650: add the missing l2 cache node

      commit: 4becd72352b6861de0c24074a8502ca85080fd63

Best regards,

Signature · 1 line
Bjorn Andersson <[email protected]>