DC Patches May 05 2025
Subsystems (5)
cover DC Patches May 05 2025
This DC patchset brings improvements in multiple areas. In summary, we highlight:
- Update IPS checks to properly include all ASICs.
- Refactoring DSC enum dsc_bits_per_comp
- Remove redundant NULL check
- Revert "Refactor SubVP cursor limiting logic"
- Disable DPP RCG before DPP CLK enable
- Add skip rIOMMU dc config option
- Fix race condition in DPIA AUX transfer
- Refactor SubVP cursor limiting logic
Cc Daniel Wheeler <[email protected]>
Alex Hung (2):
drm/amd/display: Remove redundant null check drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
Aurabindo Pillai (1):
drm/amd/display: more liberal vmin/vmax update for freesync
Austin Zheng (2):
drm/amd/display: Call FP Protect Before Mode Programming/Mode Support drm/amd/display: DML21 Fixes
Bhuvanachandra Pinninti (1):
drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.
Charlene Liu (2):
drm/amd/display: allow dscclk disable drm/amd/display: disable DPP RCG before DPP CLK enable
Dillon Varone (2):
drm/amd/display: Refactor SubVP cursor limiting logic drm/amd/display: Only wait for required free space in DMUB mailbox
Dominik Kaszewski (1):
drm/amd/display: Prepare for Fused I2C-over-AUX
Jesse Agate (1):
drm/amd/display: Always Scale Flag
JinZe Xu (1):
drm/amd/display: Send IPSExit unconditionally.
Kevin Gao (1):
drm/amd/display: Add skip rIOMMU dc config option
Leo Li (1):
drm/amd/display: Allow 0 dtbclk for DCN35 and above
Meenakshikumar Somasundaram (1):
drm/amd/display: Assign preferred stream encoder instance to dpia
Nicholas Kazlauskas (1):
Revert "drm/amd/display: turn off eDP lcdvdd and backlight if not
required"
Ovidiu Bunea (1):
drm/amd/display: Update IPS sequential_ono requirement checks
Roman Li (1):
drm/amd/display: Fix invalid context error in dml helper
Ryan Seto (1):
Revert "drm/amd/display: Refactor SubVP cursor limiting logic"
Taimur Hassan (3):
drm/amd/display: Promote DAL to 3.2.330
drm/amd/display: [FW Promotion] Release 0.1.8.0
drm/amd/display: Promote DAL to 3.2.331
Wayne Lin (5):
drm/amd/display: Shift DMUB AUX reply command if necessary drm/amd/display: Fix the checking condition in dmub aux handling drm/amd/display: Remove incorrect checking in dmub aux handler drm/amd/display: Copy AUX read reply data whenever length > 0 drm/amd/display: Fix wrong handling for AUX_DEFER case
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 +++++----- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 28 ++++++- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +- .../gpu/drm/amd/display/dc/core/dc_state.c | 15 +++- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 17 ++-- drivers/gpu/drm/amd/display/dc/dc_fused_io.c | 12 ++- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 62 ++++++++------ .../amd/display/dc/dml2/dml21/dml21_wrapper.c | 8 +- .../amd/display/dc/dml2/dml21/inc/dml_top.h | 1 - .../dml21/inc/dml_top_soc_parameter_types.h | 1 + .../display/dc/dml2/dml21/inc/dml_top_types.h | 10 ++- .../src/dml2_core/dml2_core_dcn4_calcs.c | 7 +- .../src/dml2_core/dml2_core_shared_types.h | 82 ++++++++++++++++++- .../dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 3 - .../src/inc/dml2_internal_shared_types.h | 10 ++- .../display/dc/dml2/dml2_translation_helper.c | 14 ++-- .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 2 +- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 7 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 6 ++ .../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 6 -- .../display/dc/hubbub/dcn21/dcn21_hubbub.c | 6 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 21 +++-- .../gpu/drm/amd/display/dc/inc/core_types.h | 1 - .../link/protocols/link_edp_panel_control.c | 2 - .../dc/resource/dcn10/dcn10_resource.c | 4 + .../dc/resource/dcn32/dcn32_resource.c | 7 +- .../dc/resource/dcn321/dcn321_resource.c | 1 + .../dc/resource/dcn35/dcn35_resource.c | 2 +- .../dc/resource/dcn36/dcn36_resource.c | 2 +- .../dc/resource/dcn401/dcn401_resource.c | 3 +- drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 25 +++--- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++++ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 24 ++++-- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 72 ++++++++++++---- 35 files changed, 372 insertions(+), 165 deletions(-)
Signature · 1 line
2.43.0
PATCH 1/28 drm/amd/display: Update IPS sequential_ono requirement checks
From: Ovidiu Bunea <[email protected]>
[why & how]
ASICs that require special RCG/PG programming are determined based on hw_internal_rev. Update these checks to properly include all such ASICs.
Reviewed-by Nicholas Kazlauskas <[email protected]>
Signed-off-by Ovidiu Bunea <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c +1 -1
@@ -138,7 +138,7 @@ bool dpp35_construct( dpp->base.funcs = &dcn35_dpp_funcs;// w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs -if (dpp->base.ctx->asic_id.hw_internal_rev <=0x10 ) +if (dpp->base.ctx->asic_id.hw_internal_rev <0x40 ) dpp->dispclk_r_gate_disable = true;return ret; }
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +1 -1
@@ -1903,7 +1903,7 @@ static bool dcn35_resource_construct( dc->caps.max_disp_clock_khz_at_vmin =650000 ;/* Sequential ONO is based on ASIC. */ -if (dc->ctx->asic_id.hw_internal_rev >0x10 ) +if (dc->ctx->asic_id.hw_internal_rev >=0x40 ) dc->caps.sequential_ono = true;/* Use pipe context based otg sync logic */
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +1 -1
@@ -1876,7 +1876,7 @@ static bool dcn36_resource_construct( dc->caps.max_disp_clock_khz_at_vmin =650000 ;/* Sequential ONO is based on ASIC. */ -if (dc->ctx->asic_id.hw_internal_rev >0x10 ) +if (dc->ctx->asic_id.hw_internal_rev >=0x40 ) dc->caps.sequential_ono = true;/* Use pipe context based otg sync logic */
Signature · 1 line
2.43.0
PATCH 2/28 drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.
In reply to Ray WuFrom: Bhuvanachandra Pinninti <[email protected]>
[Why]
Previously the 'dsc_bits_per_comp' enumeration was defined in individual .c files, making it unavailable for other files that may need it.
[How]
The 'dsc_bits_per_comp' enumeration has been relocated to a common header file.
Reviewed-by Mounika Adhuri <[email protected]>
Reviewed-by Martin Leung <[email protected]>
Signed-off-by Bhuvanachandra Pinninti <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 7 ------- drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 6 ++++++ drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c | 6 ------ 3 files changed, 6 insertions(+), 13 deletions(-)
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +0 -7
@@ -57,13 +57,6 @@ static const struct dsc_funcs dcn20_dsc_funcs = {#define DC_LOGGER \ dsc->ctx->logger -enum dsc_bits_per_comp { -DSC_BPC_8 =8 , -DSC_BPC_10 =10 , -DSC_BPC_12 =12 , -DSC_BPC_UNKNOWN -}; -/* API functions (external or via structure->function_pointer) */ void dsc2_construct(struct dcn20_dsc *dsc,
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +6 -0
@@ -457,6 +457,12 @@type DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING ; \ type DSCRM_DSC_FORWARD_EN_STATUS +enum dsc_bits_per_comp { +DSC_BPC_8 =8 , +DSC_BPC_10 =10 , +DSC_BPC_12 =12 , +DSC_BPC_UNKNOWN +};struct dcn20_dsc_registers {uint32_t DSC_TOP_CONTROL;
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +0 -6
@@ -45,12 +45,6 @@ static const struct dsc_funcs dcn401_dsc_funcs = {#define DC_LOGGER \ dsc->ctx->logger -enum dsc_bits_per_comp { -DSC_BPC_8 =8 , -DSC_BPC_10 =10 , -DSC_BPC_12 =12 , -DSC_BPC_UNKNOWN -};/* API functions (external or via structure->function_pointer) */
Signature · 1 line
2.43.0
PATCH 3/28 drm/amd/display: Promote DAL to 3.2.330
In reply to Ray WuFrom: Taimur Hassan <[email protected]>
Summary
* Update IPS checks to properly include all ASICs.
* Refactoring DSC enum dsc_bits_per_comp
* Fix ACPI edid parsing issue
* Update AUX read interval for LTTPR with old sinks
* Correct prefetch calculation
Signed-off-by Taimur Hassan <[email protected]>
Acked-by ChiaHsuan Chung <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/display/dc/dc.h +1 -1
@@ -53,7 +53,7 @@ struct aux_payload;struct set_config_cmd_payload ;struct dmub_notification ; -#define DC_VER "3.2.329" +#define DC_VER "3.2.330"/** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
Signature · 1 line
2.43.0
PATCH 4/28 drm/amd/display: Always Scale Flag
In reply to Ray WuFrom: Jesse Agate <[email protected]>
[Why & How]
When always scale flag is set at the API level, the number of taps should not be overridden to zero in the identity scaling ratio case, and luma scale should not be set to bypass regardless of luma scale ratio
Reviewed-by Samson Tam <[email protected]>
Signed-off-by Jesse Agate <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 25 +++++++++++--------- 1 file changed, 14 insertions(+), 11 deletions(-)
drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c +14 -11
@@ -776,7 +776,7 @@ static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in,* Do not bypass UV at 1:1 for cositing to be applied */ if (!enable_isharp) { -if (data->ratios.horz.value == one && data->ratios.vert.value == one) +if (data->ratios.horz.value == one && data->ratios.vert.value == one && !spl_in->basic_out.always_scale)return SCL_MODE_SCALING_420_LUMA_BYPASS ; }
@@ -884,7 +884,7 @@ static bool spl_get_isharp_en(struct spl_in *spl_in,/* Calculate number of tap with adaptive scaling off */ static void spl_get_taps_non_adaptive_scaler ( -struct spl_scratch *spl_scratch,const struct spl_taps *in_taps) +struct spl_scratch *spl_scratch,const struct spl_taps *in_taps,bool always_scale) {bool check_max_downscale = false;
@@ -944,15 +944,15 @@ static void spl_get_taps_non_adaptive_scaler( spl_fixpt_from_fraction(6, 1));SPL_ASSERT (check_max_downscale); -if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.horz)) + +if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.horz) && !always_scale) spl_scratch->scl_data.taps.h_taps =1 ; -if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.vert)) +if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.vert) && !always_scale) spl_scratch->scl_data.taps.v_taps =1 ; -if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.horz_c)) +if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.horz_c) && !always_scale) spl_scratch->scl_data.taps.h_taps_c =1 ; -if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.vert_c)) +if (IDENTITY_RATIO (spl_scratch->scl_data.ratios.vert_c) && !always_scale) spl_scratch->scl_data.taps.v_taps_c =1 ; - }/* Calculate optimal number of taps */
@@ -965,13 +965,15 @@ static bool spl_get_optimal_number_of_taps(unsigned int max_taps_y, max_taps_c;unsigned int min_taps_y, min_taps_c;enum lb_memory_config lb_config; -bool skip_easf = false; +bool skip_easf = false; +bool always_scale = spl_in->basic_out.always_scale;bool is_subsampled =spl_is_subsampled_format (spl_in->basic_in.format); +if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && max_downscale_src_width !=0 && spl_scratch->scl_data.viewport.width > max_downscale_src_width) { -spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps); +spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps, always_scale); *enable_easf_v = false; *enable_easf_h = false; *enable_isharp = false;
@@ -980,7 +982,7 @@ static bool spl_get_optimal_number_of_taps(/* Disable adaptive scaler and sharpener when integer scaling is enabled */ if (spl_in->scaling_quality.integer_scaling) { -spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps); +spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps, always_scale); *enable_easf_v = false; *enable_easf_h = false; *enable_isharp = false;
@@ -996,7 +998,7 @@ static bool spl_get_optimal_number_of_taps(* taps = 4 for upscaling */ if (skip_easf) -spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps); +spl_get_taps_non_adaptive_scaler (spl_scratch, in_taps, always_scale);else {if (spl_is_video_format (spl_in->basic_in.format)) { spl_scratch->scl_data.taps.h_taps =6 ;
@@ -1898,3 +1900,4 @@ bool SPL_NAMESPACE(spl_get_number_of_taps(struct spl_in *spl_in, struct spl_outspl_set_taps_data (dscl_prog_data, data);return res; } +
Signature · 1 line
2.43.0
PATCH 5/28 drm/amd/display: Remove redundant null check
In reply to Ray WuFrom: Alex Hung <[email protected]>
[WHY & HOW]
The null check for connector was dereferenced previously in the same function and the caller.
Reviewed-by Aurabindo Pillai <[email protected]>
Signed-off-by Alex Hung <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ----- 1 file changed, 5 deletions(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +0 -5
@@ -6989,11 +6989,6 @@ create_stream_for_sink(struct drm_connector *connector,drm_mode_init (&mode, drm_mode);memset (&saved_mode,0 ,sizeof (saved_mode)); -if (connector ==NULL ) { -drm_err (dev,"connector is NULL!\n" ); -return stream; - } -if (connector->connector_type !=DRM_MODE_CONNECTOR_WRITEBACK ) { aconnector =NULL ; aconnector =to_amdgpu_dm_connector (connector);
Signature · 1 line
2.43.0
PATCH 6/28 drm/amd/display: Fix invalid context error in dml helper
In reply to Ray WuFrom: Roman Li <[email protected]>
[Why]
"BUG: sleeping function called from invalid context" error. after:
"drm/amd/display: Protect FPU in dml2_validate()/dml21_validate()"
The populate_dml_plane_cfg_from_plane_state() uses the GFP_KERNEL flag for memory allocation, which shouldn't be used in atomic contexts.
The allocation is needed only for using another helper function get_scaler_data_for_plane().
[How]
Modify helpers to pass a pointer to scaler_data within existing context, eliminating the need for dynamic memory allocation/deallocation and copying.
Fixes d1df16640462 ("drm/amd/display: Protect FPU in dml2_validate()/dml21_validate()")
Reviewed-by Aurabindo Pillai <[email protected]>
Signed-off-by Roman Li <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../amd/display/dc/dml2/dml2_translation_helper.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-)
drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +5 -9
@@ -973,7 +973,9 @@ static void populate_dml_surface_cfg_from_plane_state(enum dml_project_id dml2_p } } -static void get_scaler_data_for_plane (const struct dc_plane_state *in,struct dc_state *context,struct scaler_data *out) +static struct scaler_data *get_scaler_data_for_plane ( +const struct dc_plane_state *in, +struct dc_state *context) {int i;struct pipe_ctx *temp_pipe = &context->res_ctx.temp_pipe;
@@ -994,7 +996,7 @@ static void get_scaler_data_for_plane(const struct dc_plane_state *in, struct dc }ASSERT (i <MAX_PIPES ); -memcpy (out, &temp_pipe->plane_res.scl_data,sizeof (*out)); +return &temp_pipe->plane_res.scl_data; } static void populate_dummy_dml_plane_cfg(struct dml_plane_cfg_st *out, unsigned int location,
@@ -1057,11 +1059,7 @@ static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out const struct dc_plane_state *in, struct dc_state *context, const struct soc_bounding_box_st *soc) { - struct scaler_data *scaler_data = kzalloc(sizeof(*scaler_data), GFP_KERNEL); -if (!scaler_data) -return ; - -get_scaler_data_for_plane (in, context, scaler_data); + struct scaler_data *scaler_data = get_scaler_data_for_plane(in, context); out->CursorBPP[location] = dml_cur_32bit; out->CursorWidth[location] =256 ;
@@ -1126,8 +1124,6 @@ static void populate_dml_plane_cfg_from_plane_state(struct dml_plane_cfg_st *out out->DynamicMetadataTransmittedBytes[location] =0 ; out->NumberOfCursors[location] =1 ; - -kfree (scaler_data); } static unsigned int map_stream_to_dml_display_cfg(const struct dml2_context *dml2,
Signature · 1 line
2.43.0
PATCH 7/28 drm/amd/display: Prepare for Fused I2C-over-AUX
In reply to Ray WuFrom: Dominik Kaszewski <[email protected]>
[Why]
Passive DP-HDMI dongles use I2C-over-AUX protocol which is currently not supported using HDCP Locality Check FW path.
[How]
Prepare code for switching to I2C-over-AUX protocol. Passive dongle detection to be added in another commit.
Reviewed-by Alvin Lee <[email protected]>
Signed-off-by Dominik Kaszewski <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc_fused_io.c | 12 ++++++++---- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- 2 files changed, 10 insertions(+), 5 deletions(-)
drivers/gpu/drm/amd/display/dc/dc_fused_io.c +8 -4
@@ -11,7 +11,8 @@ static bool op_i2c_convert(union dmub_rb_cmd *cmd, const struct mod_hdcp_atomic_op_i2c *op, enum dmub_cmd_fused_request_type type, - uint32_t ddc_line + uint32_t ddc_line, + bool over_aux ) { struct dmub_cmd_fused_request *req = &cmd->fused_io.request;
@@ -23,6 +24,7 @@ static bool op_i2c_convert( req->type = type; loc->is_aux = false; loc->ddc_line = ddc_line; + loc->over_aux = over_aux; loc->address = op->address; loc->offset = op->offset; loc->length = op->size;
@@ -100,11 +102,13 @@ bool dm_atomic_write_poll_read_i2c(if (!link)return false; +const bool over_aux = false;const uint32_t ddc_line = link->ddc->ddc_pin->pin_data->en; +union dmub_rb_cmd commands[3 ] = {0 }; -const bool converted =op_i2c_convert (&commands[0 ], write,FUSED_REQUEST_WRITE , ddc_line) - &&op_i2c_convert (&commands[1 ], poll,FUSED_REQUEST_POLL , ddc_line) - &&op_i2c_convert (&commands[2 ], read,FUSED_REQUEST_READ , ddc_line); +const bool converted =op_i2c_convert (&commands[0 ], write,FUSED_REQUEST_WRITE , ddc_line, over_aux) + &&op_i2c_convert (&commands[1 ], poll,FUSED_REQUEST_POLL , ddc_line, over_aux) + &&op_i2c_convert (&commands[2 ], read,FUSED_REQUEST_READ , ddc_line, over_aux);if (!converted)return false;
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +2 -1
@@ -5447,7 +5447,8 @@ struct dmub_cmd_fused_request {struct dmub_cmd_fused_request_location_i2c {uint8_t is_aux :1 ;// False uint8_t ddc_line :3 ; -uint8_t _reserved0 :4 ; +uint8_t over_aux :1 ; +uint8_t _reserved0 :3 ;uint8_t address;uint8_t offset;uint8_t length;
Signature · 1 line
2.43.0
PATCH 8/28 Revert "drm/amd/display: Refactor SubVP cursor limiting logic"
In reply to Ray WuFrom: Ryan Seto <[email protected]>
This reverts commit bf4cfa2b1854("drm/amd/display: Refactor SubVP cursor limiting logic")
Reason for revert: Corruption
Reviewed-by Alvin Lee <[email protected]>
Signed-off-by Ryan Seto <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/core/dc.c | 52 ++-------- .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 - .../gpu/drm/amd/display/dc/core/dc_resource.c | 48 ++++++++-- .../gpu/drm/amd/display/dc/core/dc_state.c | 96 ------------------- .../gpu/drm/amd/display/dc/core/dc_stream.c | 70 +++----------- drivers/gpu/drm/amd/display/dc/dc.h | 4 - .../gpu/drm/amd/display/dc/dc_state_priv.h | 20 ---- drivers/gpu/drm/amd/display/dc/dc_stream.h | 10 -- .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 - .../dc/dml2/dml21/dml21_translation_helper.c | 9 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +- .../gpu/drm/amd/display/dc/inc/core_status.h | 3 - .../gpu/drm/amd/display/dc/inc/core_types.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 + .../dc/resource/dce100/dce100_resource.c | 4 +- .../dc/resource/dce110/dce110_resource.c | 4 +- .../dc/resource/dce112/dce112_resource.c | 4 +- .../dc/resource/dce112/dce112_resource.h | 2 +- .../dc/resource/dce60/dce60_resource.c | 4 +- .../dc/resource/dce80/dce80_resource.c | 4 +- .../dc/resource/dcn10/dcn10_resource.c | 5 +- .../dc/resource/dcn20/dcn20_resource.c | 6 +- .../dc/resource/dcn20/dcn20_resource.h | 2 +- .../dc/resource/dcn21/dcn21_resource.c | 6 +- .../dc/resource/dcn30/dcn30_resource.c | 4 +- .../dc/resource/dcn30/dcn30_resource.h | 2 +- .../dc/resource/dcn31/dcn31_resource.c | 4 +- .../dc/resource/dcn31/dcn31_resource.h | 2 +- .../dc/resource/dcn314/dcn314_resource.c | 4 +- .../dc/resource/dcn314/dcn314_resource.h | 2 +- .../dc/resource/dcn32/dcn32_resource.c | 65 ++----------- .../dc/resource/dcn32/dcn32_resource.h | 6 +- .../dc/resource/dcn321/dcn321_resource.c | 3 +- .../dc/resource/dcn35/dcn35_resource.c | 6 +- .../dc/resource/dcn351/dcn351_resource.c | 6 +- .../dc/resource/dcn36/dcn36_resource.c | 6 +- .../dc/resource/dcn401/dcn401_resource.c | 49 ++-------- .../dc/resource/dcn401/dcn401_resource.h | 2 +- 39 files changed, 129 insertions(+), 400 deletions(-)
drivers/gpu/drm/amd/display/dc/core/dc.c +10 -42
@@ -37,7 +37,6 @@#include "dc_state.h" #include "dc_state_priv.h" #include "dc_plane_priv.h" -#include "dc_stream_priv.h" #include "gpio_service_interface.h" #include "clk_mgr.h"
@@ -2887,7 +2886,7 @@ static enum surface_update_type check_update_surfaces_for_stream(int i;enum surface_update_type overall_type =UPDATE_TYPE_FAST ; -if (dc->idle_optimizations_allowed ||dc_can_clear_cursor_limit (dc)) +if (dc->idle_optimizations_allowed) overall_type =UPDATE_TYPE_FULL ;if (stream_status ==NULL || stream_status->plane_count != surface_count)
@@ -3291,7 +3290,7 @@ static void copy_stream_update_to_stream(struct dc *dc,if (dsc_validate_context) { stream->timing.dsc_cfg = *update->dsc_config; stream->timing.flags.DSC = enable_dsc; -if (dc->res_pool->funcs->validate_bandwidth (dc, dsc_validate_context, true) !=DC_OK ) { +if (!dc->res_pool->funcs->validate_bandwidth (dc, dsc_validate_context, true)) { stream->timing.dsc_cfg = old_dsc_cfg; stream->timing.flags.DSC = old_dsc_enabled; update->dsc_config =NULL ;
@@ -4609,7 +4608,7 @@ static struct dc_state *create_minimal_transition_state(struct dc *dc,backup_and_set_minimal_pipe_split_policy (dc, base_context, policy);/* commit minimal state */ -if (dc->res_pool->funcs->validate_bandwidth (dc, minimal_transition_context, false) ==DC_OK ) { +if (dc->res_pool->funcs->validate_bandwidth (dc, minimal_transition_context, false)) {/* prevent underflow and corruption when reconfiguring pipes */ force_vsync_flip_in_minimal_transition_context (minimal_transition_context); }else {
@@ -5129,7 +5128,7 @@ static bool update_planes_and_stream_v1(struct dc *dc,copy_stream_update_to_stream (dc, context, stream, stream_update);if (update_type >=UPDATE_TYPE_FULL ) { -if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK ) { +if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false)) {DC_ERROR ("Mode validation failed for stream update!\n" );dc_state_release (context);return false;
@@ -6273,22 +6272,15 @@ bool dc_abm_save_restore(void dc_query_current_properties (struct dc *dc,struct dc_current_properties *properties) {unsigned int i; -unsigned int max_cursor_size = dc->caps.max_cursor_size; -unsigned int stream_cursor_size; +bool subvp_sw_cursor_req = false; -if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { -for (i =0 ; i < dc->current_state->stream_count; i++) { - stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size (dc, - dc->current_state, - dc->current_state->streams[i]); - -if (stream_cursor_size < max_cursor_size) { - max_cursor_size = stream_cursor_size; - } +for (i =0 ; i < dc->current_state->stream_count; i++) { +if (check_subvp_sw_cursor_fallback_req (dc, dc->current_state->streams[i]) && !dc->current_state->streams[i]->hw_cursor_req) { + subvp_sw_cursor_req = true; +break ; } } - - properties->cursor_size_limit = max_cursor_size; + properties->cursor_size_limit = subvp_sw_cursor_req ?64 : dc->caps.max_cursor_size; }/**
@@ -6354,27 +6346,3 @@ unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)else return 0 ; } - -bool dc_is_cursor_limit_pending (struct dc *dc) -{ -uint32_t i; - -for (i =0 ; i < dc->current_state->stream_count; i++) { -if (dc_stream_is_cursor_limit_pending (dc, dc->current_state->streams[i])) -return true; - } - -return false; -} - -bool dc_can_clear_cursor_limit (struct dc *dc) -{ -uint32_t i; - -for (i =0 ; i < dc->current_state->stream_count; i++) { -if (dc_state_can_clear_stream_cursor_subvp_limit (dc->current_state->streams[i], dc->current_state)) -return true; - } - -return false; -}
drivers/gpu/drm/amd/display/dc/core/dc_debug.c +0 -2
@@ -266,8 +266,6 @@ char *dc_status_to_str(enum dc_status status)return "Fail dp payload allocation" ;case DC_FAIL_DP_LINK_BANDWIDTH :return "Insufficient DP link bandwidth" ; -case DC_FAIL_HW_CURSOR_SUPPORT : -return "HW Cursor not supported" ;case DC_ERROR_UNEXPECTED :return "Unexpected error" ; }
drivers/gpu/drm/amd/display/dc/core/dc_resource.c +42 -6
72 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/core/dc_state.c +0 -96
113 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +15 -55
93 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/dc.h +0 -4
@@ -249,7 +249,6 @@ struct dc_caps {uint32_t i2c_speed_in_khz_hdcp;uint32_t dmdata_alloc_size;unsigned int max_cursor_size; -unsigned int max_buffered_cursor_size;unsigned int max_video_width;/* * max video plane width that can be safely assumed to be always
@@ -2608,7 +2607,4 @@ void dc_disable_accelerated_mode(struct dc *dc);bool dc_is_timing_changed (struct dc_stream_state *cur_stream,struct dc_stream_state *new_stream); -bool dc_is_cursor_limit_pending (struct dc *dc); -bool dc_can_clear_cursor_limit (struct dc *dc); -#endif /* DC_INTERFACE_H_ */
drivers/gpu/drm/amd/display/dc/dc_state_priv.h +0 -20
@@ -105,24 +105,4 @@ bool dc_state_is_fams2_in_use(const struct dc *dc, const struct dc_state *state); - -void dc_state_set_stream_subvp_cursor_limit (const struct dc_stream_state *stream, -struct dc_state *state, -bool limit); - -bool dc_state_get_stream_subvp_cursor_limit (const struct dc_stream_state *stream, -struct dc_state *state); - -void dc_state_set_stream_cursor_subvp_limit (const struct dc_stream_state *stream, -struct dc_state *state, -bool limit); - -bool dc_state_get_stream_cursor_subvp_limit (const struct dc_stream_state *stream, -struct dc_state *state); - -bool dc_state_can_clear_stream_cursor_subvp_limit (const struct dc_stream_state *stream, -struct dc_state *state); - -bool dc_state_is_subvp_in_use (struct dc_state *state); -#endif /* _DC_STATE_PRIV_H_ */
drivers/gpu/drm/amd/display/dc/dc_stream.h +0 -10
@@ -44,8 +44,6 @@ struct mall_stream_config {*/ enum mall_stream_type type;struct dc_stream_state *paired_stream;// master / slave stream -bool subvp_limit_cursor_size;/* stream has/is using subvp limiting hw cursor support */ -bool cursor_size_limit_subvp;/* stream is using hw cursor config preventing subvp */ };struct dc_stream_status {
@@ -505,11 +503,6 @@ void program_cursor_position(struct dc *dc, struct dc_stream_state *stream); -bool dc_stream_check_cursor_attributes ( -const struct dc_stream_state *stream, -struct dc_state *state, -const struct dc_cursor_attributes *attributes); -bool dc_stream_set_cursor_attributes (struct dc_stream_state *stream,const struct dc_cursor_attributes *attributes);
@@ -587,7 +580,4 @@ void dc_dmub_update_dirty_rect(struct dc *dc,struct dc_surface_update *srf_updates, struct dc_state *context); -bool dc_stream_is_cursor_limit_pending (struct dc *dc,struct dc_stream_state *stream); -bool dc_stream_can_clear_cursor_limit (struct dc *dc,struct dc_stream_state *stream); -#endif /* DC_STREAM_H_ */
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +0 -1
@@ -627,7 +627,6 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,*/ if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) && !pipe->stream->hw_cursor_req && - !dc_state_get_stream_cursor_subvp_limit(pipe->stream, context) && !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &&
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +3 -6
@@ -526,8 +526,7 @@ static void populate_dml21_output_config_from_stream_state(struct dml2_link_outpstatic void populate_dml21_stream_overrides_from_stream_state (struct dml2_stream_parameters *stream_desc, -struct dc_stream_state *stream, -struct dc_stream_status *stream_status) +struct dc_stream_state *stream) {switch (stream->debug.force_odm_combine_segments) {case 0 :
@@ -552,9 +551,7 @@ static void populate_dml21_stream_overrides_from_stream_state(if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy || stream->debug.force_odm_combine_segments >0 ) stream_desc->overrides.disable_dynamic_odm = true; - stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || - stream->hw_cursor_req || - stream_status->mall_stream_config.cursor_size_limit_subvp; + stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req; }static enum dml2_swizzle_mode gfx_addr3_to_dml2_swizzle_mode (enum swizzle_mode_addr3_values addr3_mode)
@@ -1027,7 +1024,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_spopulate_dml21_timing_config_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);adjust_dml21_hblank_timing_config_from_pipe_ctx (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);populate_dml21_output_config_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]); -populate_dml21_stream_overrides_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]); +populate_dml21_stream_overrides_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index]); dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.fclk_pstate = dml2_twait_budgeting_setting_if_needed; dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.uclk_pstate = dml2_twait_budgeting_setting_if_needed;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +1 -1
@@ -2482,7 +2482,7 @@ bool dcn20_update_bandwidth(struct dce_hwseq *hws = dc->hwseq;/* recalculate DML parameters */ -if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK ) +if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false))return false;/* apply updated bandwidth parameters */
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +1 -1
@@ -2651,7 +2651,7 @@ bool dcn401_update_bandwidth(struct dce_hwseq *hws = dc->hwseq;/* recalculate DML parameters */ -if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK ) +if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false))return false;/* apply updated bandwidth parameters */
drivers/gpu/drm/amd/display/dc/inc/core_status.h +0 -3
@@ -26,8 +26,6 @@#ifndef _CORE_STATUS_H_#define _CORE_STATUS_H_ -#include "dc_hw_types.h" -enum dc_status { DC_OK = 1,
@@ -58,7 +56,6 @@ enum dc_status {DC_NO_LINK_ENC_RESOURCE =26 ,DC_FAIL_DP_PAYLOAD_ALLOCATION =27 ,DC_FAIL_DP_LINK_BANDWIDTH =28 , -DC_FAIL_HW_CURSOR_SUPPORT =29 , DC_ERROR_UNEXPECTED = -1 };
drivers/gpu/drm/amd/display/dc/inc/core_types.h +1 -5
@@ -78,8 +78,7 @@ struct resource_funcs {/* Create a minimal link encoder object with no dc_link object * associated with it. */ struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx,enum engine_id eng_id); - -enum dc_status (*validate_bandwidth)( +bool (*validate_bandwidth)(struct dc *dc,struct dc_state *context,bool fast_validate);
@@ -218,9 +217,6 @@ struct resource_funcs {int (*get_power_profile)(const struct dc_state *context);unsigned int (*get_det_buffer_size)(const struct dc_state *context);unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx); -unsigned int (*get_max_hw_cursor_size)(const struct dc *dc, -struct dc_state *state, -const struct dc_stream_state *stream); };struct audio_support {
drivers/gpu/drm/amd/display/dc/inc/resource.h +2 -0
@@ -628,6 +628,8 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,struct dc_state *context, struct pipe_ctx *pipe_ctx); +bool check_subvp_sw_cursor_fallback_req (const struct dc *dc,struct dc_stream_state *stream); +/* Get hw programming parameters container from pipe context * @pipe_ctx: pipe context * @dscl_prog_data: struct to hold programmable hw reg values
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +2 -2
@@ -836,7 +836,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -static enum dc_status dce100_validate_bandwidth ( +static bool dce100_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -858,7 +858,7 @@ static enum dc_status dce100_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return DC_OK ; +return true; } static bool dce100_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +2 -2
@@ -960,7 +960,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -static enum dc_status dce110_validate_bandwidth ( +static bool dce110_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -1031,7 +1031,7 @@ static enum dc_status dce110_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz, context->bw_ctx.bw.dce.blackout_recovery_time_us); } -return result ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return result; } static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +2 -2
@@ -883,7 +883,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -enum dc_status dce112_validate_bandwidth ( +bool dce112_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -952,7 +952,7 @@ enum dc_status dce112_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz, context->bw_ctx.bw.dce.blackout_recovery_time_us); } -return result ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return result; } enum dc_status resource_map_phy_clock_resources(
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h +1 -1
@@ -42,7 +42,7 @@ enum dc_status dce112_validate_with_context(struct dc_state *context, struct dc_state *old_context); -enum dc_status dce112_validate_bandwidth ( +bool dce112_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +2 -2
@@ -863,7 +863,7 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool) } } -static enum dc_status dce60_validate_bandwidth ( +static bool dce60_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -885,7 +885,7 @@ static enum dc_status dce60_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return DC_OK ; +return true; } static bool dce60_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +2 -2
@@ -869,7 +869,7 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } -static enum dc_status dce80_validate_bandwidth ( +static bool dce80_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -891,7 +891,7 @@ static enum dc_status dce80_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return DC_OK ; +return true; } static bool dce80_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +2 -3
@@ -23,7 +23,6 @@* */ -#include "core_status.h" #include "dm_services.h" #include "dc.h"
@@ -1126,7 +1125,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool) *pool =NULL ; } -static enum dc_status dcn10_validate_bandwidth ( +static bool dcn10_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -1137,7 +1136,7 @@ static enum dc_status dcn10_validate_bandwidth( voltage_supported =dcn_validate_bandwidth (dc, context, fast_validate);DC_FP_END (); -return voltage_supported ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return voltage_supported; }static enum dc_status dcn10_validate_plane (const struct dc_plane_state *plane_state,struct dc_caps *caps)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +3 -3
@@ -2124,7 +2124,7 @@ bool dcn20_fast_validate_bw(return out; } -enum dc_status dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context, +bool dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {bool voltage_supported;
@@ -2132,14 +2132,14 @@ enum dc_status dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, pipes =kcalloc (dc->res_pool->pipe_count,sizeof (display_e2e_pipe_params_st),GFP_KERNEL );if (!pipes) -return DC_FAIL_BANDWIDTH_VALIDATE ; +return false;DC_FP_START (); voltage_supported =dcn20_validate_bandwidth_fp (dc, context, fast_validate, pipes);DC_FP_END ();kfree (pipes); -return voltage_supported ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return voltage_supported; } struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +1 -1
@@ -119,7 +119,7 @@ void dcn20_set_mcif_arb_params(struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt); -enum dc_status dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); +bool dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);void dcn20_merge_pipes_for_validate (struct dc *dc,struct dc_state *context);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +3 -3
@@ -923,7 +923,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,* with DC_FP_START()/DC_FP_END(). Use the same approach as for * dcn20_validate_bandwidth in dcn20_resource.c. */ -static enum dc_status dcn21_validate_bandwidth (struct dc *dc,struct dc_state *context, +static bool dcn21_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {bool voltage_supported;
@@ -931,14 +931,14 @@ static enum dc_status dcn21_validate_bandwidth(struct dc *dc, struct dc_state *c pipes =kcalloc (dc->res_pool->pipe_count,sizeof (display_e2e_pipe_params_st),GFP_KERNEL );if (!pipes) -return DC_FAIL_BANDWIDTH_VALIDATE ; +return false;DC_FP_START (); voltage_supported =dcn21_validate_bandwidth_fp (dc, context, fast_validate, pipes);DC_FP_END ();kfree (pipes); -return voltage_supported ?DC_OK :DC_NOT_SUPPORTED ; +return voltage_supported; }static void dcn21_destroy_resource_pool (struct resource_pool **pool)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +2 -2
@@ -2035,7 +2035,7 @@ void dcn30_calculate_wm_and_dlg(DC_FP_END (); } -enum dc_status dcn30_validate_bandwidth (struct dc *dc, +bool dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -2092,7 +2092,7 @@ enum dc_status dcn30_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }void dcn30_update_bw_bounding_box (struct dc *dc,struct clk_bw_params *bw_params)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h +1 -1
@@ -56,7 +56,7 @@ unsigned int dcn30_calc_max_scaled_time(enum mmhubbub_wbif_mode mode, unsigned int urgent_watermark); -enum dc_status dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context, +bool dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); bool dcn30_internal_validate_bw( struct dc *dc,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +2 -2
@@ -1758,7 +1758,7 @@ dcn31_set_mcif_arb_params(struct dc *dc,DC_FP_END (); } -enum dc_status dcn31_validate_bandwidth (struct dc *dc, +bool dcn31_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1813,7 +1813,7 @@ enum dc_status dcn31_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }static void dcn31_get_panel_config_defaults (struct dc_panel_config *panel_config)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h +1 -1
@@ -37,7 +37,7 @@ struct dcn31_resource_pool {struct resource_pool base; }; -enum dc_status dcn31_validate_bandwidth (struct dc *dc, +bool dcn31_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); void dcn31_calculate_wm_and_dlg(
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +2 -2
@@ -1694,7 +1694,7 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi *panel_config = panel_config_defaults; } -enum dc_status dcn314_validate_bandwidth (struct dc *dc, +bool dcn314_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1750,7 +1750,7 @@ enum dc_status dcn314_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }static struct resource_funcs dcn314_res_pool_funcs = {
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h +1 -1
@@ -39,7 +39,7 @@ struct dcn314_resource_pool {struct resource_pool base; }; -enum dc_status dcn314_validate_bandwidth (struct dc *dc, +bool dcn314_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +7 -58
96 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +1 -5
@@ -98,7 +98,7 @@ void dcn32_add_phantom_pipes(struct dc *dc,unsigned int pipe_cnt, unsigned int index); -enum dc_status dcn32_validate_bandwidth (struct dc *dc, +bool dcn32_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
@@ -188,10 +188,6 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);unsigned int dcn32_calculate_mall_ways_from_bytes (const struct dc *dc,unsigned int total_size_in_mall_bytes); -unsigned int dcn32_get_max_hw_cursor_size (const struct dc *dc, -struct dc_state *state, -const struct dc_stream_state *stream); -/* definitions for run time init of reg offsets */ /* CLK SRC */
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +1 -2
@@ -1624,8 +1624,7 @@ static struct resource_funcs dcn321_res_pool_funcs = { .add_phantom_pipes = dcn32_add_phantom_pipes, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, - .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe };static uint32_t read_pipe_fuses (struct dc_context *ctx)
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +3 -3
@@ -1732,7 +1732,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static enum dc_status dcn35_validate_bandwidth (struct dc *dc, +static bool dcn35_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1743,13 +1743,13 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }enum dc_status dcn35_patch_unknown_plane_state (struct dc_plane_state *plane_state)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +3 -3
@@ -1712,7 +1712,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static enum dc_status dcn351_validate_bandwidth (struct dc *dc, +static bool dcn351_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1723,13 +1723,13 @@ static enum dc_status dcn351_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }static struct resource_funcs dcn351_res_pool_funcs = {
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +3 -3
@@ -1713,7 +1713,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static enum dc_status dcn35_validate_bandwidth (struct dc *dc, +static bool dcn35_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1724,13 +1724,13 @@ static enum dc_status dcn35_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; +return out; }
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +6 -43
66 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +1 -1
@@ -22,7 +22,7 @@ struct resource_pool *dcn401_create_resource_pool(enum dc_status dcn401_patch_unknown_plane_state (struct dc_plane_state *plane_state); -enum dc_status dcn401_validate_bandwidth (struct dc *dc, +bool dcn401_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
Signature · 1 line
2.43.0
PATCH 9/28 drm/amd/display: allow dscclk disable
In reply to Ray WuFrom: Charlene Liu <[email protected]>
[why]
when dscclk rcg disabled from usr reg option,
dsc clock will remain enabled because driver was doing two things both dscclk and dsc rcg in the same routine.
Reviewed-by Hansen Dsouza <[email protected]>
Signed-off-by Charlene Liu <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +13 -11
@@ -1035,6 +1035,7 @@ static void dccg35_enable_dpp_clk_new( DPPCLK0_DTO_MODULO, 0xFF); } +static void dccg35_disable_dpp_clk_new (struct dccg *dccg,int inst)
@@ -1771,36 +1772,40 @@ static void dccg35_enable_dscclk(struct dccg *dccg, int inst)//Disable DTO switch (inst) {case 0 : +if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) +REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK0_ROOT_GATE_DISABLE ,1 ); +REG_UPDATE_2 (DSCCLK0_DTO_PARAM ,DSCCLK0_DTO_PHASE ,0 ,DSCCLK0_DTO_MODULO ,0 );REG_UPDATE (DSCCLK_DTO_CTRL ,DSCCLK0_EN ,1 ); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK0_ROOT_GATE_DISABLE ,1 );break ;case 1 : +if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) +REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK1_ROOT_GATE_DISABLE ,1 ); +REG_UPDATE_2 (DSCCLK1_DTO_PARAM ,DSCCLK1_DTO_PHASE ,0 ,DSCCLK1_DTO_MODULO ,0 );REG_UPDATE (DSCCLK_DTO_CTRL ,DSCCLK1_EN ,1 ); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK1_ROOT_GATE_DISABLE ,1 );break ;case 2 : +if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) +REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK2_ROOT_GATE_DISABLE ,1 ); +REG_UPDATE_2 (DSCCLK2_DTO_PARAM ,DSCCLK2_DTO_PHASE ,0 ,DSCCLK2_DTO_MODULO ,0 );REG_UPDATE (DSCCLK_DTO_CTRL ,DSCCLK2_EN ,1 ); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK2_ROOT_GATE_DISABLE ,1 );break ;case 3 : +if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) +REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK3_ROOT_GATE_DISABLE ,1 ); +REG_UPDATE_2 (DSCCLK3_DTO_PARAM ,DSCCLK3_DTO_PHASE ,0 ,DSCCLK3_DTO_MODULO ,0 );REG_UPDATE (DSCCLK_DTO_CTRL ,DSCCLK3_EN ,1 ); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DSCCLK3_ROOT_GATE_DISABLE ,1 );break ;default :BREAK_TO_DEBUGGER ();
@@ -1813,9 +1818,6 @@ static void dccg35_disable_dscclk(struct dccg *dccg, {struct dcn_dccg *dccg_dcn =TO_DCN_DCCG (dccg); -if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) -return ; -switch (inst) {case 0 :REG_UPDATE (DSCCLK_DTO_CTRL ,DSCCLK0_EN ,0 );
Signature · 1 line
2.43.0
PATCH 10/28 drm/amd/display: more liberal vmin/vmax update for freesync
In reply to Ray WuFrom: Aurabindo Pillai <[email protected]>
[Why]
FAMS2 expects vmin/vmax to be updated in the case when freesync is off, but supported. But we only update it when freesync is enabled.
[How]
Change the vsync handler such that dc_stream_adjust_vmin_vmax() its called irrespective of whether freesync is enabled. If freesync is supported, then there is no harm in updating vmin/vmax registers.
Reviewed-by ChiaHsuan Chung <[email protected]>
Signed-off-by Aurabindo Pillai <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +11 -5
@@ -675,15 +675,21 @@ static void dm_crtc_high_irq(void *interrupt_params)spin_lock_irqsave (&adev_to_drm (adev)->event_lock, flags);if (acrtc->dm_irq_params.stream && - acrtc->dm_irq_params.vrr_params.supported && - acrtc->dm_irq_params.freesync_config.state == -VRR_STATE_ACTIVE_VARIABLE ) { + acrtc->dm_irq_params.vrr_params.supported) { +bool replay_en = acrtc->dm_irq_params.stream->link->replay_settings.replay_feature_enabled; +bool psr_en = acrtc->dm_irq_params.stream->link->psr_settings.psr_feature_enabled; +bool fs_active_var_en = acrtc->dm_irq_params.freesync_config.state ==VRR_STATE_ACTIVE_VARIABLE ; +mod_freesync_handle_v_update (adev->dm.freesync_module, acrtc->dm_irq_params.stream, &acrtc->dm_irq_params.vrr_params); -dc_stream_adjust_vmin_vmax (adev->dm.dc, acrtc->dm_irq_params.stream, - &acrtc->dm_irq_params.vrr_params.adjust); +/* update vmin_vmax only if freesync is enabled, or only if PSR and REPLAY are disabled */ +if (fs_active_var_en || (!fs_active_var_en && !replay_en && !psr_en)) { +dc_stream_adjust_vmin_vmax (adev->dm.dc, + acrtc->dm_irq_params.stream, + &acrtc->dm_irq_params.vrr_params.adjust); + } }/*
Signature · 1 line
2.43.0
PATCH 11/28 drm/amd/display: disable DPP RCG before DPP CLK enable
In reply to Ray WuFrom: Charlene Liu <[email protected]>
[why]
DPP CLK enable needs to disable DPPCLK RCG first.
The DPPCLK_en in dccg should always be enabled when the corresponding pipe is enabled.
Reviewed-by Hansen Dsouza <[email protected]>
Signed-off-by Charlene Liu <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 38 ++++++++++++------- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 21 ++++++---- 2 files changed, 38 insertions(+), 21 deletions(-)
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +24 -14
@@ -391,6 +391,7 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg,struct dcn_dccg *dccg_dcn =TO_DCN_DCCG (dccg); +if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)return ;
@@ -411,6 +412,8 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg,BREAK_TO_DEBUGGER ();break ; } +//DC_LOG_DEBUG("%s: inst(%d) DPPCLK rcg_disable: %d\n", __func__, inst, enable ? 0 : 1); + } static void dccg35_set_dpstreamclk_rcg(
@@ -1113,30 +1116,24 @@ static void dcn35_set_dppclk_enable(struct dccg *dccg, {struct dcn_dccg *dccg_dcn =TO_DCN_DCCG (dccg); +switch (dpp_inst) {case 0 :REG_UPDATE (DPPCLK_CTRL ,DPPCLK0_EN , enable); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DPPCLK0_ROOT_GATE_DISABLE , enable);break ;case 1 :REG_UPDATE (DPPCLK_CTRL ,DPPCLK1_EN , enable); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DPPCLK1_ROOT_GATE_DISABLE , enable);break ;case 2 :REG_UPDATE (DPPCLK_CTRL ,DPPCLK2_EN , enable); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DPPCLK2_ROOT_GATE_DISABLE , enable);break ;case 3 :REG_UPDATE (DPPCLK_CTRL ,DPPCLK3_EN , enable); -if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) -REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DPPCLK3_ROOT_GATE_DISABLE , enable);break ;default :break ; } +//DC_LOG_DEBUG("%s: dpp_inst(%d) DPPCLK_EN = %d\n", __func__, dpp_inst, enable); }
@@ -1164,14 +1161,18 @@ static void dccg35_update_dpp_dto(struct dccg *dccg, int dpp_inst,ASSERT (false); phase =0xff ; } +dccg35_set_dppclk_rcg (dccg, dpp_inst, false);REG_SET_2 (DPPCLK_DTO_PARAM [dpp_inst],0 ,DPPCLK0_DTO_PHASE , phase,DPPCLK0_DTO_MODULO , modulo);dcn35_set_dppclk_enable (dccg, dpp_inst, true); - }else + }else {dcn35_set_dppclk_enable (dccg, dpp_inst, false); +/*we have this in hwss: disable_plane*/ +//dccg35_set_dppclk_rcg(dccg, dpp_inst, true); + } dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; }
@@ -1183,6 +1184,7 @@ static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)return ; +switch (dpp_inst) {case 0 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL6 ,DPPCLK0_ROOT_GATE_DISABLE , enable);
@@ -1199,6 +1201,8 @@ static void dccg35_set_dppclk_root_clock_gating(struct dccg *dccg,default :break ; } +//DC_LOG_DEBUG("%s: dpp_inst(%d) rcg: %d\n", __func__, dpp_inst, enable); + } static void dccg35_get_pixel_rate_div(
@@ -1522,28 +1526,30 @@ static void dccg35_set_physymclk_root_clock_gating(switch (phy_inst) {case 0 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL2 , -PHYASYMCLK_ROOT_GATE_DISABLE , enable ?1 :0 ); +PHYASYMCLK_ROOT_GATE_DISABLE , enable ?0 :1 );break ;case 1 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL2 , -PHYBSYMCLK_ROOT_GATE_DISABLE , enable ?1 :0 ); +PHYBSYMCLK_ROOT_GATE_DISABLE , enable ?0 :1 );break ;case 2 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL2 , -PHYCSYMCLK_ROOT_GATE_DISABLE , enable ?1 :0 ); +PHYCSYMCLK_ROOT_GATE_DISABLE , enable ?0 :1 );break ;case 3 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL2 , -PHYDSYMCLK_ROOT_GATE_DISABLE , enable ?1 :0 ); +PHYDSYMCLK_ROOT_GATE_DISABLE , enable ?0 :1 );break ;case 4 :REG_UPDATE (DCCG_GATE_DISABLE_CNTL2 , -PHYESYMCLK_ROOT_GATE_DISABLE , enable ?1 :0 ); +PHYESYMCLK_ROOT_GATE_DISABLE , enable ?0 :1 );break ;default :BREAK_TO_DEBUGGER ();return ; } +//DC_LOG_DEBUG("%s: dpp_inst(%d) PHYESYMCLK_ROOT_GATE_DISABLE:\n", __func__, phy_inst, enable ? 0 : 1); + } static void dccg35_set_physymclk(
@@ -1644,6 +1650,8 @@ static void dccg35_dpp_root_clock_control(return ;if (clock_on) { +dccg35_set_dppclk_rcg (dccg, dpp_inst, false); +/* turn off the DTO and leave phase/modulo at max */ dcn35_set_dppclk_enable (dccg, dpp_inst,1 ); REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
@@ -1655,6 +1663,8 @@ static void dccg35_dpp_root_clock_control(REG_SET_2 (DPPCLK_DTO_PARAM [dpp_inst],0 ,DPPCLK0_DTO_PHASE ,0 ,DPPCLK0_DTO_MODULO ,1 ); +/*we have this in hwss: disable_plane*/ +//dccg35_set_dppclk_rcg(dccg, dpp_inst, true); } dccg->dpp_clock_gated[dpp_inst] = !clock_on;
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +14 -7
@@ -241,11 +241,6 @@ void dcn35_init_hw(struct dc *dc) dc->res_pool->hubbub->funcs->allow_self_refresh_control (dc->res_pool->hubbub, !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); } -if (res_pool->dccg->funcs->dccg_root_gate_disable_control) { -for (i =0 ; i < res_pool->pipe_count; i++) - res_pool->dccg->funcs->dccg_root_gate_disable_control (res_pool->dccg, i,0 ); - } -for (i =0 ; i < res_pool->audio_count; i++) {struct audio *audio = res_pool->audios[i];
@@ -901,12 +896,18 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)void dcn35_enable_plane (struct dc *dc,struct pipe_ctx *pipe_ctx,struct dc_state *context) { +struct dpp *dpp = pipe_ctx->plane_res.dpp; +struct dccg *dccg = dc->res_pool->dccg; + +/* enable DCFCLK current DCHUB */ pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl (pipe_ctx->plane_res.hubp, true);/* initialize HUBP on power up */ pipe_ctx->plane_res.hubp->funcs->hubp_init (pipe_ctx->plane_res.hubp); - +/*make sure DPPCLK is on*/ + dccg->funcs->dccg_root_gate_disable_control (dccg, dpp->inst, true); + dpp->funcs->dpp_dppclk_control (dpp, false, true);/* make sure OPP_PIPE_CLOCK_EN = 1 */ pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control( pipe_ctx->stream_res.opp,
@@ -923,6 +924,7 @@ void dcn35_enable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx,// Program system aperture settings pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings (pipe_ctx->plane_res.hubp, &apt); } +//DC_LOG_DEBUG("%s: dpp_inst(%d) =\n", __func__, dpp->inst); if (!pipe_ctx->top_pipe && pipe_ctx->plane_state
@@ -938,6 +940,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) {struct hubp *hubp = pipe_ctx->plane_res.hubp;struct dpp *dpp = pipe_ctx->plane_res.dpp; +struct dccg *dccg = dc->res_pool->dccg; + dc->hwss.wait_for_mpcc_disconnect (dc, dc->res_pool, pipe_ctx);
@@ -955,7 +959,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) hubp->funcs->hubp_clk_cntl (hubp, false); dpp->funcs->dpp_dppclk_control (dpp, false, false); -/*to do, need to support both case*/ + dccg->funcs->dccg_root_gate_disable_control (dccg, dpp->inst, false); + hubp->power_gated = true; hubp->funcs->hubp_reset (hubp);
@@ -967,6 +972,8 @@ void dcn35_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) pipe_ctx->top_pipe =NULL ; pipe_ctx->bottom_pipe =NULL ; pipe_ctx->plane_state =NULL ; +//DC_LOG_DEBUG("%s: dpp_inst(%d)=\n", __func__, dpp->inst); + }void dcn35_disable_plane (struct dc *dc,struct dc_state *state,struct pipe_ctx *pipe_ctx)
Signature · 1 line
2.43.0
PATCH 12/28 drm/amd/display: [FW Promotion] Release 0.1.8.0
In reply to Ray WuFrom: Taimur Hassan <[email protected]>
Undefined unnecessary definition to avoid wrong referring
Acked-by Tom Chung <[email protected]>
Signed-off-by Taimur Hassan <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 +++ 1 file changed, 3 insertions(+)
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +3 -0
@@ -36,6 +36,9 @@//<DMUB_TYPES>================================================================== /* Basic type definitions. */ +#ifdef __forceinline +#undef __forceinline +#endif #define __forceinline inline/**
Signature · 1 line
2.43.0
PATCH 13/28 drm/amd/display: Promote DAL to 3.2.331
In reply to Ray WuFrom: Taimur Hassan <[email protected]>
Summary
* Remove redundant NULL check
* Fix invalid context error in dml helper
* Prepare for Fused I2C-over-AUX
* Allow DSCClock disable
* Vmax / Vmin update for Vsync
Acked-by Tom Chung <[email protected]>
Signed-off-by Taimur Hassan <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/display/dc/dc.h +1 -1
@@ -53,7 +53,7 @@ struct aux_payload;struct set_config_cmd_payload ;struct dmub_notification ; -#define DC_VER "3.2.330" +#define DC_VER "3.2.331"/** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
Signature · 1 line
2.43.0
PATCH 14/28 drm/amd/display: Allow 0 dtbclk for DCN35 and above
In reply to Ray WuFrom: Leo Li <[email protected]>
[Why & How]
0 dtbclk is supported by ASICs with DCN35 and above, so allow it during driver init.
Reviewed-by Aurabindo Pillai <[email protected]>
Signed-off-by Leo Li <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +4 -0
@@ -2106,6 +2106,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.disable_ips_in_vpb =0 ; +/* DCN35 and above supports dtb clk disable */ +if (amdgpu_ip_version (adev,DCE_HWIP ,0 ) >=IP_VERSION (3 ,5 ,0 )) + init_data.flags.allow_0_dtb_clk = true; +/* Enable DWB for tested platforms only */ if (amdgpu_ip_version (adev,DCE_HWIP ,0 ) >=IP_VERSION (3 ,0 ,0 )) init_data.num_virtual_links =1 ;
Signature · 1 line
2.43.0
PATCH 15/28 Revert "drm/amd/display: turn off eDP lcdvdd and backlight if not required"
In reply to Ray WuFrom: Nicholas Kazlauskas <[email protected]>
This reverts commit b91fff88686e("drm/amd/display: turn off eDP lcdvdd and backlight if not required")
Reason for revert: Causes S4 lightup regressions.
Reviewed-by Gabe Teeger <[email protected]>
Signed-off-by Nicholas Kazlauskas <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- .../amd/display/dc/link/protocols/link_edp_panel_control.c | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/display/dc/core/dc.c +2 -2
@@ -6298,10 +6298,10 @@ void dc_query_current_properties(struct dc *dc, struct dc_current_properties *prvoid dc_set_edp_power (const struct dc *dc,struct dc_link *edp_link,bool powerOn) { -if (!edp_link || !edp_link->dc || !edp_link->dc->link_srv) +if (edp_link->connector_signal !=SIGNAL_TYPE_EDP )return ; -if (edp_link->connector_signal !=SIGNAL_TYPE_EDP ) +if (edp_link->skip_implict_edp_power_control == false)return ; edp_link->dc->link_srv->edp_set_panel_power (edp_link, powerOn);
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +0 -2
@@ -393,7 +393,6 @@ void edp_set_panel_power(struct dc_link *link, bool powerOn)// 3. Rx power on dpcd_write_rx_power_ctrl (link, true); -DC_LOG_BACKLIGHT ("eDP power and backlight: Power on" ); }else {// 3. Rx power off dpcd_write_rx_power_ctrl (link, false);
@@ -405,7 +404,6 @@ void edp_set_panel_power(struct dc_link *link, bool powerOn)// 1. panel VDD off if (!link->dc->config.edp_no_power_sequencing) link->dc->hwss.edp_power_control (link, false); -DC_LOG_BACKLIGHT ("eDP power and backlight: Power off" ); } }
Signature · 1 line
2.43.0
PATCH 16/28 drm/amd/display: Add skip rIOMMU dc config option
In reply to Ray WuFrom: Kevin Gao <[email protected]>
[Why]
Need option to skip rIOMMU calls for dcn21.
[How]
Added rIOMMU dc config option and check for whether to skip rIOMMU calls.
Reviewed-by Nicholas Kazlauskas <[email protected]>
Signed-off-by Kevin Gao <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-)
drivers/gpu/drm/amd/display/dc/dc.h +1 -0
@@ -448,6 +448,7 @@ struct dc_config {bool enable_windowed_mpo_odm;bool forceHBR2CP2520;// Used for switching between test patterns TPS4 and CP2520 uint32_t allow_edp_hotplug_detection; +bool skip_riommu_prefetch_wa;bool clamp_min_dcfclk;uint64_t vblank_alignment_dto_params;uint8_t vblank_alignment_max_frame_time_diff;
drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c +3 -3
@@ -132,9 +132,9 @@ int hubbub21_init_dchub(struct hubbub *hubbub,// Init VMID 0 based on PA config dcn20_vmid_setup (&hubbub1->vmid[0 ], &phys_config); } - -dcn21_dchvm_init (hubbub); - +if (!hubbub1->base.ctx->dc->config.skip_riommu_prefetch_wa) { +dcn21_dchvm_init (hubbub); + }return hubbub1->num_vmid; }
Signature · 1 line
2.43.0
PATCH 17/28 drm/amd/display: Send IPSExit unconditionally.
In reply to Ray WuFrom: JinZe Xu <[email protected]>
[Why&How]
PMFW needs to flush page cache in IPSExit.
Reviewed-by Nicholas Kazlauskas <[email protected]>
Signed-off-by JinZe Xu <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-)
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +8 -7
@@ -1365,14 +1365,15 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc)if (!dc->debug.optimize_ips_handshake || !ips_fw->signals.bits.ips2_commit)udelay (dc->debug.ips2_eval_delay_us); -if (ips_fw->signals.bits.ips2_commit) { -DC_LOG_IPS ( -"exit IPS2 #1 (ips1_commit=%u ips2_commit=%u)" , - ips_fw->signals.bits.ips1_commit, - ips_fw->signals.bits.ips2_commit); +DC_LOG_IPS ( +"exit IPS2 #1 (ips1_commit=%u ips2_commit=%u)" , + ips_fw->signals.bits.ips1_commit, + ips_fw->signals.bits.ips2_commit); -// Tell PMFW to exit low power state - dc->clk_mgr->funcs->exit_low_power_state (dc->clk_mgr); +// Tell PMFW to exit low power state + dc->clk_mgr->funcs->exit_low_power_state (dc->clk_mgr); + +if (ips_fw->signals.bits.ips2_commit) { DC_LOG_IPS( "wait IPS2 entry delay (ips1_commit=%u ips2_commit=%u)",
Signature · 1 line
2.43.0
PATCH 18/28 drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
In reply to Ray WuFrom: Alex Hung <[email protected]>
[WHY & HOW]
Remove the unnecessary DC_FP_START/DC_FP_END pair to reduce time in preempt_disable. It also fixes "BUG: sleeping function called from invalid context" error messages because of calling kzalloc with GFP_KERNEL which can sleep.
Reviewed-by Aurabindo Pillai <[email protected]>
Signed-off-by Alex Hung <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 6 ------ 1 file changed, 6 deletions(-)
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +0 -6
@@ -2114,8 +2114,6 @@ static bool dcn32_resource_construct(#define REG_STRUCT dccg_regsdccg_regs_init (); -DC_FP_START (); - ctx->dc_bios->regs = &bios_regs; pool->base.res_cap = &res_cap_dcn32;
@@ -2501,14 +2499,10 @@ static bool dcn32_resource_construct(if (ASICREV_IS_GC_11_0_3 (dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc ==0 )) dc->config.sdpif_request_limit_words_per_umc =16 ; -DC_FP_END (); -return true; create_fail: -DC_FP_END (); -dcn32_resource_destruct (pool);return false;
Signature · 1 line
2.43.0
Re: [PATCH 18/28] drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
Quoted 8 lines · Ray Wu
From: Alex Hung <[email protected]>
[WHY & HOW]
Remove the unnecessary DC_FP_START/DC_FP_END pair to reduce time inpreempt_disable. It also fixes "BUG: sleeping function called from invalid context" error messages because of calling kzalloc withGFP_KERNELwhich can sleep.
Is this safe? If this function uses FP or calls a function which uses FP, removing these will lead to register corruption.
Alex
Quoted 39 lines
Reviewed-by Aurabindo Pillai <[email protected]>Signed-off-by Alex Hung <[email protected]>Signed-off-by Ray Wu <[email protected]>--- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 6 ------ 1 file changed, 6 deletions(-)drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +0
-7@@ -2114,8 +2114,6 @@ static bool dcn32_resource_construct(#define REG_STRUCT dccg_regsdccg_regs_init (); -DC_FP_START (); - ctx->dc_bios->regs = &bios_regs; pool->base.res_cap = &res_cap_dcn32;@@ -2501,14 +2499,10 @@ static bool dcn32_resource_construct(if (ASICREV_IS_GC_11_0_3 (dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc ==0 )) dc->config.sdpif_request_limit_words_per_umc =16 ; -DC_FP_END (); -return true; create_fail: -DC_FP_END (); -dcn32_resource_destruct (pool);return false; --2.43.0
Re: [PATCH 18/28] drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
Quoted 4 lines · Alex Deucher
Quoted 3 lines · Ray Wu
From: Alex Hung <[email protected]>
Quoted 8 lines
Quoted 5 lines
[WHY & HOW]
Remove the unnecessary DC_FP_START/DC_FP_END pair to reduce time inpreempt_disable. It also fixes "BUG: sleeping function called from invalid context" error messages because of calling kzalloc withGFP_KERNELwhich can sleep.Is this safe? If this function uses FP or calls a function which uses FP, removing these will lead to register corruption.
I checked dcn32_resource_construct again and I did not find any FP or functions uses FP, and Aurabindo helped double check.
I also checked other dnc*_resource_construct (like 321, 35, 351, 36) and they don't use DC_FP_START/DC_FP_END pair either.
So it should be safe to remove this pair.
Quoted 42 lines
Alex
Quoted 39 lines
Reviewed-by Aurabindo Pillai <[email protected]>Signed-off-by Alex Hung <[email protected]>Signed-off-by Ray Wu <[email protected]>--- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 6 ------ 1 file changed, 6 deletions(-)drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +0
-7@@ -2114,8 +2114,6 @@ static bool dcn32_resource_construct(#define REG_STRUCT dccg_regsdccg_regs_init (); -DC_FP_START (); - ctx->dc_bios->regs = &bios_regs; pool->base.res_cap = &res_cap_dcn32;@@ -2501,14 +2499,10 @@ static bool dcn32_resource_construct(if (ASICREV_IS_GC_11_0_3 (dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc ==0 )) dc->config.sdpif_request_limit_words_per_umc =16 ; -DC_FP_END (); -return true; create_fail: -DC_FP_END (); -dcn32_resource_destruct (pool);return false; --2.43.0
Re: [PATCH 18/28] drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
Quoted 17 lines · Alex Hung
Quoted 4 lines · Alex Deucher
Quoted 3 lines · Ray Wu
From: Alex Hung <[email protected]>
Quoted 8 lines
Quoted 5 lines
[WHY & HOW]
Remove the unnecessary DC_FP_START/DC_FP_END pair to reduce time inpreempt_disable. It also fixes "BUG: sleeping function called from invalid context" error messages because of calling kzalloc withGFP_KERNELwhich can sleep.Is this safe? If this function uses FP or calls a function which uses FP, removing these will lead to register corruption.
Quoted 7 lines
I checked
dcn32_resource_constructagain and I did not find any FP or functions uses FP, and Aurabindo helped double check.I also checked other dnc*_resource_construct (like 321, 35, 351, 36) and they don't use DC_FP_START/DC_FP_END pair either.
So it should be safe to remove this pair.
Great. Thanks for verifying.
Alex
Quoted 44 lines
Quoted 43 lines
Alex
Quoted 39 lines
Reviewed-by Aurabindo Pillai <[email protected]>Signed-off-by Alex Hung <[email protected]>Signed-off-by Ray Wu <[email protected]>--- .../gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c | 6 ------ 1 file changed, 6 deletions(-)drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +0
-7@@ -2114,8 +2114,6 @@ static bool dcn32_resource_construct(#define REG_STRUCT dccg_regsdccg_regs_init (); -DC_FP_START (); - ctx->dc_bios->regs = &bios_regs; pool->base.res_cap = &res_cap_dcn32;@@ -2501,14 +2499,10 @@ static bool dcn32_resource_construct(if (ASICREV_IS_GC_11_0_3 (dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc ==0 )) dc->config.sdpif_request_limit_words_per_umc =16 ; -DC_FP_END (); -return true; create_fail: -DC_FP_END (); -dcn32_resource_destruct (pool);return false; --2.43.0
PATCH 19/28 drm/amd/display: Call FP Protect Before Mode Programming/Mode Support
In reply to Ray WuFrom: Austin Zheng <[email protected]>
[Why]
Memory allocation occurs within dml21_validate() for adding phantom planes. May cause kernel to be tainted due to usage of FP Start.
[How]
Move FP start from dml21_validate to before mode programming/mode support. Calculations requiring floating point are all done within mode programming or mode support.
Reviewed-by Alvin Lee <[email protected]>
Signed-off-by Austin Zheng <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +4 -4
@@ -234,7 +234,9 @@ static bool dml21_mode_check_and_programming(const struct dc *in_dc, struct dc_sif (!result)return false; +DC_FP_START (); result =dml2_build_mode_programming (mode_programming); +DC_FP_END ();if (!result)return false;
@@ -277,7 +279,9 @@ static bool dml21_check_mode_support(const struct dc *in_dc, struct dc_state *co mode_support->dml2_instance = dml_init->dml2_instance;dml21_map_dc_state_into_dml_display_cfg (in_dc, context, dml_ctx); dml_ctx->v21.mode_programming.dml2_instance->scratch.build_mode_programming_locals.mode_programming_params.programming = dml_ctx->v21.mode_programming.programming; +DC_FP_START (); is_supported =dml2_check_mode_supported (mode_support); +DC_FP_END ();if (!is_supported)return false;
@@ -288,16 +292,12 @@ bool dml21_validate(const struct dc *in_dc, struct dc_state *context, struct dml {bool out = false; -DC_FP_START (); -/* Use dml_validate_only for fast_validate path */ if (fast_validate) out =dml21_check_mode_support (in_dc, context, dml_ctx);else out =dml21_mode_check_and_programming (in_dc, context, dml_ctx); -DC_FP_END (); -return out; }
Signature · 1 line
2.43.0
PATCH 20/28 drm/amd/display: DML21 Fixes
In reply to Ray WuFrom: Austin Zheng <[email protected]>
- Store state related info inside mode_lib.
- Fix bad DCFCLK deep sleep
- Update FAMS structure in DMUB header
Reviewed-by Alvin Lee <[email protected]>
Signed-off-by Austin Zheng <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../amd/display/dc/dml2/dml21/inc/dml_top.h | 1 - .../dml21/inc/dml_top_soc_parameter_types.h | 1 + .../display/dc/dml2/dml21/inc/dml_top_types.h | 10 ++- .../src/dml2_core/dml2_core_dcn4_calcs.c | 7 +- .../src/dml2_core/dml2_core_shared_types.h | 82 ++++++++++++++++++- .../dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 3 - .../src/inc/dml2_internal_shared_types.h | 10 ++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 18 +++- 8 files changed, 117 insertions(+), 15 deletions(-)
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top.h +0 -1
@@ -43,5 +43,4 @@ bool dml2_build_mode_programming(struct dml2_build_mode_programming_in_out *in_o*/ bool dml2_build_mcache_programming (struct dml2_build_mcache_programming_in_out *in_out); -#endif
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h +1 -0
@@ -130,6 +130,7 @@ struct dml2_soc_state_table {struct dml2_soc_vmin_clock_limits {unsigned long dispclk_khz; +unsigned long dcfclk_khz; };struct dml2_soc_bb {
drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +9 -1
@@ -279,7 +279,10 @@ struct dml2_per_stream_programming { } phantom_stream;union dmub_cmd_fams2_config fams2_base_params; -union dmub_cmd_fams2_config fams2_sub_params; +union { +union dmub_cmd_fams2_config fams2_sub_params; +union dmub_fams2_stream_static_sub_state_v2 fams2_sub_params_v2; + }; };//-----------------
@@ -674,9 +677,14 @@ struct dml2_display_cfg_programming {// unlimited # of mcache struct dml2_mcache_surface_allocation non_optimized_mcache_allocation[DML2_MAX_PLANES ]; +bool failed_prefetch; +bool failed_uclk_pstate;bool failed_mcache_validation;bool failed_dpmm;bool failed_mode_programming; +bool failed_mode_programming_dcfclk; +bool failed_mode_programming_prefetch; +bool failed_mode_programming_flip;bool failed_map_watermarks; } informative; };
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +4 -3
@@ -7905,6 +7905,7 @@ static noinline_for_stack void dml_core_ms_prefetch_check(struct dml2_core_inter } +static bool dml_core_mode_support (struct dml2_core_calcs_mode_support_ex *in_out_params) {struct dml2_core_internal_display_mode_lib *mode_lib = in_out_params->mode_lib;
@@ -11880,7 +11881,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex }//Maximum Bandwidth Used - s->TotalWRBandwidth =0 ; + mode_lib->mp.TotalWRBandwidth =0 ;for (k =0 ; k < display_cfg->num_streams; ++k) { s->WRBandwidth =0 ;if (display_cfg->stream_descriptors[k].writeback.active_writebacks_per_stream >0 ) {
@@ -11889,7 +11890,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex (display_cfg->stream_descriptors[k].timing.h_total * display_cfg->stream_descriptors[k].writeback.writeback_stream[0 ].input_height / ((double )display_cfg->stream_descriptors[k].timing.pixel_clock_khz /1000 )) * (display_cfg->stream_descriptors[k].writeback.writeback_stream[0 ].pixel_format == dml2_444_32 ?4.0 :8.0 ); - s->TotalWRBandwidth = s->TotalWRBandwidth + s->WRBandwidth; + mode_lib->mp.TotalWRBandwidth = mode_lib->mp.TotalWRBandwidth + s->WRBandwidth; } }
@@ -13243,7 +13244,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.misc.DisplayPipeLineDeliveryTimeLumaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeLumaPrefetch[k]; out->informative.misc.DisplayPipeLineDeliveryTimeChromaPrefetch[k] = mode_lib->mp.DisplayPipeLineDeliveryTimeChromaPrefetch[k]; - out->informative.misc.WritebackRequiredBandwidth = mode_lib->scratch.dml_core_mode_programming_locals.TotalWRBandwidth /1000.0 ; + out->informative.misc.WritebackRequiredBandwidth = mode_lib->mp.TotalWRBandwidth /1000.0 ; out->informative.misc.WritebackAllowDRAMClockChangeEndPosition[k] = mode_lib->mp.WritebackAllowDRAMClockChangeEndPosition[k]; out->informative.misc.WritebackAllowFCLKChangeEndPosition[k] = mode_lib->mp.WritebackAllowFCLKChangeEndPosition[k]; out->informative.misc.DSCCLK_calculated[k] = mode_lib->mp.DSCCLK[k];
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h +81 -1
137 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +0 -3
@@ -389,9 +389,6 @@ static bool map_min_clocks_to_dpm(const struct dml2_core_mode_support_result *moif (result) result =round_up_to_next_dpm (&display_cfg->min_clocks.dcn4x.dispclk_khz, &state_table->dispclk); -if (result) - result =round_up_to_next_dpm (&display_cfg->min_clocks.dcn4x.deepsleep_dcfclk_khz, &state_table->dcfclk); -for (i =0 ; i <DML2_MAX_DCN_PIPES ; i++) {if (result) result =round_up_to_next_dpm (&display_cfg->plane_programming[i].min_clocks.dcn4x.dppclk_khz, &state_table->dppclk);
drivers/gpu/drm/amd/display/dc/dml2/dml21/src/inc/dml2_internal_shared_types.h +8 -2
@@ -202,6 +202,8 @@ struct dml2_core_mode_support_result { } active;unsigned int dispclk_khz; +unsigned int dpprefclk_khz; +unsigned int dtbrefclk_khz;unsigned int dcfclk_deepsleep_khz;unsigned int socclk_khz;
@@ -446,13 +448,17 @@ struct dml2_core_internal_state_intermediates { };struct dml2_core_mode_support_locals { -struct dml2_core_calcs_mode_support_ex mode_support_ex_params; +union { +struct dml2_core_calcs_mode_support_ex mode_support_ex_params; + };struct dml2_display_cfg svp_expanded_display_cfg;struct dml2_calculate_mcache_allocation_in_out calc_mcache_allocation_params; };struct dml2_core_mode_programming_locals { -struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; +union { +struct dml2_core_calcs_mode_programming_ex mode_programming_ex_params; + };struct dml2_display_cfg svp_expanded_display_cfg; };
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +14 -4
@@ -104,6 +104,14 @@*/ #define DMUB_MAX_FPO_STREAMS 4 +/* Define to ensure that the "common" members always appear in the same +* order in different structs for back compat purposes +*/ +#define COMMON_STREAM_STATIC_SUB_STATE \ + struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ + struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ + struct dmub_fams2_cmd_drr_stream_static_state drr; +/* Maximum number of streams on any ASIC. */ #define DMUB_MAX_STREAMS 6
@@ -1998,11 +2006,13 @@ union dmub_fams2_stream_static_sub_state { };//v0 union dmub_fams2_cmd_stream_static_sub_state { -struct dmub_fams2_cmd_legacy_stream_static_state legacy; -struct dmub_fams2_cmd_subvp_stream_static_state subvp; -struct dmub_fams2_cmd_drr_stream_static_state drr; + COMMON_STREAM_STATIC_SUB_STATE }; //v1 +union dmub_fams2_stream_static_sub_state_v2 { + COMMON_STREAM_STATIC_SUB_STATE +}; //v2 + struct dmub_fams2_stream_static_state { enum fams2_stream_type type; uint32_t otg_vline_time_ns;
@@ -2068,7 +2078,7 @@ struct dmub_fams2_cmd_stream_static_base_state {struct dmub_fams2_stream_static_state_v1 {struct dmub_fams2_cmd_stream_static_base_state base; -union dmub_fams2_cmd_stream_static_sub_state sub_state; +union dmub_fams2_stream_static_sub_state_v2 sub_state; };//v1 /**
Signature · 1 line
2.43.0
PATCH 21/28 drm/amd/display: Refactor SubVP cursor limiting logic
In reply to Ray WuFrom: Dillon Varone <[email protected]>
[WHY]
There are several gaps that can result in SubVP being enabled with incompatible HW cursor sizes, and unjust restrictions to cursor size due to wrong predictions on future usage of SubVP.
[HOW]
- remove "prediction" logic in favor of tagging based on previous SubVP usage
- block SubVP if current HW cursor settings are incompatible
- provide interface for DM to determine if HW cursor should be disabled due to an attempt to enable SubVP
Reviewed-by Alvin Lee <[email protected]>
Signed-off-by Dillon Varone <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/core/dc.c | 57 +++++++-- .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 + .../gpu/drm/amd/display/dc/core/dc_resource.c | 48 +------- .../gpu/drm/amd/display/dc/core/dc_state.c | 111 +++++++++++++++++- .../gpu/drm/amd/display/dc/core/dc_stream.c | 70 ++++++++--- drivers/gpu/drm/amd/display/dc/dc.h | 4 + .../gpu/drm/amd/display/dc/dc_state_priv.h | 20 ++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 10 ++ .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 1 + .../dc/dml2/dml21/dml21_translation_helper.c | 9 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +- .../gpu/drm/amd/display/dc/inc/core_status.h | 3 + .../gpu/drm/amd/display/dc/inc/core_types.h | 5 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 - .../dc/resource/dce100/dce100_resource.c | 4 +- .../dc/resource/dce110/dce110_resource.c | 4 +- .../dc/resource/dce112/dce112_resource.c | 4 +- .../dc/resource/dce112/dce112_resource.h | 2 +- .../dc/resource/dce60/dce60_resource.c | 4 +- .../dc/resource/dce80/dce80_resource.c | 4 +- .../dc/resource/dcn10/dcn10_resource.c | 5 +- .../dc/resource/dcn20/dcn20_resource.c | 6 +- .../dc/resource/dcn20/dcn20_resource.h | 2 +- .../dc/resource/dcn21/dcn21_resource.c | 6 +- .../dc/resource/dcn30/dcn30_resource.c | 4 +- .../dc/resource/dcn30/dcn30_resource.h | 2 +- .../dc/resource/dcn31/dcn31_resource.c | 4 +- .../dc/resource/dcn31/dcn31_resource.h | 2 +- .../dc/resource/dcn314/dcn314_resource.c | 4 +- .../dc/resource/dcn314/dcn314_resource.h | 2 +- .../dc/resource/dcn32/dcn32_resource.c | 66 +++++++++-- .../dc/resource/dcn32/dcn32_resource.h | 6 +- .../dc/resource/dcn321/dcn321_resource.c | 4 +- .../dc/resource/dcn35/dcn35_resource.c | 6 +- .../dc/resource/dcn351/dcn351_resource.c | 6 +- .../dc/resource/dcn36/dcn36_resource.c | 6 +- .../dc/resource/dcn401/dcn401_resource.c | 52 ++++++-- .../dc/resource/dcn401/dcn401_resource.h | 2 +- 39 files changed, 418 insertions(+), 135 deletions(-)
drivers/gpu/drm/amd/display/dc/core/dc.c +46 -11
@@ -37,6 +37,7 @@#include "dc_state.h" #include "dc_state_priv.h" #include "dc_plane_priv.h" +#include "dc_stream_priv.h" #include "gpio_service_interface.h" #include "clk_mgr.h"
@@ -2886,7 +2887,7 @@ static enum surface_update_type check_update_surfaces_for_stream(int i;enum surface_update_type overall_type =UPDATE_TYPE_FAST ; -if (dc->idle_optimizations_allowed) +if (dc->idle_optimizations_allowed ||dc_can_clear_cursor_limit (dc)) overall_type =UPDATE_TYPE_FULL ;if (stream_status ==NULL || stream_status->plane_count != surface_count)
@@ -3290,7 +3291,7 @@ static void copy_stream_update_to_stream(struct dc *dc,if (dsc_validate_context) { stream->timing.dsc_cfg = *update->dsc_config; stream->timing.flags.DSC = enable_dsc; -if (!dc->res_pool->funcs->validate_bandwidth (dc, dsc_validate_context, true)) { +if (dc->res_pool->funcs->validate_bandwidth (dc, dsc_validate_context, true) !=DC_OK ) { stream->timing.dsc_cfg = old_dsc_cfg; stream->timing.flags.DSC = old_dsc_enabled; update->dsc_config =NULL ;
@@ -3515,7 +3516,7 @@ static bool update_planes_and_stream_state(struct dc *dc, }if (update_type ==UPDATE_TYPE_FULL ) { -if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false)) { +if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK ) {BREAK_TO_DEBUGGER (); goto fail; }
@@ -4608,7 +4609,7 @@ static struct dc_state *create_minimal_transition_state(struct dc *dc,backup_and_set_minimal_pipe_split_policy (dc, base_context, policy);/* commit minimal state */ -if (dc->res_pool->funcs->validate_bandwidth (dc, minimal_transition_context, false)) { +if (dc->res_pool->funcs->validate_bandwidth (dc, minimal_transition_context, false) ==DC_OK ) {/* prevent underflow and corruption when reconfiguring pipes */ force_vsync_flip_in_minimal_transition_context (minimal_transition_context); }else {
@@ -5043,6 +5044,9 @@ static bool full_update_required(struct dc *dc,if (dc->idle_optimizations_allowed)return true; +if (dc_can_clear_cursor_limit (dc)) +return true; +return false; }
@@ -5128,7 +5132,7 @@ static bool update_planes_and_stream_v1(struct dc *dc,copy_stream_update_to_stream (dc, context, stream, stream_update);if (update_type >=UPDATE_TYPE_FULL ) { -if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false)) { +if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK ) {DC_ERROR ("Mode validation failed for stream update!\n" );dc_state_release (context);return false;
@@ -6272,15 +6276,22 @@ bool dc_abm_save_restore(void dc_query_current_properties (struct dc *dc,struct dc_current_properties *properties) {unsigned int i; -bool subvp_sw_cursor_req = false; +unsigned int max_cursor_size = dc->caps.max_cursor_size; +unsigned int stream_cursor_size; -for (i =0 ; i < dc->current_state->stream_count; i++) { -if (check_subvp_sw_cursor_fallback_req (dc, dc->current_state->streams[i]) && !dc->current_state->streams[i]->hw_cursor_req) { - subvp_sw_cursor_req = true; -break ; +if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { +for (i =0 ; i < dc->current_state->stream_count; i++) { + stream_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size (dc, + dc->current_state, + dc->current_state->streams[i]); + +if (stream_cursor_size < max_cursor_size) { + max_cursor_size = stream_cursor_size; + } } } - properties->cursor_size_limit = subvp_sw_cursor_req ?64 : dc->caps.max_cursor_size; + + properties->cursor_size_limit = max_cursor_size; }/**
@@ -6346,3 +6357,27 @@ unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context)else return 0 ; } + +bool dc_is_cursor_limit_pending (struct dc *dc) +{ +uint32_t i; + +for (i =0 ; i < dc->current_state->stream_count; i++) { +if (dc_stream_is_cursor_limit_pending (dc, dc->current_state->streams[i])) +return true; + } + +return false; +} + +bool dc_can_clear_cursor_limit (struct dc *dc) +{ +uint32_t i; + +for (i =0 ; i < dc->current_state->stream_count; i++) { +if (dc_state_can_clear_stream_cursor_subvp_limit (dc->current_state->streams[i], dc->current_state)) +return true; + } + +return false; +}
drivers/gpu/drm/amd/display/dc/core/dc_debug.c +2 -0
@@ -266,6 +266,8 @@ char *dc_status_to_str(enum dc_status status)return "Fail dp payload allocation" ;case DC_FAIL_DP_LINK_BANDWIDTH :return "Insufficient DP link bandwidth" ; +case DC_FAIL_HW_CURSOR_SUPPORT : +return "HW Cursor not supported" ;case DC_ERROR_UNEXPECTED :return "Unexpected error" ; }
drivers/gpu/drm/amd/display/dc/core/dc_resource.c +6 -42
72 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/core/dc_state.c +107 -4
137 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +55 -15
95 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/dc.h +4 -0
@@ -249,6 +249,7 @@ struct dc_caps {uint32_t i2c_speed_in_khz_hdcp;uint32_t dmdata_alloc_size;unsigned int max_cursor_size; +unsigned int max_buffered_cursor_size;unsigned int max_video_width;/* * max video plane width that can be safely assumed to be always
@@ -2608,4 +2609,7 @@ void dc_disable_accelerated_mode(struct dc *dc);bool dc_is_timing_changed (struct dc_stream_state *cur_stream,struct dc_stream_state *new_stream); +bool dc_is_cursor_limit_pending (struct dc *dc); +bool dc_can_clear_cursor_limit (struct dc *dc); +#endif /* DC_INTERFACE_H_ */
drivers/gpu/drm/amd/display/dc/dc_state_priv.h +20 -0
@@ -105,4 +105,24 @@ bool dc_state_is_fams2_in_use(const struct dc *dc, const struct dc_state *state); + +void dc_state_set_stream_subvp_cursor_limit (const struct dc_stream_state *stream, +struct dc_state *state, +bool limit); + +bool dc_state_get_stream_subvp_cursor_limit (const struct dc_stream_state *stream, +struct dc_state *state); + +void dc_state_set_stream_cursor_subvp_limit (const struct dc_stream_state *stream, +struct dc_state *state, +bool limit); + +bool dc_state_get_stream_cursor_subvp_limit (const struct dc_stream_state *stream, +struct dc_state *state); + +bool dc_state_can_clear_stream_cursor_subvp_limit (const struct dc_stream_state *stream, +struct dc_state *state); + +bool dc_state_is_subvp_in_use (struct dc_state *state); +#endif /* _DC_STATE_PRIV_H_ */
drivers/gpu/drm/amd/display/dc/dc_stream.h +10 -0
@@ -44,6 +44,8 @@ struct mall_stream_config {*/ enum mall_stream_type type;struct dc_stream_state *paired_stream;// master / slave stream +bool subvp_limit_cursor_size;/* stream has/is using subvp limiting hw cursor support */ +bool cursor_size_limit_subvp;/* stream is using hw cursor config preventing subvp */ };struct dc_stream_status {
@@ -503,6 +505,11 @@ void program_cursor_position(struct dc *dc, struct dc_stream_state *stream); +bool dc_stream_check_cursor_attributes ( +const struct dc_stream_state *stream, +struct dc_state *state, +const struct dc_cursor_attributes *attributes); +bool dc_stream_set_cursor_attributes (struct dc_stream_state *stream,const struct dc_cursor_attributes *attributes);
@@ -580,4 +587,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,struct dc_surface_update *srf_updates, struct dc_state *context); +bool dc_stream_is_cursor_limit_pending (struct dc *dc,struct dc_stream_state *stream); +bool dc_stream_can_clear_cursor_limit (struct dc *dc,struct dc_stream_state *stream); +#endif /* DC_STREAM_H_ */
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c +1 -0
@@ -627,6 +627,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,*/ if (pipe->plane_state && !pipe->top_pipe && !pipe->prev_odm_pipe && !dcn32_is_center_timing(pipe) && !pipe->stream->hw_cursor_req && + !dc_state_get_stream_cursor_subvp_limit(pipe->stream, context) && !(pipe->stream->timing.pix_clk_100hz / 10000 > DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ) && (!dcn32_is_psr_capable(pipe) || (context->stream_count == 1 && dc->caps.dmub_caps.subvp_psr)) && dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_NONE &&
drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +6 -3
@@ -526,7 +526,8 @@ static void populate_dml21_output_config_from_stream_state(struct dml2_link_outpstatic void populate_dml21_stream_overrides_from_stream_state (struct dml2_stream_parameters *stream_desc, -struct dc_stream_state *stream) +struct dc_stream_state *stream, +struct dc_stream_status *stream_status) {switch (stream->debug.force_odm_combine_segments) {case 0 :
@@ -551,7 +552,9 @@ static void populate_dml21_stream_overrides_from_stream_state(if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy || stream->debug.force_odm_combine_segments >0 ) stream_desc->overrides.disable_dynamic_odm = true; - stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req; + stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || + stream->hw_cursor_req || + stream_status->mall_stream_config.cursor_size_limit_subvp; }static enum dml2_swizzle_mode gfx_addr3_to_dml2_swizzle_mode (enum swizzle_mode_addr3_values addr3_mode)
@@ -1024,7 +1027,7 @@ bool dml21_map_dc_state_into_dml_display_cfg(const struct dc *in_dc, struct dc_spopulate_dml21_timing_config_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, context->streams[stream_index], dml_ctx);adjust_dml21_hblank_timing_config_from_pipe_ctx (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].timing, &context->res_ctx.pipe_ctx[stream_index]);populate_dml21_output_config_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location].output, context->streams[stream_index], &context->res_ctx.pipe_ctx[stream_index]); -populate_dml21_stream_overrides_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index]); +populate_dml21_stream_overrides_from_stream_state (&dml_dispcfg->stream_descriptors[disp_cfg_stream_location], context->streams[stream_index], &context->stream_status[stream_index]); dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.fclk_pstate = dml2_twait_budgeting_setting_if_needed; dml_dispcfg->stream_descriptors[disp_cfg_stream_location].overrides.hw.twait_budgeting.uclk_pstate = dml2_twait_budgeting_setting_if_needed;
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +1 -1
@@ -2482,7 +2482,7 @@ bool dcn20_update_bandwidth(struct dce_hwseq *hws = dc->hwseq;/* recalculate DML parameters */ -if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false)) +if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK )return false;/* apply updated bandwidth parameters */
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +1 -1
@@ -2651,7 +2651,7 @@ bool dcn401_update_bandwidth(struct dce_hwseq *hws = dc->hwseq;/* recalculate DML parameters */ -if (!dc->res_pool->funcs->validate_bandwidth (dc, context, false)) +if (dc->res_pool->funcs->validate_bandwidth (dc, context, false) !=DC_OK )return false;/* apply updated bandwidth parameters */
drivers/gpu/drm/amd/display/dc/inc/core_status.h +3 -0
@@ -26,6 +26,8 @@#ifndef _CORE_STATUS_H_#define _CORE_STATUS_H_ +#include "dc_hw_types.h" +enum dc_status { DC_OK = 1,
@@ -56,6 +58,7 @@ enum dc_status {DC_NO_LINK_ENC_RESOURCE =26 ,DC_FAIL_DP_PAYLOAD_ALLOCATION =27 ,DC_FAIL_DP_LINK_BANDWIDTH =28 , +DC_FAIL_HW_CURSOR_SUPPORT =29 , DC_ERROR_UNEXPECTED = -1 };
drivers/gpu/drm/amd/display/dc/inc/core_types.h +4 -1
@@ -78,7 +78,7 @@ struct resource_funcs {/* Create a minimal link encoder object with no dc_link object * associated with it. */ struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx,enum engine_id eng_id); -bool (*validate_bandwidth)( +enum dc_status (*validate_bandwidth)(struct dc *dc,struct dc_state *context,bool fast_validate);
@@ -217,6 +217,9 @@ struct resource_funcs {int (*get_power_profile)(const struct dc_state *context);unsigned int (*get_det_buffer_size)(const struct dc_state *context);unsigned int (*get_vstartup_for_pipe)(struct pipe_ctx *pipe_ctx); +unsigned int (*get_max_hw_cursor_size)(const struct dc *dc, +struct dc_state *state, +const struct dc_stream_state *stream); };struct audio_support {
drivers/gpu/drm/amd/display/dc/inc/resource.h +0 -2
@@ -628,8 +628,6 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,struct dc_state *context, struct pipe_ctx *pipe_ctx); -bool check_subvp_sw_cursor_fallback_req (const struct dc *dc,struct dc_stream_state *stream); -/* Get hw programming parameters container from pipe context * @pipe_ctx: pipe context * @dscl_prog_data: struct to hold programmable hw reg values
drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c +2 -2
@@ -836,7 +836,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -static bool dce100_validate_bandwidth ( +static enum dc_status dce100_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -858,7 +858,7 @@ static bool dce100_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return true; +return DC_OK ; } static bool dce100_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c +2 -2
@@ -960,7 +960,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -static bool dce110_validate_bandwidth ( +static enum dc_status dce110_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -1031,7 +1031,7 @@ static bool dce110_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz, context->bw_ctx.bw.dce.blackout_recovery_time_us); } -return result; +return result ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; } static enum dc_status dce110_validate_plane(const struct dc_plane_state *plane_state,
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c +2 -2
@@ -883,7 +883,7 @@ static enum dc_status build_mapped_resource(return DC_OK ; } -bool dce112_validate_bandwidth ( +enum dc_status dce112_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -952,7 +952,7 @@ bool dce112_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz, context->bw_ctx.bw.dce.blackout_recovery_time_us); } -return result; +return result ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; } enum dc_status resource_map_phy_clock_resources(
drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.h +1 -1
@@ -42,7 +42,7 @@ enum dc_status dce112_validate_with_context(struct dc_state *context, struct dc_state *old_context); -bool dce112_validate_bandwidth ( +enum dc_status dce112_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c +2 -2
@@ -863,7 +863,7 @@ static void dce60_resource_destruct(struct dce110_resource_pool *pool) } } -static bool dce60_validate_bandwidth ( +static enum dc_status dce60_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -885,7 +885,7 @@ static bool dce60_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return true; +return DC_OK ; } static bool dce60_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c +2 -2
@@ -869,7 +869,7 @@ static void dce80_resource_destruct(struct dce110_resource_pool *pool) } } -static bool dce80_validate_bandwidth ( +static enum dc_status dce80_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -891,7 +891,7 @@ static bool dce80_validate_bandwidth( context->bw_ctx.bw.dce.yclk_khz =0 ; } -return true; +return DC_OK ; } static bool dce80_validate_surface_sets(
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +3 -2
@@ -23,6 +23,7 @@* */ +#include "core_status.h" #include "dm_services.h" #include "dc.h"
@@ -1125,7 +1126,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool) *pool =NULL ; } -static bool dcn10_validate_bandwidth ( +static enum dc_status dcn10_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate)
@@ -1136,7 +1137,7 @@ static bool dcn10_validate_bandwidth( voltage_supported =dcn_validate_bandwidth (dc, context, fast_validate);DC_FP_END (); -return voltage_supported; +return voltage_supported ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }static enum dc_status dcn10_validate_plane (const struct dc_plane_state *plane_state,struct dc_caps *caps)
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +3 -3
@@ -2124,7 +2124,7 @@ bool dcn20_fast_validate_bw(return out; } -bool dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context, +enum dc_status dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {bool voltage_supported;
@@ -2132,14 +2132,14 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, pipes =kcalloc (dc->res_pool->pipe_count,sizeof (display_e2e_pipe_params_st),GFP_KERNEL );if (!pipes) -return false; +return DC_FAIL_BANDWIDTH_VALIDATE ;DC_FP_START (); voltage_supported =dcn20_validate_bandwidth_fp (dc, context, fast_validate, pipes);DC_FP_END ();kfree (pipes); -return voltage_supported; +return voltage_supported ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; } struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +1 -1
@@ -119,7 +119,7 @@ void dcn20_set_mcif_arb_params(struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt); -bool dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); +enum dc_status dcn20_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);void dcn20_merge_pipes_for_validate (struct dc *dc,struct dc_state *context);
drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +3 -3
@@ -923,7 +923,7 @@ bool dcn21_fast_validate_bw(struct dc *dc,* with DC_FP_START()/DC_FP_END(). Use the same approach as for * dcn20_validate_bandwidth in dcn20_resource.c. */ -static bool dcn21_validate_bandwidth (struct dc *dc,struct dc_state *context, +static enum dc_status dcn21_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {bool voltage_supported;
@@ -931,14 +931,14 @@ static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context, pipes =kcalloc (dc->res_pool->pipe_count,sizeof (display_e2e_pipe_params_st),GFP_KERNEL );if (!pipes) -return false; +return DC_FAIL_BANDWIDTH_VALIDATE ;DC_FP_START (); voltage_supported =dcn21_validate_bandwidth_fp (dc, context, fast_validate, pipes);DC_FP_END ();kfree (pipes); -return voltage_supported; +return voltage_supported ?DC_OK :DC_NOT_SUPPORTED ; }static void dcn21_destroy_resource_pool (struct resource_pool **pool)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +2 -2
@@ -2035,7 +2035,7 @@ void dcn30_calculate_wm_and_dlg(DC_FP_END (); } -bool dcn30_validate_bandwidth (struct dc *dc, +enum dc_status dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -2092,7 +2092,7 @@ bool dcn30_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }void dcn30_update_bw_bounding_box (struct dc *dc,struct clk_bw_params *bw_params)
drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.h +1 -1
@@ -56,7 +56,7 @@ unsigned int dcn30_calc_max_scaled_time(enum mmhubbub_wbif_mode mode, unsigned int urgent_watermark); -bool dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context, +enum dc_status dcn30_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); bool dcn30_internal_validate_bw( struct dc *dc,
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +2 -2
@@ -1758,7 +1758,7 @@ dcn31_set_mcif_arb_params(struct dc *dc,DC_FP_END (); } -bool dcn31_validate_bandwidth (struct dc *dc, +enum dc_status dcn31_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1813,7 +1813,7 @@ bool dcn31_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }static void dcn31_get_panel_config_defaults (struct dc_panel_config *panel_config)
drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.h +1 -1
@@ -37,7 +37,7 @@ struct dcn31_resource_pool {struct resource_pool base; }; -bool dcn31_validate_bandwidth (struct dc *dc, +enum dc_status dcn31_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate); void dcn31_calculate_wm_and_dlg(
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +2 -2
@@ -1694,7 +1694,7 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi *panel_config = panel_config_defaults; } -bool dcn314_validate_bandwidth (struct dc *dc, +enum dc_status dcn314_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1750,7 +1750,7 @@ bool dcn314_validate_bandwidth(struct dc *dc,BW_VAL_TRACE_FINISH (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }static struct resource_funcs dcn314_res_pool_funcs = {
drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.h +1 -1
@@ -39,7 +39,7 @@ struct dcn314_resource_pool {struct resource_pool base; }; -bool dcn314_validate_bandwidth (struct dc *dc, +enum dc_status dcn314_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +59 -7
103 lines not on this page · raw message
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +5 -1
@@ -98,7 +98,7 @@ void dcn32_add_phantom_pipes(struct dc *dc,unsigned int pipe_cnt, unsigned int index); -bool dcn32_validate_bandwidth (struct dc *dc, +enum dc_status dcn32_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
@@ -188,6 +188,10 @@ void dcn32_override_min_req_dcfclk(struct dc *dc, struct dc_state *context);unsigned int dcn32_calculate_mall_ways_from_bytes (const struct dc *dc,unsigned int total_size_in_mall_bytes); +unsigned int dcn32_get_max_hw_cursor_size (const struct dc *dc, +struct dc_state *state, +const struct dc_stream_state *stream); +/* definitions for run time init of reg offsets */ /* CLK SRC */
drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +3 -1
@@ -1624,7 +1624,8 @@ static struct resource_funcs dcn321_res_pool_funcs = { .add_phantom_pipes = dcn32_add_phantom_pipes, .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, - .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe + .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe, + .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size, };static uint32_t read_pipe_fuses (struct dc_context *ctx)
@@ -1709,6 +1710,7 @@ static bool dcn321_resource_construct( dc->caps.i2c_speed_in_khz_hdcp =100 ;/*1.4 w/a applied by default*/ /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ dc->caps.max_cursor_size =64 ; + dc->caps.max_buffered_cursor_size =64 ;// sqrt(16 * 1024 / 4) dc->caps.min_horizontal_blanking_period =80 ; dc->caps.dmdata_alloc_size =2048 ; dc->caps.mall_size_per_mem_channel =4 ;
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +3 -3
@@ -1732,7 +1732,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static bool dcn35_validate_bandwidth (struct dc *dc, +static enum dc_status dcn35_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1743,13 +1743,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }enum dc_status dcn35_patch_unknown_plane_state (struct dc_plane_state *plane_state)
drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +3 -3
@@ -1712,7 +1712,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static bool dcn351_validate_bandwidth (struct dc *dc, +static enum dc_status dcn351_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1723,13 +1723,13 @@ static bool dcn351_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }static struct resource_funcs dcn351_res_pool_funcs = {
drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c +3 -3
@@ -1713,7 +1713,7 @@ static void dcn35_get_panel_config_defaults(struct dc_panel_config *panel_config } -static bool dcn35_validate_bandwidth (struct dc *dc, +static enum dc_status dcn35_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate) {
@@ -1724,13 +1724,13 @@ static bool dcn35_validate_bandwidth(struct dc *dc, fast_validate);if (fast_validate) -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ;DC_FP_START ();dcn35_decide_zstate_support (dc, context);DC_FP_END (); -return out; +return out ?DC_OK :DC_FAIL_BANDWIDTH_VALIDATE ; }
drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +45 -7
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drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +1 -1
@@ -22,7 +22,7 @@ struct resource_pool *dcn401_create_resource_pool(enum dc_status dcn401_patch_unknown_plane_state (struct dc_plane_state *plane_state); -bool dcn401_validate_bandwidth (struct dc *dc, +enum dc_status dcn401_validate_bandwidth (struct dc *dc,struct dc_state *context,bool fast_validate);
Signature · 1 line
2.43.0
PATCH 22/28 drm/amd/display: Shift DMUB AUX reply command if necessary
In reply to Ray WuFrom: Wayne Lin <[email protected]>
[Why]
Defined value of dmub AUX reply command field get updated but didn't adjust dm receiving side accordingly.
[How]
Check the received reply command value to see if it's updated version or not. Adjust it if necessary.
Fixes ead08b95fa50 ("drm/amd/display: Fix race condition in DPIA AUX transfer")
Reviewed-by Ray Wu <[email protected]>
Signed-off-by Wayne Lin <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +4 -1
@@ -12852,8 +12852,11 @@ int amdgpu_dm_process_dmub_aux_transfer_sync( goto out; } + payload->reply[0 ] = adev->dm.dmub_notify->aux_reply.command &0xF ; +if (adev->dm.dmub_notify->aux_reply.command &0xF0 ) +/* The reply is stored in the top nibble of the command. */ + payload->reply[0 ] = (adev->dm.dmub_notify->aux_reply.command >>4 ) &0xF ; - payload->reply[0 ] = adev->dm.dmub_notify->aux_reply.command;if (!payload->write && p_notify->aux_reply.length && (payload->reply[0 ] ==AUX_TRANSACTION_REPLY_AUX_ACK )) {
Signature · 1 line
2.43.0
PATCH 23/28 drm/amd/display: Fix the checking condition in dmub aux handling
In reply to Ray WuFrom: Wayne Lin <[email protected]>
[Why & How]
Fix the checking condition for detecting AUX_RET_ERROR_PROTOCOL_ERROR. It was wrongly checking by "not equals to"
Reviewed-by Ray Wu <[email protected]>
Signed-off-by Wayne Lin <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 -1
@@ -12843,7 +12843,7 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(* Transient states before tunneling is enabled could * lead to this error. We can ignore this for now. */ -if (p_notify->result !=AUX_RET_ERROR_PROTOCOL_ERROR ) { +if (p_notify->result ==AUX_RET_ERROR_PROTOCOL_ERROR ) {drm_warn (adev_to_drm (adev),"DPIA AUX failed on 0x%x(%d), error %d\n" , payload->address, payload->length, p_notify->result);
Signature · 1 line
2.43.0
PATCH 24/28 drm/amd/display: Remove incorrect checking in dmub aux handler
In reply to Ray WuFrom: Wayne Lin <[email protected]>
[Why & How]
"Request length != reply length" is expected behavior defined in spec. It's not an invalid reply. Besides, replied data handling logic is not designed to be written in amdgpu_dm_process_dmub_aux_transfer_sync(). Remove the incorrectly handling section.
Fixes ead08b95fa50 ("drm/amd/display: Fix race condition in DPIA AUX transfer")
Reviewed-by Ray Wu <[email protected]>
Signed-off-by Wayne Lin <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 -11
@@ -12858,19 +12858,9 @@ int amdgpu_dm_process_dmub_aux_transfer_sync( payload->reply[0 ] = (adev->dm.dmub_notify->aux_reply.command >>4 ) &0xF ;if (!payload->write && p_notify->aux_reply.length && - (payload->reply[0 ] ==AUX_TRANSACTION_REPLY_AUX_ACK )) { - -if (payload->length != p_notify->aux_reply.length) { -drm_warn (adev_to_drm (adev),"invalid read length %d from DPIA AUX 0x%x(%d)!\n" , - p_notify->aux_reply.length, - payload->address, payload->length); - *operation_result =AUX_RET_ERROR_INVALID_REPLY ; - goto out; - } - + (payload->reply[0 ] ==AUX_TRANSACTION_REPLY_AUX_ACK ))memcpy (payload->data, p_notify->aux_reply.data, p_notify->aux_reply.length); - }/* success */ ret = p_notify->aux_reply.length;
Signature · 1 line
2.43.0
PATCH 25/28 drm/amd/display: Copy AUX read reply data whenever length > 0
In reply to Ray WuFrom: Wayne Lin <[email protected]>
[Why]amdgpu_dm_process_dmub_aux_transfer_sync() should return all exact data reply from the sink side. Don't do the analysis job in it.
[How]
Remove unnecessary check condition AUX_TRANSACTION_REPLY_AUX_ACK.
Fixes ead08b95fa50 ("drm/amd/display: Fix race condition in DPIA AUX transfer")
Reviewed-by Ray Wu <[email protected]>
Signed-off-by Wayne Lin <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +1 -2
@@ -12857,8 +12857,7 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(/* The reply is stored in the top nibble of the command. */ payload->reply[0 ] = (adev->dm.dmub_notify->aux_reply.command >>4 ) &0xF ; -if (!payload->write && p_notify->aux_reply.length && - (payload->reply[0 ] ==AUX_TRANSACTION_REPLY_AUX_ACK )) +if (!payload->write && p_notify->aux_reply.length)memcpy (payload->data, p_notify->aux_reply.data, p_notify->aux_reply.length);
Signature · 1 line
2.43.0
PATCH 26/28 drm/amd/display: Fix wrong handling for AUX_DEFER case
In reply to Ray WuFrom: Wayne Lin <[email protected]>
[Why]
We incorrectly ack all bytes get written when the reply actually is defer. When it's defer, means sink is not ready for the request. We should retry the request.
[How]
Only reply all data get written when receive I2C_ACK|AUX_ACK. Otherwise, reply the number of actual written bytes received from the sink. Add some messages to facilitate debugging as well.
Fixes ad6756b4d773 ("drm/amd/display: Shift dc link aux to aux_payload")
Reviewed-by Ray Wu <[email protected]>
Signed-off-by Wayne Lin <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-)
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +24 -4
@@ -51,6 +51,9 @@#define PEAK_FACTOR_X1000 1006 +/* +* This function handles both native AUX and I2C-Over-AUX transactions. +*/ static ssize_t dm_dp_aux_transfer (struct drm_dp_aux *aux,struct drm_dp_aux_msg *msg) {
@@ -87,15 +90,25 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,if (adev->dm.aux_hpd_discon_quirk) {if (msg->address ==DP_SIDEBAND_MSG_DOWN_REQ_BASE && operation_result ==AUX_RET_ERROR_HPD_DISCON ) { - result =0 ; + result = msg->size; operation_result =AUX_RET_SUCCESS ; } } -if (payload.write && result >=0 ) - result = msg->size; +/* +* result equals to 0 includes the cases of AUX_DEFER/I2C_DEFER +*/ +if (payload.write && result >=0 ) { +if (result) { +/*one byte indicating partially written bytes. Force 0 to retry*/ +drm_info (adev_to_drm (adev),"amdgpu: AUX partially written\n" ); + result =0 ; + }else if (!payload.reply[0 ]) +/*I2C_ACK|AUX_ACK*/ + result = msg->size; + } -if (result <0 ) +if (result <0 ) {switch (operation_result) {case AUX_RET_SUCCESS :break ;
@@ -114,6 +127,13 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux,break ; } +drm_info (adev_to_drm (adev),"amdgpu: DP AUX transfer fail:%d\n" , operation_result); + } + +if (payload.reply[0 ]) +drm_info (adev_to_drm (adev),"amdgpu: AUX reply command not ACK: 0x%02x." , + payload.reply[0 ]); +return result; }
Signature · 1 line
2.43.0
PATCH 27/28 drm/amd/display: Assign preferred stream encoder instance to dpia
In reply to Ray WuFrom: Meenakshikumar Somasundaram <[email protected]>
[Why]
For dpia, preferred engine instance availability is not checked when assigning stream encoder instance.
[How]
Check for dpia preferred engine id and assign the same stream encoder instance for the stream if available.
Reviewed-by PeiChen Huang <[email protected]>
Signed-off-by Meenakshikumar Somasundaram <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- .../gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +4 -0
@@ -1246,6 +1246,10 @@ struct stream_encoder *dcn10_find_first_free_match_stream_enc_for_link(if (link->ep_type ==DISPLAY_ENDPOINT_PHY && pool->stream_enc[i]->id == link->link_enc->preferred_engine)return pool->stream_enc[i]; + +if (link->ep_type ==DISPLAY_ENDPOINT_USB4_DPIA && pool->stream_enc[i]->id == + link->dpia_preferred_eng_id) +return pool->stream_enc[i]; } }
Signature · 1 line
2.43.0
PATCH 28/28 drm/amd/display: Only wait for required free space in DMUB mailbox
In reply to Ray WuFrom: Dillon Varone <[email protected]>
[WHY&HOW]
When command submission is blocked by a full mailbox, only wait for enough space to free to submit the command, instead of waiting for idle.
Reviewed-by Nicholas Kazlauskas <[email protected]>
Signed-off-by Dillon Varone <[email protected]>
Signed-off-by Ray Wu <[email protected]>
--- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++++ .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 72 ++++++++++++++----- 3 files changed, 76 insertions(+), 17 deletions(-)
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +1 -1
@@ -207,7 +207,7 @@ static bool dc_dmub_srv_fb_cmd_list_queue_execute(struct dc_dmub_srv *dc_dmub_srreturn false;do { - status =dmub_srv_wait_for_idle (dmub,100000 ); + status =dmub_srv_wait_for_inbox_free (dmub,100000 , count - i); }while (dc_dmub_srv->ctx->dc->debug.disable_timeout && status !=DMUB_STATUS_OK );/* Requeue the command. */
drivers/gpu/drm/amd/display/dmub/dmub_srv.h +19 -0
@@ -1034,4 +1034,23 @@ void dmub_srv_cmd_get_response(struct dmub_srv *dmub,*/ enum dmub_status dmub_srv_sync_inboxes (struct dmub_srv *dmub); +/** +* dmub_srv_wait_for_inbox_free() - Waits for space in the DMUB inbox to free up +* @dmub: the dmub service +* @timeout_us: the maximum number of microseconds to wait +* @num_free_required: number of free entries required +* +* Waits until the DMUB buffer is freed to the specified number. +* The maximum wait time is given in microseconds to prevent spinning +* forever. +* +* Return: +* DMUB_STATUS_OK - success +* DMUB_STATUS_TIMEOUT - wait for buffer to flush timed out +* DMUB_STATUS_INVALID - unspecified error +*/ +enum dmub_status dmub_srv_wait_for_inbox_free (struct dmub_srv *dmub, +uint32_t timeout_us, +uint32_t num_free_required); +#endif /* _DMUB_SRV_H_ */
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c +56 -16
91 lines not on this page · raw message
Signature · 1 line
2.43.0
[Public]
Hi all,
This week this patchset was tested on 4 systems, two dGPU and two APU based, and tested across multiple display and connection types.
APU
* Single Display eDP -> 1080p 60hz, 2560x1600 120hz, 1920x1200 165hz
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multi display -> eDP + DP/HDMI/USB-C -> 1080p 60hz eDP + 4k 144hz, 4k 240hz (Includes USB-C to DP/HDMI adapters)
* Thunderbolt -> LG Ultrafine 5k
* MST DSC -> Cable Matters 101075 (DP to 3x DP) with 3x 4k60hz displays, HP Hook G2 with 2x 4k60hz displays
* USB 4 -> HP Hook G4, Lenovo Thunderbolt Dock, both with 2x 4k60hz DP and 1x 4k60hz HDMI displays
* SST PCON -> Club3D CAC-1085 + 1x 4k 144hz, FRL3, at a max resolution supported by the dongle of 4k 120hz YUV420 12bpc.
* MST PCON -> 1x 4k 144hz, FRL3, at a max resolution supported by the adapter of 4k 120hz RGB 8bpc.
DGPU
* Single Display DP (SST DSC) -> 4k144hz, 4k240hz
* Multiple Display DP -> 4k240hz + 4k144hz
* MST (Startech MST14DP123DP [DP to 3x DP] and 2x 4k 60hz displays)
* MST DSC (with Cable Matters 101075 [DP to 3x DP] with 3x 4k60hz displays)
The testing is a mix of automated and manual tests. Manual testing includes (but is not limited to)
* Changing display configurations and settings
* Video/Audio playback
* Benchmark testing
* Suspend/Resume testing
* Feature testing (Freesync, HDCP, etc.)
Automated testing includes (but is not limited to)
* Script testing (scripts to automate some of the manual checks)
* IGT testing
The testing is mainly tested on the following displays, but occasionally there are tests with other displays
* Samsung G8 Neo 4k240hz
* Samsung QN55QN95B 4k 120hz
* Acer XV322QKKV 4k144hz
* HP U27 4k Wireless 4k60hz
* LG 27UD58B 4k60hz
* LG 32UN650WA 4k60hz
* LG Ultrafine 5k 5k60hz
* AU Optronics B140HAN01.1 1080p 60hz eDP
* AU Optronics B160UAN01.J 1920x1200 165hz eDP
* AU Optronics B160QAN02.L 2560x1600 120hz eDP
The patchset consists of the amd-staging-drm-next branch (Head commit - b5383f917c59e8a5e61f469bb41dc8c826258d92 -> drm/amdgpu/mes: remove more unused functions) with new patches added on top of it.
Tested on Ubuntu 24.04.1, on Wayland and X11, using KDE Plasma and Gnome.
Tested-by Daniel Wheeler <[email protected]>
Thank you,
Dan Wheeler
Sr. Technologist | AMD
SW Display
------------------------------------------------------------------------------------------------------------------
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
Facebook | Twitter | amd.com
-----Original Message-----
From: Ray Wu <[email protected]>
Sent: Monday, April 28, 2025 9:51 AM
To: [email protected]
Cc: Wentland, Harry <[email protected]>; Li, Sun peng (Leo) <[email protected]>; Pillai, Aurabindo <[email protected]>; Li, Roman <[email protected]>; Lin, Wayne <[email protected]>; Chung, ChiaHsuan (Tom) <[email protected]>; Zuo, Jerry <[email protected]>; Mohamed, Zaeem <[email protected]>; Wheeler, Daniel <[email protected]>; Hung, Alex <[email protected]>; Wu, Ray <[email protected]>
Subject: [PATCH 00/28] DC Patches May 05 2025
This DC patchset brings improvements in multiple areas. In summary, we highlight:
- Update IPS checks to properly include all ASICs.
- Refactoring DSC enum dsc_bits_per_comp
- Remove redundant NULL check
- Revert "Refactor SubVP cursor limiting logic"
- Disable DPP RCG before DPP CLK enable
- Add skip rIOMMU dc config option
- Fix race condition in DPIA AUX transfer
- Refactor SubVP cursor limiting logic
Cc Daniel Wheeler <[email protected]>
Alex Hung (2):
drm/amd/display: Remove redundant null check drm/amd/display: Remove unnecessary DC_FP_START/DC_FP_END
Aurabindo Pillai (1):
drm/amd/display: more liberal vmin/vmax update for freesync
Austin Zheng (2):
drm/amd/display: Call FP Protect Before Mode Programming/Mode Support drm/amd/display: DML21 Fixes
Bhuvanachandra Pinninti (1):
drm/amd/display: Refactoring DSC enum dsc_bits_per_comp.
Charlene Liu (2):
drm/amd/display: allow dscclk disable drm/amd/display: disable DPP RCG before DPP CLK enable
Dillon Varone (2):
drm/amd/display: Refactor SubVP cursor limiting logic drm/amd/display: Only wait for required free space in DMUB mailbox
Dominik Kaszewski (1):
drm/amd/display: Prepare for Fused I2C-over-AUX
Jesse Agate (1):
drm/amd/display: Always Scale Flag
JinZe Xu (1):
drm/amd/display: Send IPSExit unconditionally.
Kevin Gao (1):
drm/amd/display: Add skip rIOMMU dc config option
Leo Li (1):
drm/amd/display: Allow 0 dtbclk for DCN35 and above
Meenakshikumar Somasundaram (1):
drm/amd/display: Assign preferred stream encoder instance to dpia
Nicholas Kazlauskas (1):
Revert "drm/amd/display: turn off eDP lcdvdd and backlight if not
required"
Ovidiu Bunea (1):
drm/amd/display: Update IPS sequential_ono requirement checks
Roman Li (1):
drm/amd/display: Fix invalid context error in dml helper
Ryan Seto (1):
Revert "drm/amd/display: Refactor SubVP cursor limiting logic"
Taimur Hassan (3):
drm/amd/display: Promote DAL to 3.2.330
drm/amd/display: [FW Promotion] Release 0.1.8.0
drm/amd/display: Promote DAL to 3.2.331
Wayne Lin (5):
drm/amd/display: Shift DMUB AUX reply command if necessary drm/amd/display: Fix the checking condition in dmub aux handling drm/amd/display: Remove incorrect checking in dmub aux handler drm/amd/display: Copy AUX read reply data whenever length > 0 drm/amd/display: Fix wrong handling for AUX_DEFER case
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 +++++----- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 28 ++++++- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +- .../gpu/drm/amd/display/dc/core/dc_state.c | 15 +++- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 17 ++-- drivers/gpu/drm/amd/display/dc/dc_fused_io.c | 12 ++- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 62 ++++++++------ .../amd/display/dc/dml2/dml21/dml21_wrapper.c | 8 +- .../amd/display/dc/dml2/dml21/inc/dml_top.h | 1 - .../dml21/inc/dml_top_soc_parameter_types.h | 1 + .../display/dc/dml2/dml21/inc/dml_top_types.h | 10 ++- .../src/dml2_core/dml2_core_dcn4_calcs.c | 7 +- .../src/dml2_core/dml2_core_shared_types.h | 82 ++++++++++++++++++- .../dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 3 - .../src/inc/dml2_internal_shared_types.h | 10 ++- .../display/dc/dml2/dml2_translation_helper.c | 14 ++-- .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 2 +- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 7 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 6 ++ .../amd/display/dc/dsc/dcn401/dcn401_dsc.c | 6 -- .../display/dc/hubbub/dcn21/dcn21_hubbub.c | 6 +- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 21 +++-- .../gpu/drm/amd/display/dc/inc/core_types.h | 1 - .../link/protocols/link_edp_panel_control.c | 2 - .../dc/resource/dcn10/dcn10_resource.c | 4 + .../dc/resource/dcn32/dcn32_resource.c | 7 +- .../dc/resource/dcn321/dcn321_resource.c | 1 + .../dc/resource/dcn35/dcn35_resource.c | 2 +- .../dc/resource/dcn36/dcn36_resource.c | 2 +- .../dc/resource/dcn401/dcn401_resource.c | 3 +- drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c | 25 +++--- drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 19 +++++ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 24 ++++-- .../gpu/drm/amd/display/dmub/src/dmub_srv.c | 72 ++++++++++++---- 35 files changed, 372 insertions(+), 165 deletions(-)
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2.43.0