drm: sun4i: add Display Engine 3.3 (DE33) support
Subsystems (7)
v11 cover drm: sun4i: add Display Engine 3.3 (DE33) support
Hi All,
v11 of this patch adding support for the Allwinner DE33 display engine. This version removes the clock dt-binding and ccu driver support that Chen-Yu has also taken as a subset, and as suggested removes the bus dt-binding patch which will be sent with the device-tree changes to enable downstream device support subsequently.
Use of lower-case for an enum is also corrected and Maxime's Acked-by added. I also noticed a couple of other ordering issues while fixing the enum, and have also corrected these so that the intermediate patches all compile, but no code changes, so the end result of applying this series (now on top of clk-next) is unchanged.
Regards,
Ryan
Jernej Skrabec (7):
drm: sun4i: de2/de3: add mixer version enum
drm: sun4i: de2/de3: refactor mixer initialisation
drm: sun4i: de2/de3: add generic blender register reference function
drm: sun4i: de2/de3: use generic register reference function for layer
configuration
drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
drm: sun4i: de33: mixer: add mixer configuration for the H616
Ryan Walklin (1):
dt-bindings: allwinner: add H616 DE33 mixer binding
.../allwinner,sun8i-a83t-de2-mixer.yaml | 34 +++- drivers/gpu/drm/sun4i/sun8i_csc.c | 4 +- drivers/gpu/drm/sun4i/sun8i_mixer.c | 168 ++++++++++++++---- drivers/gpu/drm/sun4i/sun8i_mixer.h | 30 +++- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 27 ++- drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 2 +- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 14 +- drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 6 +- 8 files changed, 223 insertions(+), 62 deletions(-)
Signature · 1 line
2.49.0
PATCH v11 1/8 drm: sun4i: de2/de3: add mixer version enum
From: Jernej Skrabec <[email protected]>
The Allwinner DE2 and DE3 display engine mixers are currently identified by a simple boolean flag. This will not scale to support additional DE variants.
Convert the boolean flag to an enum.
---
Changelog v5..v6:
- Update struct comment regarding change from is_de3 flag to de_type
Changelog v10..v11:
- Convert mixer enum to upper case and move enum definition and matching sun8i_mixer_cfg struct change (for DE2 and DE3) from patch 10.
--- drivers/gpu/drm/sun4i/sun8i_csc.c | 4 ++-- drivers/gpu/drm/sun4i/sun8i_mixer.c | 14 ++++++++++++-- drivers/gpu/drm/sun4i/sun8i_mixer.h | 13 +++++++++---- drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 2 +- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 8 ++++---- drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 4 ++-- 6 files changed, 30 insertions(+), 15 deletions(-)
drivers/gpu/drm/sun4i/sun8i_csc.c +2 -2
@@ -212,7 +212,7 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, {u32 base; -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) {sun8i_de3_ccsc_set_coefficients (mixer->engine.regs, layer, mode, encoding, range);return ;
@@ -228,7 +228,7 @@ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) {u32 base; -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) {sun8i_de3_ccsc_enable (mixer->engine.regs, layer, enable);return ; }
drivers/gpu/drm/sun4i/sun8i_mixer.c +12 -2
@@ -537,7 +537,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, base =sun8i_blender_base (mixer);/* Reset registers and disable unused sub-engines */ -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) {for (i =0 ; i <DE3_MIXER_UNIT_SIZE ; i +=4 )regmap_write (mixer->engine.regs, i,0 );
@@ -628,6 +628,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev)static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { .ccsc =CCSC_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .scaler_mask =0xf , .scanline_yuv =2048 , .ui_num =3 ,
@@ -636,6 +637,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { .ccsc =CCSC_MIXER1_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .scaler_mask =0x3 , .scanline_yuv =2048 , .ui_num =1 ,
@@ -644,6 +646,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { .ccsc =CCSC_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =432000000 , .scaler_mask =0xf , .scanline_yuv =2048 ,
@@ -653,6 +656,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { .ccsc =CCSC_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0xf , .scanline_yuv =2048 ,
@@ -662,6 +666,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { .ccsc =CCSC_MIXER1_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0x3 , .scanline_yuv =2048 ,
@@ -670,6 +675,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { };static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { + .de_type =SUN8I_MIXER_DE2 , .vi_num =2 , .ui_num =1 , .scaler_mask =0x3 ,
@@ -680,6 +686,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { .ccsc =CCSC_D1_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0x3 , .scanline_yuv =2048 ,
@@ -689,6 +696,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { .ccsc =CCSC_MIXER1_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0x1 , .scanline_yuv =1024 ,
@@ -698,6 +706,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { .ccsc =CCSC_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0xf , .scanline_yuv =4096 ,
@@ -707,6 +716,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { .ccsc =CCSC_MIXER1_LAYOUT , + .de_type =SUN8I_MIXER_DE2 , .mod_rate =297000000 , .scaler_mask =0x3 , .scanline_yuv =2048 ,
@@ -716,7 +726,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .ccsc =CCSC_MIXER0_LAYOUT , - .is_de3 = true, + .de_type =SUN8I_MIXER_DE3 , .mod_rate =600000000 , .scaler_mask =0xf , .scanline_yuv =4096 ,
drivers/gpu/drm/sun4i/sun8i_mixer.h +9 -4
@@ -151,6 +151,11 @@ enum { CCSC_D1_MIXER0_LAYOUT, }; +enum sun8i_mixer_type { +SUN8I_MIXER_DE2 , +SUN8I_MIXER_DE3 , +}; +/** * struct sun8i_mixer_cfg - mixer HW configuration * @vi_num: number of VI channels
@@ -162,7 +167,7 @@ enum {* @ccsc: select set of CCSC base addresses from the enumeration above. * @mod_rate: module clock rate that needs to be set in order to have * a functional block. -* @is_de3: true, if this is next gen display engine 3.0, false otherwise. +* @de_type: sun8i_mixer_type enum representing the display engine generation. * @scaline_yuv: size of a scanline for VI scaler for YUV formats. */ struct sun8i_mixer_cfg {
@@ -171,7 +176,7 @@ struct sun8i_mixer_cfg {int scaler_mask;int ccsc;unsigned long mod_rate; - unsigned int is_de3 : 1; +unsigned int de_type;unsigned int scanline_yuv; };
@@ -214,13 +219,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)static inline u32 sun8i_blender_base (struct sun8i_mixer *mixer) { -return mixer->cfg->is_de3 ?DE3_BLD_BASE :DE2_BLD_BASE ; +return mixer->cfg->de_type ==SUN8I_MIXER_DE3 ?DE3_BLD_BASE :DE2_BLD_BASE ; }static inline u32 sun8i_channel_base (struct sun8i_mixer *mixer,int channel) { -if (mixer->cfg->is_de3) +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 )return DE3_CH_BASE + channel *DE3_CH_SIZE ;else return DE2_CH_BASE + channel *DE2_CH_SIZE ;
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +1 -1
@@ -93,7 +93,7 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel) {int vi_num = mixer->cfg->vi_num; -if (mixer->cfg->is_de3) +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 )return DE3_VI_SCALER_UNIT_BASE +DE3_VI_SCALER_UNIT_SIZE * vi_num +DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
drivers/gpu/drm/sun4i/sun8i_vi_layer.c +4 -4
@@ -25,7 +25,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel, ch_base =sun8i_channel_base (mixer, channel); -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type >=SUN8I_MIXER_DE3 ) { mask =SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK |SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK ; val =SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA
@@ -483,7 +483,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,if (!layer)return ERR_PTR (-ENOMEM ); -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type >=SUN8I_MIXER_DE3 ) { formats = sun8i_vi_layer_de3_formats; format_count =ARRAY_SIZE (sun8i_vi_layer_de3_formats); }else {
@@ -507,7 +507,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num; -if (mixer->cfg->vi_num ==1 || mixer->cfg->is_de3) { +if (mixer->cfg->vi_num ==1 || mixer->cfg->de_type >=SUN8I_MIXER_DE3 ) { ret =drm_plane_create_alpha_property (&layer->plane);if (ret) {dev_err (drm->dev,"Couldn't add alpha property\n" );
@@ -524,7 +524,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, supported_encodings =BIT (DRM_COLOR_YCBCR_BT601 ) |BIT (DRM_COLOR_YCBCR_BT709 ); -if (mixer->cfg->is_de3) +if (mixer->cfg->de_type >=SUN8I_MIXER_DE3 ) supported_encodings |=BIT (DRM_COLOR_YCBCR_BT2020 ); supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +2 -2
@@ -835,7 +835,7 @@ static const u32 bicubic4coefftab32[480] = {static u32 sun8i_vi_scaler_base (struct sun8i_mixer *mixer,int channel) { -if (mixer->cfg->is_de3) +if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 )return DE3_VI_SCALER_UNIT_BASE +DE3_VI_SCALER_UNIT_SIZE * channel;else
@@ -956,7 +956,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer, cvphase = vphase; } -if (mixer->cfg->is_de3) { +if (mixer->cfg->de_type >=SUN8I_MIXER_DE3 ) {u32 val;if (format->hsub ==1 && format->vsub ==1 )
Signature · 1 line
2.49.0
Re: [PATCH v11 1/8] drm: sun4i: de2/de3: add mixer version enum
Quoted 7 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The Allwinner DE2 and DE3 display engine mixers are currently identified by a simple boolean flag. This will not scale to support additional DE variants.
Quoted 6 lines
Convert the boolean flag to an enum.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Reviewed-by Andre Przywara <[email protected]>Acked-by Maxime Ripard <[email protected]>
PATCH v11 2/8 drm: sun4i: de2/de3: refactor mixer initialisation
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
Now that the DE variant can be selected by enum, take the oppportunity to factor out some common initialisation code to a separate function.
---
Changelog v1..v2:
- Combine base register allocation and initialisation in sun8i_mixer_init
- Whitespace fix
Changelog v4..v5:
- Remove trailing whitespace
Changelog v7..v8:
- Remove CSC configuration changes (logically better placed with future YUV support) making this the first patch in the series.
--- drivers/gpu/drm/sun4i/sun8i_mixer.c | 64 +++++++++++++++-------------- 1 file changed, 34 insertions(+), 30 deletions(-)
drivers/gpu/drm/sun4i/sun8i_mixer.c +34 -30
@@ -425,6 +425,38 @@ static int sun8i_mixer_of_get_id(struct device_node *node)return of_ep.id; } +static void sun8i_mixer_init (struct sun8i_mixer *mixer) +{ +unsigned int base =sun8i_blender_base (mixer); +int plane_cnt, i; + +/* Enable the mixer */ +regmap_write (mixer->engine.regs,SUN8I_MIXER_GLOBAL_CTL , +SUN8I_MIXER_GLOBAL_CTL_RT_EN ); + +/* Set background color to black */ +regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_BKCOLOR (base), +SUN8I_MIXER_BLEND_COLOR_BLACK ); + +/* +* Set fill color of bottom plane to black. Generally not needed +* except when VI plane is at bottom (zpos = 0) and enabled. +*/ +regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), +SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN (0 )); +regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_ATTR_FCOLOR (base,0 ), +SUN8I_MIXER_BLEND_COLOR_BLACK ); + + plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; +for (i =0 ; i < plane_cnt; i++) +regmap_write (mixer->engine.regs, +SUN8I_MIXER_BLEND_MODE (base, i), +SUN8I_MIXER_BLEND_MODE_DEF ); + +regmap_update_bits (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), +SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK ,0 ); +} +static int sun8i_mixer_bind (struct device *dev,struct device *master,void *data) {
@@ -433,8 +465,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,struct sun4i_drv *drv = drm->dev_private;struct sun8i_mixer *mixer;void __iomem *regs; -unsigned int base; -int plane_cnt;int i, ret;/*
@@ -534,8 +564,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,list_add_tail (&mixer->engine.list, &drv->engine_list); - base =sun8i_blender_base (mixer); -/* Reset registers and disable unused sub-engines */ if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) {for (i =0 ; i <DE3_MIXER_UNIT_SIZE ; i +=4 )
@@ -551,7 +579,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,regmap_write (mixer->engine.regs,SUN50I_MIXER_FMT_EN ,0 );regmap_write (mixer->engine.regs,SUN50I_MIXER_CDC0_EN ,0 );regmap_write (mixer->engine.regs,SUN50I_MIXER_CDC1_EN ,0 ); - }else { + }else if (mixer->cfg->de_type ==SUN8I_MIXER_DE2 ) {for (i =0 ; i <DE2_MIXER_UNIT_SIZE ; i +=4 )regmap_write (mixer->engine.regs, i,0 );
@@ -564,31 +592,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,regmap_write (mixer->engine.regs,SUN8I_MIXER_DCSC_EN ,0 ); } -/* Enable the mixer */ -regmap_write (mixer->engine.regs,SUN8I_MIXER_GLOBAL_CTL , -SUN8I_MIXER_GLOBAL_CTL_RT_EN ); - -/* Set background color to black */ -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_BKCOLOR (base), -SUN8I_MIXER_BLEND_COLOR_BLACK ); - -/* -* Set fill color of bottom plane to black. Generally not needed -* except when VI plane is at bottom (zpos = 0) and enabled. -*/ -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), -SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN (0 )); -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_ATTR_FCOLOR (base,0 ), -SUN8I_MIXER_BLEND_COLOR_BLACK ); - - plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; -for (i =0 ; i < plane_cnt; i++) -regmap_write (mixer->engine.regs, -SUN8I_MIXER_BLEND_MODE (base, i), -SUN8I_MIXER_BLEND_MODE_DEF ); - -regmap_update_bits (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), -SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK ,0 ); +sun8i_mixer_init (mixer);return 0 ;
Signature · 1 line
2.49.0
Re: [PATCH v11 2/8] drm: sun4i: de2/de3: refactor mixer initialisation
Quoted 10 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
Now that the DE variant can be selected by enum, take the oppportunity to factor out some common initialisation code to a separate function.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Reviewed-by Andre Przywara <[email protected]>Acked-by Maxime Ripard <[email protected]>
PATCH v11 3/8 drm: sun4i: de2/de3: add generic blender register reference function
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
The DE2 and DE3 engines have a blender register range within the mixer engine register map, whereas the DE33 separates this out into a separate display group.
Prepare for this by adding a function to look the blender reference up, with a subsequent patch to add a conditional based on the DE type.
--- drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++++++ 1 file changed, 6 insertions(+)
drivers/gpu/drm/sun4i/sun8i_mixer.h +6 -0
@@ -222,6 +222,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer)return mixer->cfg->de_type ==SUN8I_MIXER_DE3 ?DE3_BLD_BASE :DE2_BLD_BASE ; } +static inline struct regmap * +sun8i_blender_regmap (struct sun8i_mixer *mixer) +{ +return mixer->engine.regs; +} +static inline u32 sun8i_channel_base (struct sun8i_mixer *mixer,int channel) {
Signature · 1 line
2.49.0
Re: [PATCH v11 3/8] drm: sun4i: de2/de3: add generic blender register reference function
Quoted 7 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The DE2 and DE3 engines have a blender register range within the mixer engine register map, whereas the DE33 separates this out into a separate display group.
Quoted 6 lines
Prepare for this by adding a function to look the blender reference up, with a subsequent patch to add a conditional based on the DE type.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Acked-by Maxime Ripard <[email protected]>
PATCH v11 4/8 drm: sun4i: de2/de3: use generic register reference function for layer configuration
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
Use the new blender register lookup function where required in the layer commit and update code.
---
Changelog v2..v3:
- Refactor for 6.11 layer init/modesetting changes
--- drivers/gpu/drm/sun4i/sun8i_mixer.c | 5 +++-- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 +++++-- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 ++++-- 3 files changed, 12 insertions(+), 6 deletions(-)
drivers/gpu/drm/sun4i/sun8i_mixer.c +3 -2
@@ -274,6 +274,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, {struct sun8i_mixer *mixer =engine_to_sun8i_mixer (engine);u32 bld_base =sun8i_blender_base (mixer); +struct regmap *bld_regs =sun8i_blender_regmap (mixer);struct drm_plane_state *plane_state;struct drm_plane *plane;u32 route =0 , pipe_en =0 ;
@@ -313,8 +314,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine, pipe_en |=SUN8I_MIXER_BLEND_PIPE_CTL_EN (zpos); } -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_ROUTE (bld_base), route); -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (bld_base), +regmap_write (bld_regs,SUN8I_MIXER_BLEND_ROUTE (bld_base), route); +regmap_write (bld_regs,SUN8I_MIXER_BLEND_PIPE_CTL (bld_base), pipe_en |SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN (0 )); regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
drivers/gpu/drm/sun4i/sun8i_ui_layer.c +5 -2
@@ -23,6 +23,7 @@#include "sun8i_mixer.h" #include "sun8i_ui_layer.h" #include "sun8i_ui_scaler.h" +#include "sun8i_vi_scaler.h" static void sun8i_ui_layer_update_alpha (struct sun8i_mixer *mixer,int channel,int overlay,struct drm_plane *plane)
@@ -51,6 +52,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, {struct drm_plane_state *state = plane->state;u32 src_w, src_h, dst_w, dst_h; +struct regmap *bld_regs;u32 bld_base, ch_base;u32 outsize, insize;u32 hphase, vphase;
@@ -59,6 +61,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, channel, overlay); bld_base =sun8i_blender_base (mixer); + bld_regs =sun8i_blender_regmap (mixer); ch_base =sun8i_channel_base (mixer, channel); src_w =drm_rect_width (&state->src) >>16 ;
@@ -103,10 +106,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,DRM_DEBUG_DRIVER ("Layer destination coordinates X: %d Y: %d\n" , state->dst.x1, state->dst.y1);DRM_DEBUG_DRIVER ("Layer destination size W: %d H: %d\n" , dst_w, dst_h); -regmap_write (mixer->engine.regs, +regmap_write (bld_regs,SUN8I_MIXER_BLEND_ATTR_COORD (bld_base, zpos),SUN8I_MIXER_COORD (state->dst.x1, state->dst.y1)); -regmap_write (mixer->engine.regs, +regmap_write (bld_regs,SUN8I_MIXER_BLEND_ATTR_INSIZE (bld_base, zpos), outsize);
drivers/gpu/drm/sun4i/sun8i_vi_layer.c +4 -2
@@ -55,6 +55,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,struct drm_plane_state *state = plane->state;const struct drm_format_info *format = state->fb->format;u32 src_w, src_h, dst_w, dst_h; +struct regmap *bld_regs;u32 bld_base, ch_base;u32 outsize, insize;u32 hphase, vphase;
@@ -66,6 +67,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel, channel, overlay); bld_base =sun8i_blender_base (mixer); + bld_regs =sun8i_blender_regmap (mixer); ch_base =sun8i_channel_base (mixer, channel); src_w =drm_rect_width (&state->src) >>16 ;
@@ -183,10 +185,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,DRM_DEBUG_DRIVER ("Layer destination coordinates X: %d Y: %d\n" , state->dst.x1, state->dst.y1);DRM_DEBUG_DRIVER ("Layer destination size W: %d H: %d\n" , dst_w, dst_h); -regmap_write (mixer->engine.regs, +regmap_write (bld_regs,SUN8I_MIXER_BLEND_ATTR_COORD (bld_base, zpos),SUN8I_MIXER_COORD (state->dst.x1, state->dst.y1)); -regmap_write (mixer->engine.regs, +regmap_write (bld_regs,SUN8I_MIXER_BLEND_ATTR_INSIZE (bld_base, zpos), outsize);
Signature · 1 line
2.49.0
Re: [PATCH v11 4/8] drm: sun4i: de2/de3: use generic register reference function for layer configuration
Quoted 9 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
Use the new blender register lookup function where required in the layer commit and update code.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Acked-by Maxime Ripard <[email protected]>
PATCH v11 5/8 dt-bindings: allwinner: add H616 DE33 mixer binding
In reply to Ryan WalklinThe Allwinner H616 and variants have a new display engine revision (DE33).
The mixer configuration registers are significantly different to the DE3 and DE2 revisions, being split into separate top and display blocks, therefore a fallback for the mixer compatible is not provided.
Note that the DE33 mixer requires 3 register blocks instead of 1. To keep things simple the maxItems value for registers is conditionally removed for the H616 and replaced with the block names from the vendor BSP kernel.
Add a display engine mixer binding for the DE33.
---
Changelog v2..v3:
- Separate content into three patches for three separate subsystems
Changelog v5..v6:
- increase reg maxItems to 3 and add conditional for h616-de33
- Increase reg maxItems to 3.
Changelog v9..v10:
- Use named register blocks rather than by count as names are available from the Allwinner BSP kernel.
--- .../allwinner,sun8i-a83t-de2-mixer.yaml | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml +32 -2
@@ -24,9 +24,11 @@ properties: - allwinner,sun50i-a64-de2-mixer-0 - allwinner,sun50i-a64-de2-mixer-1 - allwinner,sun50i-h6-de3-mixer-0 + - allwinner,sun50i-h616-de33-mixer-0 - reg: - maxItems: 1 + reg: true + + reg-names: true clocks: items:
@@ -61,6 +63,34 @@ properties: required: - port@1 +allOf: + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-de33-mixer-0 + then: + properties: + reg: + description: | + Registers for controlling individual layers of the display + engine (layers), global control (top), and display blending + control (display). Names are from Allwinner BSP kernel. + maxItems: 3 + reg-names: + items: + - const: layers + - const: top + - const: display + required: + - reg-names + + else: + properties: + reg: + maxItems: 1 + required: - compatible - reg
Signature · 1 line
2.49.0
PATCH v11 6/8 drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
The DE33 is a newer version of the Allwinner Display Engine IP block, found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already supported by the mainline driver.
Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output support
Other features (implemented but not in this patchset):
- AFBC ARM Frame Buffer Compression support
- YUV pipeline support
The DE2 and DE3 engines have a blender register range within the mixer engine register map, whereas the DE33 separates this out into a separate display group, and adds a top register map.
The DE33 also appears to remove the global double buffer control register, present in the DE2 and DE3.
Extend the mixer to support the DE33.
---
Changelog v4..v5:
- Whitespace fixes
- Correct strict mode warnings from checkpatch.pl
Changelog v7..v8:
- Add top/disp regmaps to mixer for DE33
- Remove YUV-specific code
- Remove use of global double buffer
- Remove unneeded if/then parentheses and fix an alignment issue as suggested by checkpatch.pl
Changelog v9..v10:
- Use names from vendor BSP kernel for register blocks.
Changelog v10..v11:
- move before vi_scaler patch as vi_scaler code references new DE33 enum.
Changelog v10..v11:
- Convert de_type enum to uppercase
--- drivers/gpu/drm/sun4i/sun8i_mixer.c | 82 +++++++++++++++++++++++++---- drivers/gpu/drm/sun4i/sun8i_mixer.h | 15 +++++- 2 files changed, 84 insertions(+), 13 deletions(-)
drivers/gpu/drm/sun4i/sun8i_mixer.c +71 -11
@@ -318,8 +318,9 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,regmap_write (bld_regs,SUN8I_MIXER_BLEND_PIPE_CTL (bld_base), pipe_en |SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN (0 )); -regmap_write (engine->regs,SUN8I_MIXER_GLOBAL_DBUFF , -SUN8I_MIXER_GLOBAL_DBUFF_ENABLE ); +if (mixer->cfg->de_type !=SUN8I_MIXER_DE33 ) +regmap_write (engine->regs,SUN8I_MIXER_GLOBAL_DBUFF , +SUN8I_MIXER_GLOBAL_DBUFF_ENABLE ); } static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
@@ -368,25 +369,31 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine, const struct drm_display_mode *mode) {struct sun8i_mixer *mixer =engine_to_sun8i_mixer (engine); +struct regmap *bld_regs;u32 bld_base, size, val;bool interlaced; bld_base =sun8i_blender_base (mixer); + bld_regs =sun8i_blender_regmap (mixer); interlaced = !!(mode->flags &DRM_MODE_FLAG_INTERLACE ); size =SUN8I_MIXER_SIZE (mode->hdisplay, mode->vdisplay);DRM_DEBUG_DRIVER ("Updating global size W: %u H: %u\n" , mode->hdisplay, mode->vdisplay); -regmap_write (engine->regs,SUN8I_MIXER_GLOBAL_SIZE , size); -regmap_write (engine->regs,SUN8I_MIXER_BLEND_OUTSIZE (bld_base), size); +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) +regmap_write (mixer->top_regs,SUN50I_MIXER_GLOBAL_SIZE , size); +else +regmap_write (mixer->engine.regs,SUN8I_MIXER_GLOBAL_SIZE , size); + +regmap_write (bld_regs,SUN8I_MIXER_BLEND_OUTSIZE (bld_base), size);if (interlaced) val =SUN8I_MIXER_BLEND_OUTCTL_INTERLACED ;else val =0 ; -regmap_update_bits (engine->regs,SUN8I_MIXER_BLEND_OUTCTL (bld_base), +regmap_update_bits (bld_regs,SUN8I_MIXER_BLEND_OUTCTL (bld_base),SUN8I_MIXER_BLEND_OUTCTL_INTERLACED , val); DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
@@ -400,12 +407,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = { };static const struct regmap_config sun8i_mixer_regmap_config = { + .name ="layers" , .reg_bits =32 , .val_bits =32 , .reg_stride =4 , .max_register =0xffffc ,/* guessed */ }; +static const struct regmap_config sun8i_top_regmap_config = { + .name ="top" , + .reg_bits =32 , + .val_bits =32 , + .reg_stride =4 , + .max_register =0x3c , +}; + +static const struct regmap_config sun8i_disp_regmap_config = { + .name ="display" , + .reg_bits =32 , + .val_bits =32 , + .reg_stride =4 , + .max_register =0x20000 , +}; +static int sun8i_mixer_of_get_id (struct device_node *node) {struct device_node *ep, *remote;
@@ -428,33 +452,45 @@ static int sun8i_mixer_of_get_id(struct device_node *node)static void sun8i_mixer_init (struct sun8i_mixer *mixer) { +struct regmap *top_regs, *disp_regs;unsigned int base =sun8i_blender_base (mixer);int plane_cnt, i; +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) { + top_regs = mixer->top_regs; + disp_regs = mixer->disp_regs; + }else { + top_regs = mixer->engine.regs; + disp_regs = mixer->engine.regs; + } +/* Enable the mixer */ -regmap_write (mixer->engine.regs,SUN8I_MIXER_GLOBAL_CTL , +regmap_write (top_regs,SUN8I_MIXER_GLOBAL_CTL ,SUN8I_MIXER_GLOBAL_CTL_RT_EN ); +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) +regmap_write (top_regs,SUN50I_MIXER_GLOBAL_CLK ,1 ); +/* Set background color to black */ -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_BKCOLOR (base), +regmap_write (disp_regs,SUN8I_MIXER_BLEND_BKCOLOR (base),SUN8I_MIXER_BLEND_COLOR_BLACK );/* * Set fill color of bottom plane to black. Generally not needed * except when VI plane is at bottom (zpos = 0) and enabled. */ -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), +regmap_write (disp_regs,SUN8I_MIXER_BLEND_PIPE_CTL (base),SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN (0 )); -regmap_write (mixer->engine.regs,SUN8I_MIXER_BLEND_ATTR_FCOLOR (base,0 ), +regmap_write (disp_regs,SUN8I_MIXER_BLEND_ATTR_FCOLOR (base,0 ),SUN8I_MIXER_BLEND_COLOR_BLACK ); plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;for (i =0 ; i < plane_cnt; i++) -regmap_write (mixer->engine.regs, +regmap_write (disp_regs,SUN8I_MIXER_BLEND_MODE (base, i),SUN8I_MIXER_BLEND_MODE_DEF ); -regmap_update_bits (mixer->engine.regs,SUN8I_MIXER_BLEND_PIPE_CTL (base), +regmap_update_bits (disp_regs,SUN8I_MIXER_BLEND_PIPE_CTL (base),SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK ,0 ); }
@@ -526,6 +562,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,return PTR_ERR (mixer->engine.regs); } +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) { + regs =devm_platform_ioremap_resource_byname (pdev,"top" ); +if (IS_ERR (regs)) +return PTR_ERR (regs); + + mixer->top_regs =devm_regmap_init_mmio (dev, regs, + &sun8i_top_regmap_config); +if (IS_ERR (mixer->top_regs)) { +dev_err (dev,"Couldn't create the top regmap\n" ); +return PTR_ERR (mixer->top_regs); + } + + regs =devm_platform_ioremap_resource_byname (pdev,"display" ); +if (IS_ERR (regs)) +return PTR_ERR (regs); + + mixer->disp_regs =devm_regmap_init_mmio (dev, regs, + &sun8i_disp_regmap_config); +if (IS_ERR (mixer->disp_regs)) { +dev_err (dev,"Couldn't create the disp regmap\n" ); +return PTR_ERR (mixer->disp_regs); + } + } + mixer->reset =devm_reset_control_get (dev,NULL );if (IS_ERR (mixer->reset)) {dev_err (dev,"Couldn't get our reset line\n" );
drivers/gpu/drm/sun4i/sun8i_mixer.h +13 -2
@@ -21,6 +21,9 @@#define SUN8I_MIXER_GLOBAL_DBUFF 0x8#define SUN8I_MIXER_GLOBAL_SIZE 0xc +#define SUN50I_MIXER_GLOBAL_SIZE 0x8 +#define SUN50I_MIXER_GLOBAL_CLK 0xc +#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
@@ -154,6 +157,7 @@ enum {enum sun8i_mixer_type {SUN8I_MIXER_DE2 ,SUN8I_MIXER_DE3 , +SUN8I_MIXER_DE33 , };/**
@@ -178,6 +182,7 @@ struct sun8i_mixer_cfg {unsigned long mod_rate;unsigned int de_type;unsigned int scanline_yuv; +unsigned int map[6 ]; };struct sun8i_mixer {
@@ -189,6 +194,9 @@ struct sun8i_mixer {struct clk *bus_clk;struct clk *mod_clk; + +struct regmap *top_regs; +struct regmap *disp_regs; };enum {
@@ -225,13 +233,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer)static inline struct regmap *sun8i_blender_regmap (struct sun8i_mixer *mixer) { -return mixer->engine.regs; +return mixer->cfg->de_type ==SUN8I_MIXER_DE33 ? + mixer->disp_regs : mixer->engine.regs; }static inline u32 sun8i_channel_base (struct sun8i_mixer *mixer,int channel) { -if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) +return mixer->cfg->map[channel] *0x20000 +DE2_CH_SIZE ; +else if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 )return DE3_CH_BASE + channel *DE3_CH_SIZE ;else return DE2_CH_BASE + channel *DE2_CH_SIZE ;
Signature · 1 line
2.49.0
Re: [PATCH v11 6/8] drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
Quoted 21 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The DE33 is a newer version of the Allwinner Display Engine IP block, found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already supported by the mainline driver.
Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output supportOther features (implemented but not in this patchset):
- AFBC ARM Frame Buffer Compression support
- YUV pipeline supportThe DE2 and DE3 engines have a blender register range within the mixer engine register map, whereas the DE33 separates this out into a separate display group, and adds a top register map.
The DE33 also appears to remove the global double buffer control register, present in the DE2 and DE3.
Quoted 6 lines
Extend the mixer to support the DE33.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Signed-off-by Chris Morgan <[email protected]>Acked-by Maxime Ripard <[email protected]>
Code looks OK, though I have not tried to check the register offsets.
Re: [PATCH v11 6/8] drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
In reply to Ryan WalklinHi,
Quoted 52 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The DE33 is a newer version of the Allwinner Display Engine IP block, found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already supported by the mainline driver.
Notable features (from the H616 datasheet and implemented):
- 4096 x 2048 (4K) output supportOther features (implemented but not in this patchset):
- AFBC ARM Frame Buffer Compression support
- YUV pipeline supportThe DE2 and DE3 engines have a blender register range within the mixer engine register map, whereas the DE33 separates this out into a separate display group, and adds a top register map.
The DE33 also appears to remove the global double buffer control register, present in the DE2 and DE3.
Extend the mixer to support the DE33.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Signed-off-by Chris Morgan <[email protected]>Acked-by Maxime Ripard <[email protected]>---
Changelog v4..v5:
- Whitespace fixes
- Correct strict mode warnings from checkpatch.plChangelog v7..v8:
- Add top/disp regmaps to mixer for DE33
- Remove YUV-specific code
- Remove use of global double buffer
- Remove unneeded if/then parentheses and fix an alignment issue as suggested by checkpatch.plChangelog v9..v10:
- Use names from vendor BSP kernel for register blocks.Changelog v10..v11:
- move beforevi_scalerpatch asvi_scalercode references new DE33 enum.Changelog v10..v11:
- Convertde_typeenum to uppercase--- drivers/gpu/drm/sun4i/sun8i_mixer.c | 82 +++++++++++++++++++++++++---- drivers/gpu/drm/sun4i/sun8i_mixer.h | 15 +++++- 2 files changed, 84 insertions(+), 13 deletions(-)
[...]
Quoted 23 lines
drivers/gpu/drm/sun4i/sun8i_mixer.h +4
-0@@ -21,6 +21,9 @@#define SUN8I_MIXER_GLOBAL_DBUFF 0x8#define SUN8I_MIXER_GLOBAL_SIZE 0xc +#define SUN50I_MIXER_GLOBAL_SIZE 0x8 +#define SUN50I_MIXER_GLOBAL_CLK 0xc +#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)@@ -154,6 +157,7 @@ enum {enum sun8i_mixer_type {SUN8I_MIXER_DE2 ,SUN8I_MIXER_DE3 , +SUN8I_MIXER_DE33 , };/**
drivers/gpu/drm/sun4i/sun8i_mixer.h struct sun8i_mixer_cfg { · line 185
Quoted 4 lines
drivers/gpu/drm/sun4i/sun8i_mixer.h +1
-0@@ -178,6 +182,7 @@ struct sun8i_mixer_cfg {unsigned long mod_rate;unsigned int de_type;unsigned int scanline_yuv; +unsigned int map[6 ];
This needs a corresponding change to the kernel-doc immediately before it, or the doc generation build will produce a warning.
You can keep the reviewed-by after fixing it.
ChenYu
PATCH v11 7/8 drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
The vi_scaler appears to be used in preference to the ui_scaler module for hardware video scaling in the DE33.
Enable support for this scaler.
--
Changelog v10..v11:
- Convert de_type enum to uppercase
--- drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 20 ++++++++++++++++---- drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 4 +++- 2 files changed, 19 insertions(+), 5 deletions(-)
drivers/gpu/drm/sun4i/sun8i_ui_layer.c +16 -4
@@ -94,12 +94,24 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, hscale = state->src_w / state->crtc_w; vscale = state->src_h / state->crtc_h; -sun8i_ui_scaler_setup (mixer, channel, src_w, src_h, dst_w, - dst_h, hscale, vscale, hphase, vphase); -sun8i_ui_scaler_enable (mixer, channel, true); +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) { +sun8i_vi_scaler_setup (mixer, channel, src_w, src_h, + dst_w, dst_h, hscale, vscale, + hphase, vphase, + state->fb->format); +sun8i_vi_scaler_enable (mixer, channel, true); + }else { +sun8i_ui_scaler_setup (mixer, channel, src_w, src_h, + dst_w, dst_h, hscale, vscale, + hphase, vphase); +sun8i_ui_scaler_enable (mixer, channel, true); + } }else {DRM_DEBUG_DRIVER ("HW scaling is not needed\n" ); -sun8i_ui_scaler_enable (mixer, channel, false); +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) +sun8i_vi_scaler_enable (mixer, channel, false); +else +sun8i_ui_scaler_enable (mixer, channel, false); }/* Set base coordinates */
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +3 -1
@@ -835,7 +835,9 @@ static const u32 bicubic4coefftab32[480] = {static u32 sun8i_vi_scaler_base (struct sun8i_mixer *mixer,int channel) { -if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 ) +if (mixer->cfg->de_type ==SUN8I_MIXER_DE33 ) +return sun8i_channel_base (mixer, channel) +0x3000 ; +else if (mixer->cfg->de_type ==SUN8I_MIXER_DE3 )return DE3_VI_SCALER_UNIT_BASE +DE3_VI_SCALER_UNIT_SIZE * channel;else
Signature · 1 line
2.49.0
Re: [PATCH v11 7/8] drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
Quoted 11 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The
vi_scalerappears to be used in preference to theui_scalermodule for hardware video scaling in the DE33.Enable support for this scaler.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Acked-by Maxime Ripard <[email protected]>
PATCH v11 8/8 drm: sun4i: de33: mixer: add mixer configuration for the H616
In reply to Ryan WalklinFrom: Jernej Skrabec <[email protected]>
The H616 (and related SoC packages sharing the same die) carry the new DE33 display engine.
Add the mixer configuration and a compatible string for the H616 to the mixer.
--
Changelog v7..v8:
- Separate DE33 support and H616 enablement in the mixer.
Changelog v10..v11:
- Convert de_type enum to uppercase
--- drivers/gpu/drm/sun4i/sun8i_mixer.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
drivers/gpu/drm/sun4i/sun8i_mixer.c +15 -0
@@ -799,6 +799,17 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { .vi_num = 1, }; +static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = { + .ccsc =CCSC_MIXER0_LAYOUT , + .de_type =SUN8I_MIXER_DE33 , + .mod_rate =600000000 , + .scaler_mask =0xf , + .scanline_yuv =4096 , + .ui_num =3 , + .vi_num =1 , + .map = {0 ,6 ,7 ,8 }, +}; +static const struct of_device_id sun8i_mixer_of_table[] = { { .compatible ="allwinner,sun8i-a83t-de2-mixer-0" ,
@@ -844,6 +855,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = { .compatible = "allwinner,sun50i-h6-de3-mixer-0", .data = &sun50i_h6_mixer0_cfg, }, + { + .compatible = "allwinner,sun50i-h616-de33-mixer-0", + .data = &sun50i_h616_mixer0_cfg, + }, { } };MODULE_DEVICE_TABLE (of, sun8i_mixer_of_table);
Signature · 1 line
2.49.0
Re: [PATCH v11 8/8] drm: sun4i: de33: mixer: add mixer configuration for the H616
Quoted 6 lines · Ryan Walklin
From: Jernej Skrabec <[email protected]>
The H616 (and related SoC packages sharing the same die) carry the new DE33 display engine.
Quoted 6 lines
Add the mixer configuration and a compatible string for the H616 to the mixer.
Signed-off-by Jernej Skrabec <[email protected]>Signed-off-by Ryan Walklin <[email protected]>Acked-by Maxime Ripard <[email protected]>