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fixing typo in macro name

PATCH Applied Jihed Chaibi 3 participants 5 messages May 17, 2025 – May 19, 2025

Subsystems (4)
DRM drivers Radeon and amdgpu DRM drivers AMD display core AMD powerplay and SWSMU
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Jihed Chaibi

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#0 lore raw

PATCH 1/2 fixing typo in macro name

"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS

PS: checkpatch.pl is complaining about the presence of a space at the start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716 This is propably because this file uses (two) spaces and not tabs.

Signed-off-by Jihed Chaibi <[email protected]>
---
 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +-
 drivers/gpu/drm/amd/include/atombios.h                      | 4 ++--
 drivers/gpu/drm/amd/include/atomfirmware.h                  | 2 +-
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c                  | 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c         | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +1 -1
index 813463ffe..cc4670316 100644
@@ -424,7 +424,7 @@ struct integrated_info {
 /*
  * DFS-bypass flag
  */
-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
 enum {
 	DFS_BYPASS_ENABLE = 0x10
 };
drivers/gpu/drm/amd/include/atombios.h +2 -2
index b78360a71..a99923b4e 100644
@@ -6017,7 +6017,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
 

@@ -6460,7 +6460,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
 
 // ulGPUCapInfo
 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
drivers/gpu/drm/amd/include/atomfirmware.h +1 -1
index 0160d65f3..52eb3a474 100644
@@ -1713,7 +1713,7 @@ enum atom_system_vbiosmisc_def{
 
 // gpucapinfo
 enum atom_system_gpucapinf_def{
-  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
+  SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS  = 0x10,
 };
 
 //dpphy_override
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +1 -1
index 59fae668d..34e71727b 100644
@@ -2594,7 +2594,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
 				le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
 		}
 		if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-		    SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+		    SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
 			pi->caps_enable_dfs_bypass = true;
 
 		sumo_construct_sclk_voltage_mapping_table(adev,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +1 -1
index 9d3b33446..9b20076e2 100644
@@ -394,7 +394,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
 	}
 
 	if (le32_to_cpu(info->ulGPUCapInfo) &
-		SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
+		SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS) {
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 				    PHM_PlatformCaps_EnableDFSBypass);
 	}
Signature · 1 line
2.39.5
#1 lore raw

Jihed Chaibi <[email protected]>, 17 May 2025 Cmt, 06:06 tarihinde şunu yazdı:

Quoted 7 lines

"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS

PS: checkpatch.pl is complaining about the presence of a space at the start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716 This is propably because this file uses (two) spaces and not tabs.

Hello,

i stared at my screen for a long time to understand what the fix was and finally figured it out but i think it also occurs in files containing graphic objects.
it must have changed completely, there must be a macro that calls graph objects.

Regards

Ozgur

Quoted 88 lines
Signed-off-by Jihed Chaibi <[email protected]>
---
 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +-
 drivers/gpu/drm/amd/include/atombios.h                      | 4 ++--
 drivers/gpu/drm/amd/include/atomfirmware.h                  | 2 +-
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c                  | 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c         | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +1 -1
index 813463ffe..cc4670316 100644
@@ -424,7 +424,7 @@ struct integrated_info {
 /*
  * DFS-bypass flag
  */
-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
 enum {
        DFS_BYPASS_ENABLE = 0x10
 };
drivers/gpu/drm/amd/include/atombios.h +2 -2
index b78360a71..a99923b4e 100644
@@ -6017,7 +6017,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
 

@@ -6460,7 +6460,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
 
 // ulGPUCapInfo
 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
drivers/gpu/drm/amd/include/atomfirmware.h +1 -1
index 0160d65f3..52eb3a474 100644
@@ -1713,7 +1713,7 @@ enum atom_system_vbiosmisc_def{
 
 // gpucapinfo
 enum atom_system_gpucapinf_def{
-  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
+  SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS  = 0x10,
 };
 
 //dpphy_override
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +1 -1
index 59fae668d..34e71727b 100644
@@ -2594,7 +2594,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
                                le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
                }
                if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-                   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+                   SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
                        pi->caps_enable_dfs_bypass = true;
 
                sumo_construct_sclk_voltage_mapping_table(adev,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +1 -2
index 9d3b33446..9b20076e2 100644
@@ -394,7 +394,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
        }
 
        if (le32_to_cpu(info->ulGPUCapInfo) &
-               SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
+               SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS) {
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                    PHM_PlatformCaps_EnableDFSBypass);
        }
--

2.39.5

#2 lore raw
In reply to Jihed Chaibi

Jihed Chaibi <[email protected]>, 17 May 2025 Cmt, 06:06 tarihinde şunu yazdı:

Quoted 7 lines

"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS

PS: checkpatch.pl is complaining about the presence of a space at the start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716 This is propably because this file uses (two) spaces and not tabs.

Hello,

i stared at my screen for a long time to understand what the fix was and finally figured it out but i think it also occurs in files containing graphic objects.
it must have changed completely, there must be a macro that calls graph objects.

Regards

Ozgur

Quoted 88 lines
Signed-off-by Jihed Chaibi <[email protected]>
---
 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +-
 drivers/gpu/drm/amd/include/atombios.h                      | 4 ++--
 drivers/gpu/drm/amd/include/atomfirmware.h                  | 2 +-
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c                  | 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c         | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +1 -1
index 813463ffe..cc4670316 100644
@@ -424,7 +424,7 @@ struct integrated_info {
 /*
  * DFS-bypass flag
  */
-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
 enum {
        DFS_BYPASS_ENABLE = 0x10
 };
drivers/gpu/drm/amd/include/atombios.h +2 -2
index b78360a71..a99923b4e 100644
@@ -6017,7 +6017,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
 

@@ -6460,7 +6460,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
 
 // ulGPUCapInfo
 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
drivers/gpu/drm/amd/include/atomfirmware.h +1 -1
index 0160d65f3..52eb3a474 100644
@@ -1713,7 +1713,7 @@ enum atom_system_vbiosmisc_def{
 
 // gpucapinfo
 enum atom_system_gpucapinf_def{
-  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
+  SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS  = 0x10,
 };
 
 //dpphy_override
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +1 -1
index 59fae668d..34e71727b 100644
@@ -2594,7 +2594,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
                                le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
                }
                if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-                   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+                   SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
                        pi->caps_enable_dfs_bypass = true;
 
                sumo_construct_sclk_voltage_mapping_table(adev,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +1 -2
index 9d3b33446..9b20076e2 100644
@@ -394,7 +394,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
        }
 
        if (le32_to_cpu(info->ulGPUCapInfo) &
-               SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
+               SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS) {
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                    PHM_PlatformCaps_EnableDFSBypass);
        }
--

2.39.5

#3 lore raw
In reply to Jihed Chaibi

Jihed Chaibi <[email protected]>, 17 May 2025 Cmt, 06:06 tarihinde şunu yazdı:

Quoted 7 lines

"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS

PS: checkpatch.pl is complaining about the presence of a space at the start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716 This is propably because this file uses (two) spaces and not tabs.

Hello,

i stared at my screen for a long time to understand what the fix was and finally figured it out but i think it also occurs in files containing graphic objects.
it must have changed completely, there must be a macro that calls graph objects.

Regards

Ozgur

Quoted 88 lines
Signed-off-by Jihed Chaibi <[email protected]>
---
 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +-
 drivers/gpu/drm/amd/include/atombios.h                      | 4 ++--
 drivers/gpu/drm/amd/include/atomfirmware.h                  | 2 +-
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c                  | 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c         | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +1 -1
index 813463ffe..cc4670316 100644
@@ -424,7 +424,7 @@ struct integrated_info {
 /*
  * DFS-bypass flag
  */
-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
 enum {
        DFS_BYPASS_ENABLE = 0x10
 };
drivers/gpu/drm/amd/include/atombios.h +2 -2
index b78360a71..a99923b4e 100644
@@ -6017,7 +6017,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
 

@@ -6460,7 +6460,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
 
 // ulGPUCapInfo
 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
drivers/gpu/drm/amd/include/atomfirmware.h +1 -1
index 0160d65f3..52eb3a474 100644
@@ -1713,7 +1713,7 @@ enum atom_system_vbiosmisc_def{
 
 // gpucapinfo
 enum atom_system_gpucapinf_def{
-  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
+  SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS  = 0x10,
 };
 
 //dpphy_override
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +1 -1
index 59fae668d..34e71727b 100644
@@ -2594,7 +2594,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
                                le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
                }
                if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-                   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+                   SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
                        pi->caps_enable_dfs_bypass = true;
 
                sumo_construct_sclk_voltage_mapping_table(adev,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +1 -2
index 9d3b33446..9b20076e2 100644
@@ -394,7 +394,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
        }
 
        if (le32_to_cpu(info->ulGPUCapInfo) &
-               SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
+               SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS) {
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                    PHM_PlatformCaps_EnableDFSBypass);
        }
--

2.39.5

Applied
#4 lore raw
In reply to Jihed Chaibi

Applied. Thanks!

Quoted 93 lines · Jihed Chaibi

"ENABLE" is currently misspelled in SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS

PS: checkpatch.pl is complaining about the presence of a space at the start of drivers/gpu/drm/amd/include/atomfirmware.h line: 1716 This is propably because this file uses (two) spaces and not tabs.

Signed-off-by Jihed Chaibi <[email protected]>
---
 drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h | 2 +-
 drivers/gpu/drm/amd/include/atombios.h                      | 4 ++--
 drivers/gpu/drm/amd/include/atomfirmware.h                  | 2 +-
 drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c                  | 2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c         | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/display/include/grph_object_ctrl_defs.h +1 -1
index 813463ffe..cc4670316 100644
@@ -424,7 +424,7 @@ struct integrated_info {
 /*
  * DFS-bypass flag
  */
-/* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */
+/* Copy of SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS from atombios.h */
 enum {
        DFS_BYPASS_ENABLE = 0x10
 };
drivers/gpu/drm/amd/include/atombios.h +2 -2
index b78360a71..a99923b4e 100644
@@ -6017,7 +6017,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
 

@@ -6460,7 +6460,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
 
 // ulGPUCapInfo
 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT                         0x08
-#define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS                               0x10
+#define SYS_INFO_V1_9_GPUCAPSINFO_ENABLE_DFS_BYPASS                               0x10
 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE                         0x00010000
 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available
drivers/gpu/drm/amd/include/atomfirmware.h +1 -1
index 0160d65f3..52eb3a474 100644
@@ -1713,7 +1713,7 @@ enum atom_system_vbiosmisc_def{
 
 // gpucapinfo
 enum atom_system_gpucapinf_def{
-  SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS  = 0x10,
+  SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS  = 0x10,
 };
 
 //dpphy_override
drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +1 -1
index 59fae668d..34e71727b 100644
@@ -2594,7 +2594,7 @@ static int kv_parse_sys_info_table(struct amdgpu_device *adev)
                                le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
                }
                if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
-                   SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
+                   SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS)
                        pi->caps_enable_dfs_bypass = true;
 
                sumo_construct_sclk_voltage_mapping_table(adev,
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c +1 -2
index 9d3b33446..9b20076e2 100644
@@ -394,7 +394,7 @@ static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
        }
 
        if (le32_to_cpu(info->ulGPUCapInfo) &
-               SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS) {
+               SYS_INFO_GPUCAPS__ENABLE_DFS_BYPASS) {
                phm_cap_set(hwmgr->platform_descriptor.platformCaps,
                                    PHM_PlatformCaps_EnableDFSBypass);
        }
--

2.39.5