ARM: at91: clock: remove unused SAMA5D2/SAMA5D3 support from legacy clock driver

PATCH Applied Alexander Shiyan 2 participants 11 messages Jun 18, 2025

Subsystems (3)

Arm (32-bit) Arm sub-architectures Arm/Microchip (AT91) SoC support

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Alexander Shiyan

author

2025-06-18 06:38 UTC #0 lore raw

PATCH 1/1 ARM: at91: clock: remove unused SAMA5D2/SAMA5D3 support from legacy clock driver

This driver is not used for DT-based boards and only affects legacy non-DT platforms. Remove support for SAMA5D2/SAMA5D3 SoCs as they are exclusively supported through DT-based boot in current configurations.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-at91/clock.c | 32 ++++----------------------------
 1 file changed, 4 insertions(+), 28 deletions(-)

arch/arm/mach-at91/clock.c +4 ~~-28~~

index 6482aa93c0..7ffd549dc4 100644
@@ -40,14 +40,10 @@
 #define cpu_has_utmi()		(  cpu_is_at91sam9rl() \
 				|| cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4())
 
 #define cpu_has_1200M_plla()	(cpu_is_sama5d4())
 
-#define cpu_has_1056M_plla()	(cpu_is_sama5d3())
-
 #define cpu_has_800M_plla()	(  cpu_is_at91sam9g20() \
 				|| cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \

@@ -64,14 +60,10 @@
 #define cpu_has_pllb()		(!(cpu_is_at91sam9rl() \
 				|| cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4()))
 
 #define cpu_has_upll()		(cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4())
 
 /* USB host HS & FS */

@@ -81,36 +73,25 @@
 #define cpu_has_udpfs()		(!(cpu_is_at91sam9rl() \
 				|| cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4()))
 
 #define cpu_has_plladiv2()	(cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
 				|| cpu_is_at91sam9n12() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4())
 
 #define cpu_has_mdiv3()		(cpu_is_at91sam9g45() \
 				|| cpu_is_at91sam9x5() \
 				|| cpu_is_at91sam9n12() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4())
 
 #define cpu_has_alt_prescaler()	(cpu_is_at91sam9x5() \
 				|| cpu_is_at91sam9n12() \
-				|| cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
 				|| cpu_is_sama5d4())
 
-#define cpu_has_pcr()		(cpu_is_sama5d2() \
-				|| cpu_is_sama5d3() \
-				|| cpu_is_sama5d4())
+#define cpu_has_pcr()		(cpu_is_sama5d4())
 
-#define cpu_has_dual_matrix()	(cpu_is_sama5d2() \
-				|| cpu_is_sama5d4())
+#define cpu_has_dual_matrix()	(cpu_is_sama5d4())
 
 static void *pmc;

@@ -253,7 +234,7 @@ static void pmc_periph_mode(struct clk *clk, int is_on)
 	u32 regval = 0;
 
 	/*
-	 * With sama5d3 chips, you have more than 32 peripherals so only one
+	 * With sama5d4 chips, you have more than 32 peripherals so only one
 	 * register is not enough to manage their clocks. A peripheral
 	 * control register has been introduced to solve this issue.
 	 */

@@ -517,7 +498,7 @@ static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 	unsigned mul, div;
 
 	div = reg & 0xff;
-	if (cpu_is_sama5d3() || cpu_is_sama5d4())
+	if (cpu_is_sama5d4())
 		mul = (reg >> 18) & 0x7ff;
 	else
 		mul = (reg >> 16) & 0x7ff;

@@ -666,8 +647,6 @@ int at91_clock_init(void)
 
 	if (cpu_is_sama5d4())
 		pmc = IOMEM(0xf0018000);
-	else if (cpu_is_sama5d2())
-		pmc = IOMEM(0xf0014000);
 	else
 		pmc = IOMEM(0xfffffc00); /*
 					  * All other supported SoCs use this

@@ -696,9 +675,6 @@ int at91_clock_init(void)
 	if (cpu_has_1200M_plla()) {
 		if (plla.rate_hz > 1200000000)
 			pll_overclock = 1;
-	} else if (cpu_has_1056M_plla()) {
-		if (plla.rate_hz > 1056000000)
-			pll_overclock = 1;
 	} else if (cpu_has_300M_plla()) {
 		if (plla.rate_hz > 300000000)
 			pll_overclock = 1;

Signature · 1 line

2.39.1

Alexander Shiyan

author

2025-06-18 06:38 UTC #1 lore raw

PATCH 1/1 ARM: at91: sam9x5ek: enable missing DT and clock options for devicetree boot

The AT91SAM9X5EK board uses devicetree but was missing critical Kconfig options required for proper DT-based operation. This patch adds OFDEVICE and COMMON_CLK_OF_PROVIDER Kconfig options for this board.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-at91/Kconfig | 2 ++
 1 file changed, 2 insertions(+)

arch/arm/mach-at91/Kconfig +2 -0

index bb04c1267e..db79ad2d26 100644
@@ -581,6 +581,8 @@ config MACH_AT91SAM9263EK
 config MACH_AT91SAM9X5EK
 	bool "Atmel AT91SAM9x5 Series Evaluation Kit"
 	select SOC_AT91SAM9X5
+	select OFDEVICE
+	select COMMON_CLK_OF_PROVIDER
 	help
 	  Select this if you re using Atmel's AT91SAM9x5-EK Evaluation Kit.
 	  Supported chips are sam9g15, sam9g25, sam9x25, sam9g35 and sam9x35.

Signature · 1 line

2.39.1

Sascha Hauer

Applied

2025-06-18 10:54 UTC #2 lore raw

Re: [PATCH] ARM: at91: sam9x5ek: enable missing DT and clock options for devicetree boot

Quoted 5 lines · Alexander Shiyan

The AT91SAM9X5EK board uses devicetree but was missing critical Kconfig options required for proper DT-based operation. This patch adds OFDEVICE and COMMON_CLK_OF_PROVIDER Kconfig options for this board.

Applied, thanks!

[1/1] ARM: at91: sam9x5ek: enable missing DT and clock options for devicetree boot
https://git.pengutronix.de/cgit/barebox/commit/?id=e6670c36bb6c (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>

Alexander Shiyan

author

2025-06-18 06:38 UTC #3 lore raw

PATCH 1/1 ARM: at91: setup: refactor SoC subtype detection with switch statements

In reply to Alexander Shiyan

This patch replaces the series of independent if-statements in dbgu_soc_detect() with a structured switch-case approach for better code organization and readability.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-at91/setup.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

arch/arm/mach-at91/setup.c +11 ~~-13~~

index 708c946192..e8d45c30dd 100644
@@ -102,7 +102,8 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 
 	at91_soc_initdata.cidr = cidr;
 
-	if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
+	switch (at91_soc_initdata.type) {
+	case AT91_SOC_SAM9G45:
 		switch (at91_soc_initdata.exid) {
 		case ARCH_EXID_AT91SAM9M10:
 			at91_soc_initdata.subtype = AT91_SOC_SAM9M10;

@@ -114,9 +115,8 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 			at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 			break;
 		}
-	}
-
-	if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
+		break;
+	case AT91_SOC_SAM9X5:
 		switch (at91_soc_initdata.exid) {
 		case ARCH_EXID_AT91SAM9G15:
 			at91_soc_initdata.subtype = AT91_SOC_SAM9G15;

@@ -134,9 +134,8 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 			at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 			break;
 		}
-	}
-
-	if (at91_soc_initdata.type == AT91_SOC_SAM9N12) {
+		break;
+	case AT91_SOC_SAM9N12:
 		switch (at91_soc_initdata.exid) {
 		case ARCH_EXID_AT91SAM9N12:
 			at91_soc_initdata.subtype = AT91_SOC_SAM9N12;

@@ -148,9 +147,8 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 			at91_soc_initdata.subtype = AT91_SOC_SAM9CN12;
 			break;
 		}
-	}
-
-	if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
+		break;
+	case AT91_SOC_SAMA5D3:
 		switch (at91_soc_initdata.exid) {
 		case ARCH_EXID_SAMA5D31:
 			at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;

@@ -168,9 +166,8 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 			at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 			break;
 		}
-	}
-
-	if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
+		break;
+	case AT91_SOC_SAMA5D4:
 		switch (at91_soc_initdata.exid) {
 		case ARCH_EXID_SAMA5D41:
 			at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;

@@ -185,6 +182,7 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 			at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 			break;
 		}
+		break;
 	}
 }

Signature · 1 line

2.39.1

Sascha Hauer

Applied

2025-06-18 10:54 UTC #4 lore raw

Re: [PATCH] ARM: at91: setup: refactor SoC subtype detection with switch statements

Quoted 5 lines · Alexander Shiyan

This patch replaces the series of independent if-statements in dbgu_soc_detect() with a structured switch-case approach for better code organization and readability.

Applied, thanks!

[1/1] ARM: at91: setup: refactor SoC subtype detection with switch statements
https://git.pengutronix.de/cgit/barebox/commit/?id=b2e8210c4119 (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>

Alexander Shiyan

author

2025-06-18 06:38 UTC #5 lore raw

PATCH 1/1 ARM: at91: xload: use pin_to_mask for peripheral pin configuration

In reply to Alexander Shiyan

The patch replaces the use of BIT(*pin) with pin_to_mask(*pin) when configuring peripheral pins for both SDHCI and QSPI boot modes.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-at91/xload.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/mach-at91/xload.c +2 -2

index fd3878269e..0f7d9738e1 100644
@@ -79,7 +79,7 @@ static void __noreturn sama5d2_sdhci_start_image(u32 r4)
 	sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOA);
 	for (pin = instance->pins; *pin >= 0; pin++) {
 		at91_mux_pio4_set_periph(SAMA5D2_BASE_PIOA,
-					 BIT(*pin), instance->periph);
+					 pin_to_mask(*pin), instance->periph);
 	}
 
 	sama5d2_pmc_enable_periph_clock(instance->id);

@@ -143,7 +143,7 @@ static void __noreturn sama5d2_qspi_start_image(u32 r4)
 	sama5d2_pmc_enable_periph_clock(SAMA5D2_ID_PIOA);
 	for (pin = instance->pins; *pin >= 0; pin++)
 		at91_mux_pio4_set_periph(SAMA5D2_BASE_PIOA,
-					 BIT(*pin), instance->periph);
+					 pin_to_mask(*pin), instance->periph);
 
 	sama5d2_pmc_enable_periph_clock(instance->id);

Signature · 1 line

2.39.1

Sascha Hauer

Applied

2025-06-18 10:54 UTC #6 lore raw

Re: [PATCH] ARM: at91: xload: use pin_to_mask for peripheral pin configuration

Quoted 4 lines · Alexander Shiyan

The patch replaces the use of BIT(*pin) with pin_to_mask(*pin) when configuring peripheral pins for both SDHCI and QSPI boot modes.

Applied, thanks!

[1/1] ARM: at91: xload: use pin_to_mask for peripheral pin configuration
https://git.pengutronix.de/cgit/barebox/commit/?id=c74dd656505f (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>

Sascha Hauer

Applied

2025-06-18 10:54 UTC #7 lore raw

Re: (subset) [PATCH] ARM: at91: xload: use pin_to_mask for peripheral pin configuration

In reply to Alexander Shiyan

Quoted 4 lines · Alexander Shiyan

The patch replaces the use of BIT(*pin) with pin_to_mask(*pin) when configuring peripheral pins for both SDHCI and QSPI boot modes.

Applied, thanks!

[1/1] ARM: at91: xload: use pin_to_mask for peripheral pin configuration
https://git.pengutronix.de/cgit/barebox/commit/?id=c74dd656505f (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>

Alexander Shiyan

author

2025-06-18 06:38 UTC #8 lore raw

PATCH 1/1 ARM: at91: setup: improve address handling for DBGU and CHIPID detection

In reply to Alexander Shiyan

This patch enhances type safety and replaces hardcoded addresses with SoC-specific constants for DBGU and CHIPID detection.

Signed-off-by Alexander Shiyan <[email protected]>

---
 arch/arm/mach-at91/setup.c   | 6 +++---
 include/mach/at91/hardware.h | 2 --
 2 files changed, 3 insertions(+), 5 deletions(-)

arch/arm/mach-at91/setup.c +3 -3

index e8d45c30dd..e726495726 100644
@@ -186,7 +186,7 @@ static void __init dbgu_soc_detect(u32 dbgu_base)
 	}
 }
 
-static void __init chipid_soc_detect(u32 chipid_base)
+static void __init chipid_soc_detect(void __iomem *chipid_base)
 {
 	u32 cidr, socid;

@@ -345,9 +345,9 @@ static int at91_detect(void)
 	if (!at91_soc_is_detected())
 		dbgu_soc_detect(AT91_BASE_DBGU1);
 	if (!at91_soc_is_detected())
-		dbgu_soc_detect(AT91_BASE_DBGU2);
+		dbgu_soc_detect(SAMA5D4_BASE_DBGU);
 	if (!at91_soc_is_detected())
-		chipid_soc_detect(0xfc069000);
+		chipid_soc_detect(SAMA5D2_BASE_CHIPID);
 
 	if (!at91_soc_is_detected())
 		panic("AT91: Impossible to detect the SOC type");

include/mach/at91/hardware.h +0 -2

index 5d2fd872ab..104ad11648 100644
@@ -12,8 +12,6 @@
 #define AT91_BASE_DBGU0	0xfffff200
 /* 9263, 9g45 */
 #define AT91_BASE_DBGU1	0xffffee00
-/* sama5d4 */
-#define AT91_BASE_DBGU2	0xfc069000
 
 #include <mach/at91/at91rm9200.h>
 #include <mach/at91/at91sam9260.h>

Signature · 1 line

2.39.1

Sascha Hauer

Applied

2025-06-18 10:54 UTC #9 lore raw

Re: [PATCH] ARM: at91: setup: improve address handling for DBGU and CHIPID detection

Quoted 4 lines · Alexander Shiyan

This patch enhances type safety and replaces hardcoded addresses with SoC-specific constants for DBGU and CHIPID detection.

Applied, thanks!

[1/1] ARM: at91: setup: improve address handling for DBGU and CHIPID detection
https://git.pengutronix.de/cgit/barebox/commit/?id=193fa21893c6 (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>

Sascha Hauer

Applied

2025-06-18 10:54 UTC #10 lore raw

Re: (subset) [PATCH] ARM: at91: clock: remove unused SAMA5D2/SAMA5D3 support from legacy clock driver

In reply to Alexander Shiyan

Quoted 5 lines · Alexander Shiyan

This driver is not used for DT-based boards and only affects legacy non-DT platforms. Remove support for SAMA5D2/SAMA5D3 SoCs as they are exclusively supported through DT-based boot in current configurations.

Applied, thanks!

[1/1] ARM: at91: clock: remove unused SAMA5D2/SAMA5D3 support from legacy clock driver
https://git.pengutronix.de/cgit/barebox/commit/?id=349fbab3a464 (link may not be stable)

Best regards,

Signature · 1 line

Sascha Hauer <[email protected]>