reset: spacemit: add K1 reset support
Subsystems (5)
v12 cover reset: spacemit: add K1 reset support
This series adds reset controller support for the SpacemiT K1 SoC. A SpacemiT reset controller is implemented as an auxiliary device associated with a clock controller (CCU). A new header file holds definitions used by both the clock and reset drivers.
The only change in this version is that three of the the four resets associated with each PCIe port have been renamed, to align better with their corresponding clocks. This affects patches 1 and 5. For example, for PCIe port 0:
RESET_PCIE0_DBI (no change)
RESET_PCIE0_SLV -> RESET_PCIE0_SLAVE
RESET_PCIE0_MSTR -> RESET_PCIE0_MASTER
RESET_PCIE0_GLB -> RESET_PCIE0_GLOBAL (no corresponding clock)No other code has changed since v11.
All of these patches are available here:
https://github.com/riscstar/linux/tree/outgoing/reset-v12
-Alex
Between version 11 and version 12:
- Renamed PCIe resets to align with their clock counterparts
Here is version 11 of this series.
https://lore.kernel.org/lkml/[email protected]/
Between version 10 and version 11:
- Rebased onto Linux v6.16-rc1
- Redefined several "multi-bit" resets as individual ones.
Here is version 10 of this series.
https://lore.kernel.org/lkml/[email protected]/
All other history is available via that link, so I won't reproduce it again here.
Alex Elder (6):
dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
soc: spacemit: create a header for clock/reset registers
clk: spacemit: set up reset auxiliary devices
clk: spacemit: define three reset-only CCUs
reset: spacemit: add support for SpacemiT CCU resets
riscv: dts: spacemit: add reset support for the K1 SoC
.../soc/spacemit/spacemit,k1-syscon.yaml | 29 +- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++ drivers/clk/spacemit/Kconfig | 1 + drivers/clk/spacemit/ccu-k1.c | 239 +++++++------- drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-spacemit.c | 304 ++++++++++++++++++ .../dt-bindings/clock/spacemit,k1-syscon.h | 141 ++++++++ include/soc/spacemit/k1-syscon.h | 160 +++++++++ 9 files changed, 775 insertions(+), 127 deletions(-) create mode 100644 drivers/reset/reset-spacemit.c create mode 100644 include/soc/spacemit/k1-syscon.h
base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
Signature · 28 lines
2.45.2 Alex Elder (6): dt-bindings: soc: spacemit: define spacemit,k1-ccu resets soc: spacemit: create a header for clock/reset registers clk: spacemit: set up reset auxiliary devices clk: spacemit: define three reset-only CCUs reset: spacemit: add support for SpacemiT CCU resets riscv: dts: spacemit: add reset support for the K1 SoC .../soc/spacemit/spacemit,k1-syscon.yaml | 29 +- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++ drivers/clk/spacemit/Kconfig | 1 + drivers/clk/spacemit/ccu-k1.c | 239 +++++++------- drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-spacemit.c | 304 ++++++++++++++++++ .../dt-bindings/clock/spacemit,k1-syscon.h | 141 ++++++++ include/soc/spacemit/k1-syscon.h | 160 +++++++++ 9 files changed, 775 insertions(+), 127 deletions(-) create mode 100644 drivers/reset/reset-spacemit.c create mode 100644 include/soc/spacemit/k1-syscon.h base-commit: 50c8770a42faf8b1c7abe93e7c114337f580a97d -- 2.45.2
PATCH v12 1/6 dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
There are additional SpacemiT syscon CCUs whose registers control both clocks and resets: RCPU, RCPU2, and APBC2. Unlike those defined previously, these will (initially) support only resets. They do not incorporate power domain functionality.
Previously the clock properties were required for all compatible nodes. Make that requirement only apply to the three existing CCUs (APBC, APMU, and MPMU), so that the new reset-only CCUs can go without specifying them.
Define the index values for resets associated with all SpacemiT K1 syscon nodes, including those with clocks already defined, as well as the new ones (without clocks).
---
v12: - Rename PCIe resets to align with their clock counterparts
.../soc/spacemit/spacemit,k1-syscon.yaml | 29 +++- .../dt-bindings/clock/spacemit,k1-syscon.h | 141 ++++++++++++++++++ 2 files changed, 163 insertions(+), 7 deletions(-)
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml +22 -7
@@ -19,6 +19,9 @@ properties: - spacemit,k1-syscon-apbc - spacemit,k1-syscon-apmu - spacemit,k1-syscon-mpmu + - spacemit,k1-syscon-rcpu + - spacemit,k1-syscon-rcpu2 + - spacemit,k1-syscon-apbc2 reg: maxItems: 1
@@ -47,9 +50,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - - "#clock-cells" - "#reset-cells" allOf:
@@ -57,13 +57,28 @@ allOf: properties: compatible: contains: - const: spacemit,k1-syscon-apbc + enum: + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu then: - properties: - "#power-domain-cells": false - else: required: - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-syscon-apbc + - spacemit,k1-syscon-apmu + - spacemit,k1-syscon-mpmu + then: + required: + - clocks + - clock-names + - "#clock-cells" additionalProperties: false
include/dt-bindings/clock/spacemit,k1-syscon.h +141 -0
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2.45.2
PATCH v12 2/6 soc: spacemit: create a header for clock/reset registers
In reply to Alex ElderMove the definitions of register offsets and fields used by the SpacemiT K1 SoC CCUs into a separate header file, so that they can be shared by the reset driver that will be found under drivers/reset.
--- drivers/clk/spacemit/ccu-k1.c | 111 +---------------------------- include/soc/spacemit/k1-syscon.h | 118 +++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+), 110 deletions(-) create mode 100644 include/soc/spacemit/k1-syscon.h
drivers/clk/spacemit/ccu-k1.c +1 -110
@@ -11,6 +11,7 @@#include <linux/minmax.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <soc/spacemit/k1-syscon.h> #include "ccu_common.h" #include "ccu_pll.h"
@@ -19,116 +20,6 @@#include <dt-bindings/clock/spacemit,k1-syscon.h> -/* APBS register offset */ -#define APBS_PLL1_SWCR1 0x100 -#define APBS_PLL1_SWCR2 0x104 -#define APBS_PLL1_SWCR3 0x108 -#define APBS_PLL2_SWCR1 0x118 -#define APBS_PLL2_SWCR2 0x11c -#define APBS_PLL2_SWCR3 0x120 -#define APBS_PLL3_SWCR1 0x124 -#define APBS_PLL3_SWCR2 0x128 -#define APBS_PLL3_SWCR3 0x12c - -/* MPMU register offset */ -#define MPMU_POSR 0x0010 -#define POSR_PLL1_LOCK BIT(27) -#define POSR_PLL2_LOCK BIT(28) -#define POSR_PLL3_LOCK BIT(29) -#define MPMU_SUCCR 0x0014 -#define MPMU_ISCCR 0x0044 -#define MPMU_WDTPCR 0x0200 -#define MPMU_RIPCCR 0x0210 -#define MPMU_ACGR 0x1024 -#define MPMU_APBCSCR 0x1050 -#define MPMU_SUCCR_1 0x10b0 - -/* APBC register offset */ -#define APBC_UART1_CLK_RST 0x00 -#define APBC_UART2_CLK_RST 0x04 -#define APBC_GPIO_CLK_RST 0x08 -#define APBC_PWM0_CLK_RST 0x0c -#define APBC_PWM1_CLK_RST 0x10 -#define APBC_PWM2_CLK_RST 0x14 -#define APBC_PWM3_CLK_RST 0x18 -#define APBC_TWSI8_CLK_RST 0x20 -#define APBC_UART3_CLK_RST 0x24 -#define APBC_RTC_CLK_RST 0x28 -#define APBC_TWSI0_CLK_RST 0x2c -#define APBC_TWSI1_CLK_RST 0x30 -#define APBC_TIMERS1_CLK_RST 0x34 -#define APBC_TWSI2_CLK_RST 0x38 -#define APBC_AIB_CLK_RST 0x3c -#define APBC_TWSI4_CLK_RST 0x40 -#define APBC_TIMERS2_CLK_RST 0x44 -#define APBC_ONEWIRE_CLK_RST 0x48 -#define APBC_TWSI5_CLK_RST 0x4c -#define APBC_DRO_CLK_RST 0x58 -#define APBC_IR_CLK_RST 0x5c -#define APBC_TWSI6_CLK_RST 0x60 -#define APBC_COUNTER_CLK_SEL 0x64 -#define APBC_TWSI7_CLK_RST 0x68 -#define APBC_TSEN_CLK_RST 0x6c -#define APBC_UART4_CLK_RST 0x70 -#define APBC_UART5_CLK_RST 0x74 -#define APBC_UART6_CLK_RST 0x78 -#define APBC_SSP3_CLK_RST 0x7c -#define APBC_SSPA0_CLK_RST 0x80 -#define APBC_SSPA1_CLK_RST 0x84 -#define APBC_IPC_AP2AUD_CLK_RST 0x90 -#define APBC_UART7_CLK_RST 0x94 -#define APBC_UART8_CLK_RST 0x98 -#define APBC_UART9_CLK_RST 0x9c -#define APBC_CAN0_CLK_RST 0xa0 -#define APBC_PWM4_CLK_RST 0xa8 -#define APBC_PWM5_CLK_RST 0xac -#define APBC_PWM6_CLK_RST 0xb0 -#define APBC_PWM7_CLK_RST 0xb4 -#define APBC_PWM8_CLK_RST 0xb8 -#define APBC_PWM9_CLK_RST 0xbc -#define APBC_PWM10_CLK_RST 0xc0 -#define APBC_PWM11_CLK_RST 0xc4 -#define APBC_PWM12_CLK_RST 0xc8 -#define APBC_PWM13_CLK_RST 0xcc -#define APBC_PWM14_CLK_RST 0xd0 -#define APBC_PWM15_CLK_RST 0xd4 -#define APBC_PWM16_CLK_RST 0xd8 -#define APBC_PWM17_CLK_RST 0xdc -#define APBC_PWM18_CLK_RST 0xe0 -#define APBC_PWM19_CLK_RST 0xe4 - -/* APMU register offset */ -#define APMU_JPG_CLK_RES_CTRL 0x020 -#define APMU_CSI_CCIC2_CLK_RES_CTRL 0x024 -#define APMU_ISP_CLK_RES_CTRL 0x038 -#define APMU_LCD_CLK_RES_CTRL1 0x044 -#define APMU_LCD_SPI_CLK_RES_CTRL 0x048 -#define APMU_LCD_CLK_RES_CTRL2 0x04c -#define APMU_CCIC_CLK_RES_CTRL 0x050 -#define APMU_SDH0_CLK_RES_CTRL 0x054 -#define APMU_SDH1_CLK_RES_CTRL 0x058 -#define APMU_USB_CLK_RES_CTRL 0x05c -#define APMU_QSPI_CLK_RES_CTRL 0x060 -#define APMU_DMA_CLK_RES_CTRL 0x064 -#define APMU_AES_CLK_RES_CTRL 0x068 -#define APMU_VPU_CLK_RES_CTRL 0x0a4 -#define APMU_GPU_CLK_RES_CTRL 0x0cc -#define APMU_SDH2_CLK_RES_CTRL 0x0e0 -#define APMU_PMUA_MC_CTRL 0x0e8 -#define APMU_PMU_CC2_AP 0x100 -#define APMU_PMUA_EM_CLK_RES_CTRL 0x104 -#define APMU_AUDIO_CLK_RES_CTRL 0x14c -#define APMU_HDMI_CLK_RES_CTRL 0x1b8 -#define APMU_CCI550_CLK_CTRL 0x300 -#define APMU_ACLK_CLK_CTRL 0x388 -#define APMU_CPU_C0_CLK_CTRL 0x38C -#define APMU_CPU_C1_CLK_CTRL 0x390 -#define APMU_PCIE_CLK_RES_CTRL_0 0x3cc -#define APMU_PCIE_CLK_RES_CTRL_1 0x3d4 -#define APMU_PCIE_CLK_RES_CTRL_2 0x3dc -#define APMU_EMAC0_CLK_RES_CTRL 0x3e4 -#define APMU_EMAC1_CLK_RES_CTRL 0x3ec -struct spacemit_ccu_data {struct clk_hw **hws;size_t num;
include/soc/spacemit/k1-syscon.h new file +118 -0
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2.45.2
PATCH v12 3/6 clk: spacemit: set up reset auxiliary devices
In reply to Alex ElderAdd a new reset_name field to the spacemit_ccu_data structure. If it is non-null, the CCU implements a reset controller, and the name will be used in the name for the auxiliary device that implements it.
Define a new type to hold an auxiliary device as well as the regmap pointer that will be needed by CCU reset controllers. Set up code to initialize and add an auxiliary device for any CCU that implements reset functionality.
Make it optional for a CCU to implement a clock controller. This doesn't apply to any of the existing CCUs but will for some new ones that will be added soon.
--- drivers/clk/spacemit/Kconfig | 1 + drivers/clk/spacemit/ccu-k1.c | 104 ++++++++++++++++++++++++++++--- include/soc/spacemit/k1-syscon.h | 12 ++++ 3 files changed, 107 insertions(+), 10 deletions(-)
drivers/clk/spacemit/Kconfig +1 -0
@@ -3,6 +3,7 @@ config SPACEMIT_CCU tristate "Clock support for SpacemiT SoCs" depends on ARCH_SPACEMIT || COMPILE_TEST + select AUXILIARY_BUS select MFD_SYSCON help Say Y to enable clock controller unit support for SpacemiT SoCs.
drivers/clk/spacemit/ccu-k1.c +94 -10
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include/soc/spacemit/k1-syscon.h +12 -0
@@ -5,6 +5,18 @@#ifndef __SOC_K1_SYSCON_H__#define __SOC_K1_SYSCON_H__ +/* Auxiliary device used to represent a CCU reset controller */ +struct spacemit_ccu_adev { +struct auxiliary_device adev; +struct regmap *regmap; +}; + +static inline struct spacemit_ccu_adev * +to_spacemit_ccu_adev (struct auxiliary_device *adev) +{ + return container_of(adev, struct spacemit_ccu_adev, adev); +} +/* APBS register offset */ #define APBS_PLL1_SWCR1 0x100#define APBS_PLL1_SWCR2 0x104
Signature · 1 line
2.45.2
PATCH v12 4/6 clk: spacemit: define three reset-only CCUs
In reply to Alex ElderThree CCUs on the SpacemiT K1 SoC implement only resets, not clocks. Define the CCU data for these resets so their auxiliary devices get created.
--- drivers/clk/spacemit/ccu-k1.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
drivers/clk/spacemit/ccu-k1.c +24 -0
@@ -943,6 +943,18 @@ static const struct spacemit_ccu_data k1_ccu_apmu_data = { .num = ARRAY_SIZE(k1_ccu_apmu_hws), }; +static const struct spacemit_ccu_data k1_ccu_rcpu_data = { + .reset_name ="rcpu-reset" , +}; + +static const struct spacemit_ccu_data k1_ccu_rcpu2_data = { + .reset_name ="rcpu2-reset" , +}; + +static const struct spacemit_ccu_data k1_ccu_apbc2_data = { + .reset_name ="apbc2-reset" , +}; + static int spacemit_ccu_register(struct device *dev, struct regmap *regmap, struct regmap *lock_regmap,
@@ -1121,6 +1133,18 @@ static const struct of_device_id of_k1_ccu_match[] = { .compatible = "spacemit,k1-syscon-apmu", .data = &k1_ccu_apmu_data, }, + { + .compatible = "spacemit,k1-syscon-rcpu", + .data = &k1_ccu_rcpu_data, + }, + { + .compatible = "spacemit,k1-syscon-rcpu2", + .data = &k1_ccu_rcpu2_data, + }, + { + .compatible = "spacemit,k1-syscon-apbc2", + .data = &k1_ccu_apbc2_data, + }, { } }; MODULE_DEVICE_TABLE(of, of_k1_ccu_match);
Signature · 1 line
2.45.2
PATCH v12 5/6 reset: spacemit: add support for SpacemiT CCU resets
In reply to Alex ElderImplement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU).
This patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. It also adds RCPU, RCPU2, and ACPB2 CCUs, which only define resets.
---
v12: - Rename PCIe resets to align with their clock counterparts
drivers/reset/Kconfig | 9 + drivers/reset/Makefile | 1 + drivers/reset/reset-spacemit.c | 304 +++++++++++++++++++++++++++++++ include/soc/spacemit/k1-syscon.h | 30 +++ 4 files changed, 344 insertions(+) create mode 100644 drivers/reset/reset-spacemit.c
drivers/reset/Kconfig +9 -0
@@ -279,6 +279,15 @@ config RESET_SOCFPGA This enables the reset driver for the SoCFPGA ARMv7 platforms. This driver gets initialized early during platform init calls. +config RESET_SPACEMIT + tristate "SpacemiT reset driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + select AUXILIARY_BUS + default ARCH_SPACEMIT + help + This enables the reset controller driver for SpacemiT SoCs, + including the K1. + config RESET_SUNPLUS bool "Sunplus SoCs Reset Driver" if COMPILE_TEST default ARCH_SUNPLUS
drivers/reset/Makefile +1 -0
@@ -36,6 +36,7 @@ obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o +obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_TH1520) += reset-th1520.o
drivers/reset/reset-spacemit.c new file +304 -0
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include/soc/spacemit/k1-syscon.h +30 -0
@@ -127,4 +127,34 @@ to_spacemit_ccu_adev(struct auxiliary_device *adev)#define APMU_EMAC0_CLK_RES_CTRL 0x3e4#define APMU_EMAC1_CLK_RES_CTRL 0x3ec +/* RCPU register offsets */ +#define RCPU_SSP0_CLK_RST 0x0028 +#define RCPU_I2C0_CLK_RST 0x0030 +#define RCPU_UART1_CLK_RST 0x003c +#define RCPU_CAN_CLK_RST 0x0048 +#define RCPU_IR_CLK_RST 0x004c +#define RCPU_UART0_CLK_RST 0x00d8 +#define AUDIO_HDMI_CLK_CTRL 0x2044 + +/* RCPU2 register offsets */ +#define RCPU2_PWM0_CLK_RST 0x0000 +#define RCPU2_PWM1_CLK_RST 0x0004 +#define RCPU2_PWM2_CLK_RST 0x0008 +#define RCPU2_PWM3_CLK_RST 0x000c +#define RCPU2_PWM4_CLK_RST 0x0010 +#define RCPU2_PWM5_CLK_RST 0x0014 +#define RCPU2_PWM6_CLK_RST 0x0018 +#define RCPU2_PWM7_CLK_RST 0x001c +#define RCPU2_PWM8_CLK_RST 0x0020 +#define RCPU2_PWM9_CLK_RST 0x0024 + +/* APBC2 register offsets */ +#define APBC2_UART1_CLK_RST 0x0000 +#define APBC2_SSP2_CLK_RST 0x0004 +#define APBC2_TWSI3_CLK_RST 0x0008 +#define APBC2_RTC_CLK_RST 0x000c +#define APBC2_TIMERS0_CLK_RST 0x0010 +#define APBC2_KPC_CLK_RST 0x0014 +#define APBC2_GPIO_CLK_RST 0x001c +#endif /* __SOC_K1_SYSCON_H__ */
Signature · 1 line
2.45.2
Re: [PATCH v12 5/6] reset: spacemit: add support for SpacemiT CCU resets
Hi Stephen, Mike
Quoted 10 lines · Alex Elder
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU).
This patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. It also adds RCPU, RCPU2, and ACPB2 CCUs, which only define resets.
Signed-off-by Alex Elder <[email protected]>Reviewed-by Philipp Zabel <[email protected]>Reviewed-by Yixun Lan <[email protected]>
To be merged via the clk tree, if Stephen is ok with that.
regards
Philipp
Re: [PATCH v12 5/6] reset: spacemit: add support for SpacemiT CCU resets
Hi Philipp, Stephen, Mike
Quoted 10 lines · Philipp Zabel
Hi Stephen, Mike
Quoted 7 lines · Alex Elder
Implement reset support for SpacemiT CCUs. A SpacemiT reset controller device is an auxiliary device associated with a clock controller (CCU).
This patch defines the reset controllers for the MPMU, APBC, and MPMU CCUs, which already define clock controllers. It also adds RCPU, RCPU2, and ACPB2 CCUs, which only define resets.
Quoted 8 lines
Quoted 3 lines
Signed-off-by Alex Elder <[email protected]>Reviewed-by Philipp Zabel <[email protected]>Reviewed-by Yixun Lan <[email protected]>Acked-by Philipp Zabel <[email protected]>To be merged via the clk tree, if Stephen is ok with that.
ok, I'll just go ahead and prepare a PR for this,
and leave Stephen to take care of the rest..
thanks all!
Signature · 1 line
Yixun Lan (dlan)
PATCH v12 6/6 riscv: dts: spacemit: add reset support for the K1 SoC
In reply to Alex ElderDefine syscon nodes for the RCPU, RCPU2, and APBC2 SpacemiT CCUS, which currently support resets but not clocks in the SpacemiT K1.
--- arch/riscv/boot/dts/spacemit/k1.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/riscv/boot/dts/spacemit/k1.dtsi +18 -0
@@ -346,6 +346,18 @@ soc { dma-noncoherent; ranges; + syscon_rcpu: system-controller@c0880000 { + compatible = "spacemit,k1-syscon-rcpu"; + reg = <0x0 0xc0880000 0x0 0x2048>; + #reset-cells = <1>; + }; + + syscon_rcpu2: system-controller@c0888000 { + compatible = "spacemit,k1-syscon-rcpu2"; + reg = <0x0 0xc0888000 0x0 0x28>; + #reset-cells = <1>; + }; + syscon_apbc: system-controller@d4015000 { compatible = "spacemit,k1-syscon-apbc"; reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -562,6 +574,12 @@ clint: timer@e4000000 { <&cpu7_intc 3>, <&cpu7_intc 7>; }; + syscon_apbc2: system-controller@f0610000 { + compatible = "spacemit,k1-syscon-apbc2"; + reg = <0x0 0xf0610000 0x0 0x20>; + #reset-cells = <1>; + }; + sec_uart1: serial@f0612000 { compatible = "spacemit,k1-uart", "intel,xscale-uart"; reg = <0x0 0xf0612000 0x0 0x100>;
Signature · 1 line
2.45.2
Yixun Lan
AppliedRe: (subset) [PATCH v12 0/6] reset: spacemit: add K1 reset support
In reply to Alex ElderQuoted 11 lines · Alex Elder
This series adds reset controller support for the SpacemiT K1 SoC. A SpacemiT reset controller is implemented as an auxiliary device associated with a clock controller (CCU). A new header file holds definitions used by both the clock and reset drivers.
The only change in this version is that three of the the four resets associated with each PCIe port have been renamed, to align better with their corresponding clocks. This affects patches 1 and 5. For example, for PCIe port 0:
[...]
Applied, thanks!
[1/6] dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
https://github.com/spacemit-com/linux/commit/25a59e813cd2ca728047f657d64f9b29480be393 [2/6] soc: spacemit: create a header for clock/reset registers https://github.com/spacemit-com/linux/commit/bf6239ddaa6a73a44cd8ea3afec5fc82ed900038 [3/6] clk: spacemit: set up reset auxiliary devices https://github.com/spacemit-com/linux/commit/988543522ebd6a9af53c288833503f0501e401b0 [4/6] clk: spacemit: define three reset-only CCUs https://github.com/spacemit-com/linux/commit/024b84f661674dcfa1341c90ce654c485c4ab756 [5/6] reset: spacemit: add support for SpacemiT CCU resets https://github.com/spacemit-com/linux/commit/c479d7cf06c3d65532442fa368b058e05dbba1a2
Best regards,
Signature · 1 line
Yixun Lan
Yixun Lan
AppliedRe: (subset) [PATCH v12 0/6] reset: spacemit: add K1 reset support
In reply to Alex ElderQuoted 11 lines · Alex Elder
This series adds reset controller support for the SpacemiT K1 SoC. A SpacemiT reset controller is implemented as an auxiliary device associated with a clock controller (CCU). A new header file holds definitions used by both the clock and reset drivers.
The only change in this version is that three of the the four resets associated with each PCIe port have been renamed, to align better with their corresponding clocks. This affects patches 1 and 5. For example, for PCIe port 0:
[...]
Applied, thanks!
[6/6] riscv: dts: spacemit: add reset support for the K1 SoC
https://github.com/spacemit-com/linux/commit/2c0cf4fed0f440200833ddfc24ea02de2cdc217c
Best regards,
Signature · 1 line
Yixun Lan