FAILED: patch "[PATCH] ALSA: hda: Add missing NVIDIA HDA codec IDs" failed to apply to 6.6-stable tree
Subsystems (2)
[email protected]
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x e0a911ac86857a73182edde9e50d9b4b949b7f01
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2025071243-multiple-shimmer-e8b6@gregkh' --subject-prefix 'PATCH 6.6.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From e0a911ac86857a73182edde9e50d9b4b949b7f01 Mon Sep 17 00:00:00 2001
From: Daniel Dadap <[email protected]>
Date: Thu, 26 Jun 2025 16:16:30 -0500
Subject: [PATCH] ALSA: hda: Add missing NVIDIA HDA codec IDs
Add codec IDs for several NVIDIA products with HDA controllers to the snd_hda_id_hdmi[] patch table.
Signed-off-by Daniel Dadap <[email protected]>
Cc <[email protected]>
Signed-off-by Takashi Iwai <[email protected]>
sound/pci/hda/patch_hdmi.c +19 -0
@@ -4551,7 +4551,9 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de002f ,"Tegra194 HDMI/DP2" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0030 ,"Tegra194 HDMI/DP3" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0031 ,"Tegra234 HDMI/DP" , patch_tegra234_hdmi), +HDA_CODEC_ENTRY (0x10de0033 ,"SoC 33 HDMI/DP" , patch_tegra234_hdmi),HDA_CODEC_ENTRY (0x10de0034 ,"Tegra264 HDMI/DP" , patch_tegra234_hdmi), +HDA_CODEC_ENTRY (0x10de0035 ,"SoC 35 HDMI/DP" , patch_tegra234_hdmi),HDA_CODEC_ENTRY (0x10de0040 ,"GPU 40 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0041 ,"GPU 41 HDMI/DP" , patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
@@ -4590,15 +4592,32 @@ HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0098 ,"GPU 98 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0099 ,"GPU 99 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009a ,"GPU 9a HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de009b ,"GPU 9b HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de009c ,"GPU 9c HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009d ,"GPU 9d HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009e ,"GPU 9e HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009f ,"GPU 9f HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a0 ,"GPU a0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a1 ,"GPU a1 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a3 ,"GPU a3 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a4 ,"GPU a4 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a5 ,"GPU a5 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a6 ,"GPU a6 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a7 ,"GPU a7 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a8 ,"GPU a8 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a9 ,"GPU a9 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00aa ,"GPU aa HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ab ,"GPU ab HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ad ,"GPU ad HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ae ,"GPU ae HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00af ,"GPU af HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00b0 ,"GPU b0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00b1 ,"GPU b1 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c0 ,"GPU c0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c1 ,"GPU c1 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c3 ,"GPU c3 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c4 ,"GPU c4 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c5 ,"GPU c5 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de8001 ,"MCP73 HDMI" , patch_nvhdmi_2ch),HDA_CODEC_ENTRY (0x10de8067 ,"MCP67/68 HDMI" , patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
Sasha Levin
maintainerPATCH 1/2 ALSA: hda/tegra: Add Tegra264 support
From: Mohan Kumar D <[email protected]>
[ Upstream commit 1c4193917eb3279788968639f24d72ffeebdec6b ]
Update HDA driver to support Tegra264 differences from legacy HDA, which includes: clocks/resets, always power on, and hardware-managed FPCI/IPFS initialization. The driver retrieves this chip-specific information from soc_data.
Signed-off-by Mohan Kumar D <[email protected]>
Signed-off-by Sheetal <[email protected]>
Signed-off-by Takashi Iwai <[email protected]>
Stable-dep-of: e0a911ac8685 ("ALSA: hda: Add missing NVIDIA HDA codec IDs")
Signed-off-by Sasha Levin <[email protected]>
--- sound/pci/hda/hda_tegra.c | 51 +++++++++++++++++++++++++++++++++----- sound/pci/hda/patch_hdmi.c | 1 + 2 files changed, 46 insertions(+), 6 deletions(-)
sound/pci/hda/hda_tegra.c +45 -6
@@ -72,6 +72,10 @@struct hda_tegra_soc {bool has_hda2codec_2x_reset;bool has_hda2hdmi; +bool has_hda2codec_2x; +bool input_stream; +bool always_on; +bool requires_init; };struct hda_tegra {
@@ -187,7 +191,9 @@ static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)if (rc !=0 )return rc;if (chip->running) { -hda_tegra_init (hda); +if (hda->soc->requires_init) +hda_tegra_init (hda); +azx_init_chip (chip,1 );/* disable controller wake up event*/ azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
@@ -252,7 +258,8 @@ static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev) bus->remap_addr = hda->regs +HDA_BAR0 ; bus->addr = res->start +HDA_BAR0 ; -hda_tegra_init (hda); +if (hda->soc->requires_init) +hda_tegra_init (hda);return 0 ; }
@@ -325,7 +332,7 @@ static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)* starts with offset 0 which is wrong as HW register for output stream * offset starts with 4. */ -if (of_device_is_compatible (np,"nvidia,tegra234-hda" )) +if (!hda->soc->input_stream) chip->capture_streams =4 ; chip->playback_streams = (gcap >>12 ) &0x0f ;
@@ -421,7 +428,6 @@ static int hda_tegra_create(struct snd_card *card, chip->driver_caps = driver_caps; chip->driver_type = driver_caps &0xff ; chip->dev_index =0 ; - chip->jackpoll_interval =msecs_to_jiffies (5000 );INIT_LIST_HEAD (&chip->pcm_list); chip->codec_probe_mask =-1 ;
@@ -438,7 +444,16 @@ static int hda_tegra_create(struct snd_card *card, chip->bus.core.sync_write =0 ; chip->bus.core.needs_damn_long_delay =1 ; chip->bus.core.aligned_mmio =1 ; - chip->bus.jackpoll_in_suspend =1 ; + +/* +* HDA power domain and clocks are always on for Tegra264 and +* the jack detection logic would work always, so no need of +* jack polling mechanism running. +*/ +if (!hda->soc->always_on) { + chip->jackpoll_interval =msecs_to_jiffies (5000 ); + chip->bus.jackpoll_in_suspend =1 ; + } err =snd_device_new (card,SNDRV_DEV_LOWLEVEL , chip, &ops);if (err <0 ) {
@@ -452,22 +467,44 @@ static int hda_tegra_create(struct snd_card *card,static const struct hda_tegra_soc tegra30_data = { .has_hda2codec_2x_reset = true, .has_hda2hdmi = true, + .has_hda2codec_2x = true, + .input_stream = true, + .always_on = false, + .requires_init = true, };static const struct hda_tegra_soc tegra194_data = { .has_hda2codec_2x_reset = false, .has_hda2hdmi = true, + .has_hda2codec_2x = true, + .input_stream = true, + .always_on = false, + .requires_init = true, };static const struct hda_tegra_soc tegra234_data = { .has_hda2codec_2x_reset = true, .has_hda2hdmi = false, + .has_hda2codec_2x = true, + .input_stream = false, + .always_on = false, + .requires_init = true, +}; + +static const struct hda_tegra_soc tegra264_data = { + .has_hda2codec_2x_reset = true, + .has_hda2hdmi = false, + .has_hda2codec_2x = false, + .input_stream = false, + .always_on = true, + .requires_init = false, };static const struct of_device_id hda_tegra_match[] = { { .compatible ="nvidia,tegra30-hda" , .data = &tegra30_data }, { .compatible ="nvidia,tegra194-hda" , .data = &tegra194_data }, { .compatible ="nvidia,tegra234-hda" , .data = &tegra234_data }, + { .compatible ="nvidia,tegra264-hda" , .data = &tegra264_data }, {}, };MODULE_DEVICE_TABLE (of, hda_tegra_match);
@@ -522,7 +559,9 @@ static int hda_tegra_probe(struct platform_device *pdev) hda->clocks[hda->nclocks++].id ="hda" ;if (hda->soc->has_hda2hdmi) hda->clocks[hda->nclocks++].id ="hda2hdmi" ; - hda->clocks[hda->nclocks++].id ="hda2codec_2x" ; + +if (hda->soc->has_hda2codec_2x) + hda->clocks[hda->nclocks++].id ="hda2codec_2x" ; err =devm_clk_bulk_get (&pdev->dev, hda->nclocks, hda->clocks);if (err <0 )
sound/pci/hda/patch_hdmi.c +1 -0
@@ -4559,6 +4559,7 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de002f ,"Tegra194 HDMI/DP2" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0030 ,"Tegra194 HDMI/DP3" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0031 ,"Tegra234 HDMI/DP" , patch_tegra234_hdmi), +HDA_CODEC_ENTRY (0x10de0034 ,"Tegra264 HDMI/DP" , patch_tegra234_hdmi),HDA_CODEC_ENTRY (0x10de0040 ,"GPU 40 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0041 ,"GPU 41 HDMI/DP" , patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
Signature · 1 line
2.39.5
Sasha Levin
maintainerPATCH 2/2 ALSA: hda: Add missing NVIDIA HDA codec IDs
From: Daniel Dadap <[email protected]>
[ Upstream commit e0a911ac86857a73182edde9e50d9b4b949b7f01 ]
Add codec IDs for several NVIDIA products with HDA controllers to the snd_hda_id_hdmi[] patch table.
Signed-off-by Daniel Dadap <[email protected]>
Cc <[email protected]>
Signed-off-by Takashi Iwai <[email protected]>
Signed-off-by Sasha Levin <[email protected]>
--- sound/pci/hda/patch_hdmi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
sound/pci/hda/patch_hdmi.c +19 -0
@@ -4559,7 +4559,9 @@ HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de002f ,"Tegra194 HDMI/DP2" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0030 ,"Tegra194 HDMI/DP3" , patch_tegra_hdmi),HDA_CODEC_ENTRY (0x10de0031 ,"Tegra234 HDMI/DP" , patch_tegra234_hdmi), +HDA_CODEC_ENTRY (0x10de0033 ,"SoC 33 HDMI/DP" , patch_tegra234_hdmi),HDA_CODEC_ENTRY (0x10de0034 ,"Tegra264 HDMI/DP" , patch_tegra234_hdmi), +HDA_CODEC_ENTRY (0x10de0035 ,"SoC 35 HDMI/DP" , patch_tegra234_hdmi),HDA_CODEC_ENTRY (0x10de0040 ,"GPU 40 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0041 ,"GPU 41 HDMI/DP" , patch_nvhdmi), HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
@@ -4598,15 +4600,32 @@ HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0098 ,"GPU 98 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de0099 ,"GPU 99 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009a ,"GPU 9a HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de009b ,"GPU 9b HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de009c ,"GPU 9c HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009d ,"GPU 9d HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009e ,"GPU 9e HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de009f ,"GPU 9f HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a0 ,"GPU a0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a1 ,"GPU a1 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a3 ,"GPU a3 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a4 ,"GPU a4 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a5 ,"GPU a5 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a6 ,"GPU a6 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de00a7 ,"GPU a7 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a8 ,"GPU a8 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00a9 ,"GPU a9 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00aa ,"GPU aa HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ab ,"GPU ab HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ad ,"GPU ad HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00ae ,"GPU ae HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00af ,"GPU af HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00b0 ,"GPU b0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00b1 ,"GPU b1 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c0 ,"GPU c0 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c1 ,"GPU c1 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c3 ,"GPU c3 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c4 ,"GPU c4 HDMI/DP" , patch_nvhdmi), +HDA_CODEC_ENTRY (0x10de00c5 ,"GPU c5 HDMI/DP" , patch_nvhdmi),HDA_CODEC_ENTRY (0x10de8001 ,"MCP73 HDMI" , patch_nvhdmi_2ch),HDA_CODEC_ENTRY (0x10de8067 ,"MCP67/68 HDMI" , patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
Signature · 1 line
2.39.5