arm64: dts: nuvoton: Add NPCM845 SoC and EVB support

PATCH Superseded Tomer Maimon 2 participants 11 messages Jul 17, 2025 – Jul 29, 2025

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Device tree bindings Arm/nuvoton npcm architecture

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Tomer Maimon

author maintainer

2025-07-17 13:53 UTC #0 lore raw

cover arm64: dts: nuvoton: Add NPCM845 SoC and EVB support

This series adds device tree support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation Board (EVB).
The first patch introduces peripheral nodes for Ethernet, MMC, SPI, USB, RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device tree. The second patch enables these peripherals for the NPCM845-EVB, adding MDIO nodes, reserved memory, aliases, and board-specific configurations like PHY modes and SPI flash partitions.

The series depends on a separate pinctrl patch for NPCM845 pinmux groups.

Tomer Maimon (2):
arm64: dts: nuvoton: npcm845: Add peripheral nodes
arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 695 ++++++++++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 +++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 3 files changed, 1147 insertions(+)

Signature · 1 line

2.34.1

Tomer Maimon

author maintainer

2025-07-17 13:54 UTC #1 lore raw

PATCH 1/2 arm64: dts: nuvoton: npcm845: Add peripheral nodes

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.
This patch enhances functionality for NPCM845-based platforms.

Depends-on: ARM: dts: nuvoton: npcm845: Add pinctrl groups

Signed-off-by Tomer Maimon <[email protected]>

---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 695 ++++++++++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 2 files changed, 702 insertions(+)

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +695 -0

index 5cd877e6c20a..3564e0e30791 100644
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <2>;

@@ -40,6 +41,11 @@ ppi_cluster0: interrupt-partition-0 {
 		};
 	};
 
+	udc0_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+	};
+
 	ahb {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -56,6 +62,259 @@ clk: rstc: reset-controller@f0801000 {
 			#clock-cells = <1>;
 		};
 
+		gmac1: eth@f0804000 {
+			device_type = "network";
+			compatible = "snps,dwmac";
+			reg = <0x0 0xf0804000 0x0 0x2000>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg2_pins
+					&rg2mdio_pins>;
+			status = "disabled";
+		};
+
+		gmac2: eth@f0806000 {
+			device_type = "network";
+			compatible = "snps,dwmac";
+			reg = <0x0 0xf0806000 0x0 0x2000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r1_pins
+					&r1err_pins
+					&r1md_pins>;
+			status = "disabled";
+		};
+
+		gmac3: eth@f0808000 {
+			device_type = "network";
+			compatible = "snps,dwmac";
+			reg = <0x0 0xf0808000 0x0 0x2000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r2_pins
+					&r2err_pins
+					&r2md_pins>;
+			status = "disabled";
+		};
+
+		sdhci: mmc@f0842000 {
+			compatible = "nuvoton,npcm845-sdhci";
+			reg = <0x0 0xf0842000 0x0 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "clk_mmc";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc8_pins
+				     &mmc_pins>;
+			status = "disabled";
+		};
+
+		fiu0: spi@fb000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI0>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
+		fiu1: spi@fb002000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb002000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI1>;
+			clock-names = "clk_spi1";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
+			status = "disabled";
+		};
+
+		fiu3: spi@c0000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xc0000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI3>;
+			clock-names = "clk_spi3";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi3_pins>;
+			status = "disabled";
+		};
+
+		fiux: spi@fb001000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb001000 0x0 0x1000>,
+			<0x0 0xf8000000 0x0 0x2000000>;
+			reg-names = "control", "memory";
+			clocks =  <&clk NPCM8XX_CLK_SPIX>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
+		mc: memory-controller@f0824000 {
+			compatible = "nuvoton,npcm845-memory-controller";
+			reg = <0x0 0xf0824000 0x0 0x1000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		udc0:usb@f0830000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0830000 0x0 0x1000
+			       0x0 0xfffeb000 0x0 0x800>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc1:usb@f0831000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0831000 0x0 0x1000
+			       0x0 0xfffeb800 0x0 0x800>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc2:usb@f0832000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0832000 0x0 0x1000
+			       0x0 0xfffec000 0x0 0x800>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc3:usb@f0833000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0833000 0x0 0x1000
+			       0x0 0xfffec800 0x0 0x800>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc4:usb@f0834000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0834000 0x0 0x1000
+			       0x0 0xfffed000 0x0 0x800>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc5:usb@f0835000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0835000 0x0 0x1000
+			       0x0 0xfffed800 0x0 0x800>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc6:usb@f0836000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0836000 0x0 0x1000
+			       0x0 0xfffee000 0x0 0x800>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc7:usb@f0837000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0837000 0x0 0x1000
+			       0x0 0xfffee800 0x0 0x800>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc8:usb@f0838000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0838000 0x0 0x1000
+			       0x0 0xfffef000 0x0 0x800>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc9:usb@f0839000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0839000 0x0 0x1000
+			       0x0 0xfffef800 0x0 0x800>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;

@@ -64,6 +323,20 @@ apb {
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
 
+			pspi: spi@201000 {
+				compatible = "nuvoton,npcm845-pspi";
+				reg = <0x201000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks =  <&clk NPCM8XX_CLK_APB5>;
+				clock-names = "clk_apb5";
+				resets = <&rstc 0x24 23>;
+				status = "disabled";
+			};
+
 			peci: peci-controller@100000 {
 				compatible = "nuvoton,npcm845-peci";
 				reg = <0x100000 0x1000>;

@@ -144,6 +417,22 @@ serial6: serial@6000 {
 				status = "disabled";
 			};
 
+			rng: rng@b000 {
+				compatible = "nuvoton,npcm845-rng";
+				reg = <0xb000 0x8>;
+				clocks =  <&clk NPCM8XX_CLK_APB1>;
+				status = "disabled";
+			};
+
+			adc: adc@c000 {
+				compatible = "nuvoton,npcm845-adc";
+				reg = <0xC000 0x8>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM8XX_CLK_ADC>;
+				resets = <&rstc 0x20 27>;
+				status = "disabled";
+			};
+
 			watchdog0: watchdog@801c {
 				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

@@ -170,6 +459,412 @@ watchdog2: watchdog@a01c {
 				clocks = <&refclk>;
 				syscon = <&gcr>;
 			};
+
+			pwm_fan:pwm-fan-controller@103000 {
+				compatible = "nuvoton,npcm845-pwm-fan";
+				reg = <0x103000 0x3000>,
+					<0x180000 0x8000>;
+				reg-names = "pwm", "fan";
+				clocks =  <&clk NPCM8XX_CLK_APB3>,
+					<&clk NPCM8XX_CLK_APB4>;
+				clock-names = "pwm","fan";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pwm0_pins &pwm1_pins
+						&pwm2_pins &pwm3_pins
+						&pwm4_pins &pwm5_pins
+						&pwm6_pins &pwm7_pins
+						&pwm8_pins &pwm9_pins
+						&pwm10_pins &pwm11_pins
+						&fanin0_pins &fanin1_pins
+						&fanin2_pins &fanin3_pins
+						&fanin4_pins &fanin5_pins
+						&fanin6_pins &fanin7_pins
+						&fanin8_pins &fanin9_pins
+						&fanin10_pins &fanin11_pins
+						&fanin12_pins &fanin13_pins
+						&fanin14_pins &fanin15_pins>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@80000 {
+				reg = <0x80000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb0_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@81000 {
+				reg = <0x81000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb1_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@82000 {
+				reg = <0x82000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb2_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@83000 {
+				reg = <0x83000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb3_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@84000 {
+				reg = <0x84000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb4_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@85000 {
+				reg = <0x85000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb5_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@86000 {
+				reg = <0x86000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb6_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@87000 {
+				reg = <0x87000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb7_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@88000 {
+				reg = <0x88000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb8_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@89000 {
+				reg = <0x89000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb9_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@8a000 {
+				reg = <0x8a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb10_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@8b000 {
+				reg = <0x8b000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb11_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@8c000 {
+				reg = <0x8c000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb12_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c13: i2c@8d000 {
+				reg = <0x8d000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb13_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c14: i2c@8e000 {
+				reg = <0x8e000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb14_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c15: i2c@8f000 {
+				reg = <0x8f000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb15_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c16: i2c@fff00000 {
+				reg = <0xfff00000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb16_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c17: i2c@fff01000 {
+				reg = <0xfff01000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb17_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c18: i2c@fff02000 {
+				reg = <0xfff02000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb18_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c19: i2c@fff03000 {
+				reg = <0xfff03000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb19_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c20: i2c@fff04000 {
+				reg = <0xfff04000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb20_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c21: i2c@fff05000 {
+				reg = <0xfff05000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb21_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c22: i2c@fff06000 {
+				reg = <0xfff06000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb22_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c23: i2c@fff07000 {
+				reg = <0xfff07000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb23_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c24: i2c@fff08000 {
+				reg = <0xfff08000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c25: i2c@fff09000 {
+				reg = <0xfff09000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c26: i2c@fff0a000 {
+				reg = <0xfff0a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
 		};
 	};

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +7 -0

index 383938dcd3ce..21dea323612d 100644
@@ -75,4 +75,11 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2025-07-17 14:05 UTC #2 lore raw

Re: [PATCH v1 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Quoted 7 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.
This patch enhances functionality for NPCM845-based platforms.

Drop this sentence, redundant and not in style (see submitting patches).

Quoted 2 lines

Depends-on: ARM: dts: nuvoton: npcm845: Add pinctrl groups

There is no such tag.

Use changelog for this purpose or b4 dependencies.

Quoted 19 lines

Signed-off-by Tomer Maimon <[email protected]>

---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 695 ++++++++++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 2 files changed, 702 insertions(+)

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +1 -0

index 5cd877e6c20a..3564e0e30791 100644
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <2>;

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi ppi_cluster0: interrupt-partition-0 { · line 46

Quoted 6 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +3 -0

@@ -40,6 +41,11 @@ ppi_cluster0: interrupt-partition-0 {
 		};
 	};
 
+	udc0_phy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";

Please follow DTS coding style.

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 65

Quoted 10 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +3 -0

+	};
+
 	ahb {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -56,6 +62,259 @@ clk: rstc: reset-controller@f0801000 {
 			#clock-cells = <1>;
 		};
 
+		gmac1: eth@f0804000 {

Please follow established naming for node names. I'll fix whatever old stuff you took it from.

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 67

Quoted 2 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +2 -0
+			device_type = "network";
+			compatible = "snps,dwmac";

I don't think we want the generic one, even if it is allowed by bindings.

Also... You CC-ed an address, which suggests you do not work on mainline kernel or you do not use get_maintainers.pl/b4/patman. Please rebase and always work on mainline or start using mentioned tools, so correct addresses will be used.

Quoted 12 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +10 -0

+			reg = <0x0 0xf0804000 0x0 0x2000>;
 
 
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg2_pins
+					&rg2mdio_pins>;
+			status = "disabled";
+		};

...

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 176

Quoted 8 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +8 -0

+
+		mc: memory-controller@f0824000 {
+			compatible = "nuvoton,npcm845-memory-controller";
+			reg = <0x0 0xf0824000 0x0 0x1000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		udc0:usb@f0830000 {

DTS coding style...

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 189

Quoted 13 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +13 -0

+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0830000 0x0 0x1000
+			       0x0 0xfffeb000 0x0 0x800>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+

...

Best regards,
Krzysztof

Tomer Maimon

author maintainer

2025-07-28 11:30 UTC #3 lore raw

Re: [PATCH v1 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi Krzysztof

Thanks for your comments

Quoted 10 lines · Krzysztof Kozlowski

Quoted 7 lines · Tomer Maimon
Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.
This patch enhances functionality for NPCM845-based platforms.

Quoted 3 lines

Drop this sentence, redundant and not in style (see submitting patches).
Quoted 2 lines
Depends-on: ARM: dts: nuvoton: npcm845: Add pinctrl groups

Maybe it's an issue with our work mail server,
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
I believe you didn't receive the patches below as well, since I didn't see any comments. Am I correct?
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/

Quoted 28 lines

There is no such tag.

Use changelog for this purpose or b4 dependencies.

Quoted 22 lines

Signed-off-by Tomer Maimon <[email protected]>

---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 695 ++++++++++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 2 files changed, 702 insertions(+)

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +1 -0

index 5cd877e6c20a..3564e0e30791 100644
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
      #address-cells = <2>;

@@ -40,6 +41,11 @@ ppi_cluster0: interrupt-partition-0 {
              };
      };

Quoted 5 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi ppi_cluster0: interrupt-partition-0 { · line 46
Quoted 3 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +3 -0
+     udc0_phy: usb-phy {
+             #phy-cells = <0>;
+             compatible = "usb-nop-xceiv";
Please follow DTS coding style.

Do you mean the property order?

Quoted 16 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 65
Quoted 11 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +3 -0
+     };
+
      ahb {
              #address-cells = <2>;
              #size-cells = <2>;
@@ -56,6 +62,259 @@ clk: rstc: reset-controller@f0801000 {
                      #clock-cells = <1>;
              };
 
+             gmac1: eth@f0804000 {
Please follow established naming for node names. I'll fix whatever old stuff you took it from.

Quoted 4 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 67
Quoted 2 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +2 -0
+                     device_type = "network";
+                     compatible = "snps,dwmac";
I don't think we want the generic one, even if it is allowed by bindings.

Do you mean to use "snps,dwmac-3.72a" and not "snps,dwmac"?

Quoted 51 lines

Quoted 12 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +10 -0

+                     reg = <0x0 0xf0804000 0x0 0x2000>;
 
 
+                     interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                     interrupt-names = "macirq";
+                     clocks  = <&clk NPCM8XX_CLK_AHB>;
+                     clock-names = "stmmaceth";
+                     pinctrl-names = "default";
+                     pinctrl-0 = <&rg2_pins
+                                     &rg2mdio_pins>;
+                     status = "disabled";
+             };

...

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 176

Quoted 8 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +8 -0

+
+             mc: memory-controller@f0824000 {
+                     compatible = "nuvoton,npcm845-memory-controller";
+                     reg = <0x0 0xf0824000 0x0 0x1000>;
+                     interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+             };
+
+             udc0:usb@f0830000 {

DTS coding style...

Quoted 13 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +13 -0

+                     compatible = "nuvoton,npcm845-udc";
+                     reg = <0x0 0xf0830000 0x0 0x1000
+                            0x0 0xfffeb000 0x0 0x800>;
+                     interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                     clocks = <&clk NPCM8XX_CLK_SU>;
+                     clock-names = "clk_usb_bridge";
+
+                     phys = <&udc0_phy>;
+                     phy_type = "utmi_wide";
+                     dr_mode = "peripheral";
+                     status = "disabled";
+             };
+

...

Quoted 2 lines

Best regards,
Krzysztof

Thanks,

Tomer

Krzysztof Kozlowski

2025-07-29 06:21 UTC #4 lore raw

Re: [PATCH v1 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Quoted 16 lines · Tomer Maimon

Hi Krzysztof
Thanks for your comments
Quoted 10 lines · Krzysztof Kozlowski
Quoted 7 lines · Tomer Maimon
Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.
This patch enhances functionality for NPCM845-based platforms.

Quoted 7 lines

Quoted 3 lines
Drop this sentence, redundant and not in style (see submitting patches).
Quoted 2 lines
Depends-on: ARM: dts: nuvoton: npcm845: Add pinctrl groups
Maybe it's an issue with our work mail server,
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
I believe you didn't receive the patches below as well, since I didn't see any comments. Am I correct?

How is it related?

Quoted 5 lines

https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
Quoted 2 lines
There is no such tag.

Do you understand this?

Quoted 2 lines

Quoted 2 lines
Use changelog for this purpose or b4 dependencies.

Do you understand this?

Best regards,
Krzysztof

Tomer Maimon

author maintainer

2025-07-29 13:25 UTC #5 lore raw

Re: [PATCH v1 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi Krzysztof,

Quoted 20 lines · Krzysztof Kozlowski

Quoted 18 lines · Tomer Maimon
Hi Krzysztof
Thanks for your comments
Quoted 12 lines · Krzysztof Kozlowski
Quoted 7 lines · Tomer Maimon
Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.
This patch enhances functionality for NPCM845-based platforms.
Drop this sentence, redundant and not in style (see submitting patches).
Quoted 1 line

Quoted 7 lines

Quoted 5 lines
Quoted 1 line
Quoted 1 line
Depends-on: ARM: dts: nuvoton: npcm845: Add pinctrl groups
Maybe it's an issue with our work mail server,
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
I believe you didn't receive the patches below as well, since I didn't see any comments. Am I correct?
How is it related?

Not related, I will send the question in a separate email.

Quoted 8 lines

Quoted 6 lines
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
https://patchwork.ozlabs.org/project/openbmc/patch/[email protected]/
Quoted 2 lines
There is no such tag.
Do you understand this?

Sure, will use changelog or b4 dependencies next version

Quoted 5 lines

Quoted 3 lines
Quoted 3 lines
Use changelog for this purpose or b4 dependencies.
Do you understand this?

yes

Quoted 4 lines

Best regards,
Krzysztof

Thanks,

Tomer

Tomer Maimon

author maintainer

2025-07-17 13:53 UTC #6 lore raw

PATCH 2/2 arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

In reply to Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access.
This patch enhances functionality for NPCM845-EVB platform.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
 1 file changed, 445 insertions(+)

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +445 -0

index 2638ee1c3846..46d5bd1c2129 100644
@@ -10,6 +10,42 @@ / {
 
 	aliases {
 		serial0 = &serial0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		ethernet3 = &gmac3;
+		mdio-gpio0 = &mdio0;
+		mdio-gpio1 = &mdio1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
+		fiu3 = &fiu1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		i2c16 = &i2c16;
+		i2c17 = &i2c17;
+		i2c18 = &i2c18;
+		i2c19 = &i2c19;
+		i2c20 = &i2c20;
+		i2c21 = &i2c21;
+		i2c22 = &i2c22;
+		i2c23 = &i2c23;
+		i2c24 = &i2c24;
+		i2c25 = &i2c25;
+		i2c26 = &i2c26;
 	};
 
 	chosen {

@@ -25,12 +61,421 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;
+		};
+	};
+
+	mdio0: mdio@0 {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+			<&gpio1 26 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+		};
+	};
+
+	mdio1: mdio@1 {
+		compatible = "virtual,mdio-gpio";
+		gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
+			<&gpio2 28 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy1: ethernet-phy@1 {
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	snps,eee-force-disable;
+	status = "okay";
+};
+
+&gmac2 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r1_pins
+			&r1oen_pins>;
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&gmac3 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r2_pins
+			&r2oen_pins>;
+	phy-handle = <&phy1>;
+	status = "okay";
 };
 
 &serial0 {
 	status = "okay";
 };
 
+&fiu0 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@80000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bbuboot1@0 {
+				label = "bb-uboot-1";
+				reg = <0x0000000 0x80000>;
+				read-only;
+				};
+			bbuboot2@80000 {
+				label = "bb-uboot-2";
+				reg = <0x0080000 0x80000>;
+				read-only;
+				};
+			envparam@100000 {
+				label = "env-param";
+				reg = <0x0100000 0x40000>;
+				read-only;
+				};
+			spare@140000 {
+				label = "spare";
+				reg = <0x0140000 0xC0000>;
+				};
+			kernel@200000 {
+				label = "kernel";
+				reg = <0x0200000 0x400000>;
+				};
+			rootfs@600000 {
+				label = "rootfs";
+				reg = <0x0600000 0x700000>;
+				};
+			spare1@D00000 {
+				label = "spare1";
+				reg = <0x0D00000 0x200000>;
+				};
+			spare2@F00000 {
+				label = "spare2";
+				reg = <0x0F00000 0x200000>;
+				};
+			spare3@1100000 {
+				label = "spare3";
+				reg = <0x1100000 0x200000>;
+				};
+			spare4@1300000 {
+				label = "spare4";
+				reg = <0x1300000 0x0>;
+			};
+		};
+	};
+};
+
+&fiu1 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@A0000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi1-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiu3 {
+	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions@A0000000 {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi3-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiux {
+	spix-mode;
+};
+
+&sdhci {
+	status = "okay";
+};
+
+&udc0 {
+	status = "okay";
+};
+
+&udc1 {
+	status = "okay";
+};
+
+&udc2 {
+	status = "okay";
+};
+
+&udc3 {
+	status = "okay";
+};
+
+&udc4 {
+	status = "okay";
+};
+
+&udc5 {
+	status = "okay";
+};
+
+&udc6 {
+	status = "okay";
+};
+
+&udc7 {
+	status = "okay";
+};
+
+&mc {
+	status = "okay";
+};
+
+&peci {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc {
+	#io-channel-cells = <1>;
+	status = "okay";
+};
+
 &watchdog1 {
 	status = "okay";
 };
+
+&pwm_fan {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins &pwm1_pins
+		&pwm2_pins &pwm3_pins
+		&pwm4_pins &pwm5_pins
+		&pwm6_pins &pwm7_pins
+		&fanin0_pins &fanin1_pins
+		&fanin2_pins &fanin3_pins
+		&fanin4_pins &fanin5_pins
+		&fanin6_pins &fanin7_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fan@0 {
+		reg = <0x00>;
+		fan-tach-ch = /bits/ 8 <0x00 0x01>;
+		cooling-levels = <127 255>;
+	};
+	fan@1 {
+		reg = <0x01>;
+		fan-tach-ch = /bits/ 8 <0x02 0x03>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@2 {
+		reg = <0x02>;
+		fan-tach-ch = /bits/ 8 <0x04 0x05>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@3 {
+		reg = <0x03>;
+		fan-tach-ch = /bits/ 8 <0x06 0x07>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@4 {
+		reg = <0x04>;
+		fan-tach-ch = /bits/ 8 <0x08 0x09>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@5 {
+		reg = <0x05>;
+		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@6 {
+		reg = <0x06>;
+		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@7 {
+		reg = <0x07>;
+		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+};
+
+&pspi {
+	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	Flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		spi-max-frequency = <1000000>;
+		partition@0 {
+			label = "spi1_spare0";
+			reg = <0x0 0x0>;
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	tmp100@48 {
+		compatible = "tmp100";
+		reg = <0x48>;
+		status = "okay";
+	};
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&i2c16 {
+	status = "okay";
+};
+
+&i2c17 {
+	status = "okay";
+};
+
+&i2c18 {
+	status = "okay";
+};
+
+&i2c19 {
+	status = "okay";
+};
+
+&i2c20 {
+	status = "okay";
+};
+
+&i2c21 {
+	status = "okay";
+};
+
+&i2c22 {
+	status = "okay";
+};
+
+&i2c23 {
+	status = "okay";
+};
+
+&i2c24 {
+	status = "okay";
+};
+
+&i2c25 {
+	status = "okay";
+};
+
+&i2c26 {
+	status = "okay";
+};

Signature · 1 line

2.34.1

Krzysztof Kozlowski

2025-07-17 14:25 UTC #7 lore raw

Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Quoted 66 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access.
This patch enhances functionality for NPCM845-EVB platform.
Signed-off-by Tomer Maimon <[email protected]>
---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
 1 file changed, 445 insertions(+)
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +38 -0
index 2638ee1c3846..46d5bd1c2129 100644
@@ -10,6 +10,42 @@ / {
 
 	aliases {
 		serial0 = &serial0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		ethernet3 = &gmac3;
+		mdio-gpio0 = &mdio0;
+		mdio-gpio1 = &mdio1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
+		fiu3 = &fiu1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		i2c16 = &i2c16;
+		i2c17 = &i2c17;
+		i2c18 = &i2c18;
+		i2c19 = &i2c19;
+		i2c20 = &i2c20;
+		i2c21 = &i2c21;
+		i2c22 = &i2c22;
+		i2c23 = &i2c23;
+		i2c24 = &i2c24;
+		i2c25 = &i2c25;
+		i2c26 = &i2c26;
 	};
 
 	chosen {
@@ -25,12 +61,421 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 75

Quoted 10 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0

+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;
+		};
+	};
+
+	mdio0: mdio@0 {

Huh... this should fail checks. It's not MMIO node, is it?

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 76

Quoted 1 line

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +1 -0
+		compatible = "virtual,mdio-gpio";

where is the reg?

Please confirm that you introduced no new dtbs_check W=1 warnings.

Quoted 9 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +9 -0

+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+			<&gpio1 26 GPIO_ACTIVE_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@1 {
+		};
+	};
+

...

Quoted 10 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0

+		reg = <0x05>;
+		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@6 {
+		reg = <0x06>;
+		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+	fan@7 {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 349

Quoted 10 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0

+		reg = <0x07>;
+		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
+		cooling-levels = /bits/ 8 <127 255>;
+	};
+};
+
+&pspi {
+	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	Flash@0 {

DTS coding style, naming...

Best regards,
Krzysztof

Tomer Maimon

author maintainer

2025-07-28 12:13 UTC #8 lore raw

Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Hi Krzysztof,

Quoted 72 lines · Krzysztof Kozlowski

Quoted 70 lines · Tomer Maimon

Signed-off-by Tomer Maimon <[email protected]>

---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 445 ++++++++++++++++++
 1 file changed, 445 insertions(+)

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +42 -0

index 2638ee1c3846..46d5bd1c2129 100644
@@ -10,6 +10,42 @@ / {
 
      aliases {
              serial0 = &serial0;
+             ethernet1 = &gmac1;
+             ethernet2 = &gmac2;
+             ethernet3 = &gmac3;
+             mdio-gpio0 = &mdio0;
+             mdio-gpio1 = &mdio1;
+             fiu0 = &fiu0;
+             fiu1 = &fiu3;
+             fiu2 = &fiux;
+             fiu3 = &fiu1;
+             i2c0 = &i2c0;
+             i2c1 = &i2c1;
+             i2c2 = &i2c2;
+             i2c3 = &i2c3;
+             i2c4 = &i2c4;
+             i2c5 = &i2c5;
+             i2c6 = &i2c6;
+             i2c7 = &i2c7;
+             i2c8 = &i2c8;
+             i2c9 = &i2c9;
+             i2c10 = &i2c10;
+             i2c11 = &i2c11;
+             i2c12 = &i2c12;
+             i2c13 = &i2c13;
+             i2c14 = &i2c14;
+             i2c15 = &i2c15;
+             i2c16 = &i2c16;
+             i2c17 = &i2c17;
+             i2c18 = &i2c18;
+             i2c19 = &i2c19;
+             i2c20 = &i2c20;
+             i2c21 = &i2c21;
+             i2c22 = &i2c22;
+             i2c23 = &i2c23;
+             i2c24 = &i2c24;
+             i2c25 = &i2c25;
+             i2c26 = &i2c26;
      };
 
      chosen {

@@ -25,12 +61,421 @@ refclk: refclk-25mhz {
              clock-frequency = <25000000>;
              #clock-cells = <0>;
      };
+
+     reserved-memory {
+             #address-cells = <2>;
+             #size-cells = <2>;
+             ranges;
+

Quoted 8 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 75
Quoted 6 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +6 -0
+             tip_reserved: tip@0 {
+                     reg = <0x0 0x0 0x0 0x6200000>;
+             };
+     };
+
+     mdio0: mdio@0 {
Huh... this should fail checks. It's not MMIO node, is it?

No, it's MDIO node,
https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
Should I modify the node name? If yes, which node name should I use?

Quoted 5 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 76
Quoted 3 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +1 -0
+             compatible = "virtual,mdio-gpio";
where is the reg?

It does not include reg in the mother node, but only in the child.

Quoted 40 lines

Please confirm that you introduced no new dtbs_check W=1 warnings.
Quoted 9 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +9 -0
+             gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+                     <&gpio1 26 GPIO_ACTIVE_HIGH>;
+             #address-cells = <1>;
+             #size-cells = <0>;
+
+             phy0: ethernet-phy@1 {
+             };
+     };
+
...
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arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0
+             reg = <0x05>;
+             fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
+             cooling-levels = /bits/ 8 <127 255>;
+     };
+     fan@6 {
+             reg = <0x06>;
+             fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
+             cooling-levels = /bits/ 8 <127 255>;
+     };
+     fan@7 {
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 349
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arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0
+             reg = <0x07>;
+             fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
+             cooling-levels = /bits/ 8 <127 255>;
+     };
+};
+
+&pspi {
+     cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+     status = "okay";
+     Flash@0 {
DTS coding style, naming...

Quoted 2 lines

Best regards,
Krzysztof

Thanks,

Tomer

Krzysztof Kozlowski

2025-07-29 06:21 UTC #9 lore raw

Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Quoted 9 lines · Tomer Maimon

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Review
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(quoted diff) +2 -0
+
+     mdio0: mdio@0 {
Huh... this should fail checks. It's not MMIO node, is it?
No, it's MDIO node,
https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
Should I modify the node name? If yes, which node name should I use?
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+ compatible = "virtual,mdio-gpio";
where is the reg?
It does not include reg in the mother node, but only in the child.

You put the unit address...

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Please confirm that you introduced no new dtbs_check W=1 warnings.

I need you to answer this.

Best regards,
Krzysztof

Tomer Maimon

author maintainer

2025-07-29 13:16 UTC #10 lore raw

Re: [PATCH v1 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Hi Krzysztof

Quoted 11 lines · Krzysztof Kozlowski

Quoted 9 lines · Tomer Maimon
Quoted 4 lines
Review
Quoted 2 lines
(quoted diff) +2 -0
+
+     mdio0: mdio@0 {
Huh... this should fail checks. It's not MMIO node, is it?
No, it's MDIO node,
https://elixir.bootlin.com/linux/v6.16-rc7/source/Documentation/devicetree/bindings/net/mdio-gpio.yaml#L48
Should I modify the node name? If yes, which node name should I use?
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+ compatible = "virtual,mdio-gpio";
where is the reg?
It does not include reg in the mother node, but only in the child.
You put the unit address...

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Please confirm that you introduced no new dtbs_check W=1 warnings.
I need you to answer this.

I didn't run dtbs_check with W=1 and the mdio-gpio document. I will make sure to run dtbs_check W=1 before submitting the next version

Quoted 5 lines

Best regards,
Krzysztof

Best regards,

Tomer