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Common csr_read_num() and csr_write_num() for RISC-V

PATCH Superseded Anup Patel 8 participants 15 messages Aug 18, 2025 – Sep 17, 2025

Subsystems (5)
ACPI RISC-V Arm PMU profiling and debugging RISC-V PMU drivers +1 more subsystems

v2 of 4 Superseded 1 of 2 applied Latest is v4 →

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Anup Patel

author
#0 lore raw

v2 cover Common csr_read_num() and csr_write_num() for RISC-V

Some of the RISC-V drivers (such as RISC-V PMU and ACPI CPPC) need to access CSR based on CSR number discovered from somewhere. Add common RISC-V csr_read_num() and csr_write_num() functions under arch/riscv for such drivers.

These patches can be found in the riscv_csr_read_num_v2 branch at:
https://github.com/avpatel/linux.git

Changes since v1:
- Make "out_err" mandatory for csr_read_num() and csr_write_num() in PATCH2 as suggested by Sunil and Drew. This also helps further simplify csr_read_num() and csr_write_num().

Anup Patel (2):
ACPI: RISC-V: Fix FFH_CPPC_CSR error handling
RISC-V: Add common csr_read_num() and csr_write_num() functions

 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  21 ++---
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 186 insertions(+), 58 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
Signature · 1 line
2.43.0
author
#1 lore raw

PATCH v2 1/2 ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
---
 drivers/acpi/riscv/cppc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/acpi/riscv/cppc.c +2 -2
index 440cf9fb91aa..42c1a9052470 100644
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
 		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;

@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
 		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
Signature · 1 line
2.43.0
maintainer Reviewed-by on v2 1/2
#2 lore raw

Re: [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

Quoted 26 lines · Anup Patel

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
---
  drivers/acpi/riscv/cppc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
drivers/acpi/riscv/cppc.c +1 -1
index 440cf9fb91aa..42c1a9052470 100644
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
  		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;

drivers/acpi/riscv/cppc.c int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val) · line 154

Quoted 8 lines
drivers/acpi/riscv/cppc.c +1 -1
@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
  		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;
Reviewed-by Atish Patra <[email protected]>
Reviewed-by on v2 1/2
#3 lore raw

Re: [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

In reply to Anup Patel
Quoted 11 lines · Anup Patel

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
---
  drivers/acpi/riscv/cppc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by Nutty Liu <[email protected]>

Thanks,
Nutty

Quoted 22 lines
drivers/acpi/riscv/cppc.c +2 -2
index 440cf9fb91aa..42c1a9052470 100644
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
  		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;

@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
  		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;
maintainer Reviewed-by on v2 1/2
#4 lore raw

Re: [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

In reply to Anup Patel
Quoted 37 lines · Anup Patel

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
---
 drivers/acpi/riscv/cppc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/acpi/riscv/cppc.c +2 -2
index 440cf9fb91aa..42c1a9052470 100644
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
 		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;

@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
 		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
 	}
 
 	return -EINVAL;
Signature · 1 line
2.43.0
Reviewed-by Sunil V L <[email protected]>
reviewer
#5 lore raw

Re: [PATCH v2 1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

In reply to Anup Patel

Hi Anup,

Quoted 26 lines · Anup Patel

The cppc_ffh_csr_read() and cppc_ffh_csr_write() returns Linux error code in "data->ret.error" so cpc_read_ffh() and cpc_write_ffh() must not use sbi_err_map_linux_errno() for FFH_CPPC_CSR.

Fixes 30f3ffbee86b ("ACPI: RISC-V: Add CPPC driver")
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Andrew Jones <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
---
  drivers/acpi/riscv/cppc.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
drivers/acpi/riscv/cppc.c +1 -1
index 440cf9fb91aa..42c1a9052470 100644
@@ -119,7 +119,7 @@ int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val)
 
  		*val = data.ret.value;
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;

drivers/acpi/riscv/cppc.c int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val) · line 154

Quoted 8 lines
drivers/acpi/riscv/cppc.c +1 -1
@@ -148,7 +148,7 @@ int cpc_write_ffh(int cpu, struct cpc_reg *reg, u64 val)
 
  		smp_call_function_single(cpu, cppc_ffh_csr_write, &data, 1);
 
-		return (data.ret.error) ? sbi_err_map_linux_errno(data.ret.error) : 0;
+		return data.ret.error;
  	}
 
  	return -EINVAL;

I picked this up for fixes, cc stable and I'll send this patch for some 6.17-rcX.

Thanks,

Alex

_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv

author
#6 lore raw

PATCH v2 2/2 RISC-V: Add common csr_read_num() and csr_write_num() functions

In reply to Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
arch/riscv/include/asm/csr.h +3 -0
index 6fed42e37705..1540626b3540 100644
@@ -575,6 +575,9 @@
 			      : "memory");			\
 })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_CSR_H */
arch/riscv/kernel/Makefile +1 -0
index c7b542573407..0a75e20bde18 100644
@@ -50,6 +50,7 @@ obj-y	+= soc.o
 obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o
 obj-y	+= cpu.o
 obj-y	+= cpufeature.o
+obj-y	+= csr.o
 obj-y	+= entry.o
 obj-y	+= irq.o
 obj-y	+= process.o
arch/riscv/kernel/csr.c new file +165 -0

165 lines not on this page · raw message

drivers/acpi/riscv/cppc.c +6 -11
index 42c1a9052470..fe491937ed25 100644
@@ -65,24 +65,19 @@ static void sbi_cppc_write(void *write_data)
 static void cppc_ffh_csr_read(void *read_data)
 {
 	struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+	int err;
 
-	switch (data->reg) {
-	/* Support only TIME CSR for now */
-	case CSR_TIME:
-		data->ret.value = csr_read(CSR_TIME);
-		data->ret.error = 0;
-		break;
-	default:
-		data->ret.error = -EINVAL;
-		break;
-	}
+	data->ret.value = csr_read_num(data->reg, &err);
+	data->ret.error = err;
 }
 
 static void cppc_ffh_csr_write(void *write_data)
 {
 	struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+	int err;
 
-	data->ret.error = -EINVAL;
+	csr_write_num(data->reg, data->val, &err);
+	data->ret.error = err;
 }
 
 /*
drivers/perf/riscv_pmu.c +9 -45

73 lines not on this page · raw message

Signature · 1 line
2.43.0
Reviewed-by on v2 2/2
#7 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

Quoted 8 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
Quoted 9 lines
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
Reviewed-by Andrew Jones <[email protected]>
maintainer Reviewed-by on v2 2/2
#8 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

In reply to Anup Patel
Quoted 5 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Thanks for the cleanup. Are you planning to align the csr.h in tools so that userpsace tools can use leverage it as well ?

tools/arch/riscv/include/asm/csr.h

Quoted 310 lines
Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
  arch/riscv/include/asm/csr.h |   3 +
  arch/riscv/kernel/Makefile   |   1 +
  arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
  drivers/acpi/riscv/cppc.c    |  17 ++--
  drivers/perf/riscv_pmu.c     |  54 ++----------
  5 files changed, 184 insertions(+), 56 deletions(-)

create mode 100644 arch/riscv/kernel/csr.c

arch/riscv/include/asm/csr.h +3 -0
index 6fed42e37705..1540626b3540 100644
@@ -575,6 +575,9 @@
  			      : "memory");			\
  })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);
+
  #endif /* __ASSEMBLY__ */
 
  #endif /* _ASM_RISCV_CSR_H */
arch/riscv/kernel/Makefile +1 -0
index c7b542573407..0a75e20bde18 100644
@@ -50,6 +50,7 @@ obj-y	+= soc.o
  obj-$(CONFIG_RISCV_ALTERNATIVE) += alternative.o
  obj-y	+= cpu.o
  obj-y	+= cpufeature.o
+obj-y	+= csr.o
  obj-y	+= entry.o
  obj-y	+= irq.o
  obj-y	+= process.o
arch/riscv/kernel/csr.c new file +165 -0
new file mode 100644
index 000000000000..e96b129c1a99
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Ventana Micro Systems Inc.
+ */
+
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/types.h>
+#include <asm/csr.h>
+
+#define CSR_CUSTOM0_U_RW_BASE		0x800
+#define CSR_CUSTOM0_U_RW_COUNT		0x100
+
+#define CSR_CUSTOM1_U_RO_BASE		0xCC0
+#define CSR_CUSTOM1_U_RO_COUNT		0x040
+
+#define CSR_CUSTOM2_S_RW_BASE		0x5C0
+#define CSR_CUSTOM2_S_RW_COUNT		0x040
+
+#define CSR_CUSTOM3_S_RW_BASE		0x9C0
+#define CSR_CUSTOM3_S_RW_COUNT		0x040
+
+#define CSR_CUSTOM4_S_RO_BASE		0xDC0
+#define CSR_CUSTOM4_S_RO_COUNT		0x040
+
+#define CSR_CUSTOM5_HS_RW_BASE		0x6C0
+#define CSR_CUSTOM5_HS_RW_COUNT		0x040
+
+#define CSR_CUSTOM6_HS_RW_BASE		0xAC0
+#define CSR_CUSTOM6_HS_RW_COUNT		0x040
+
+#define CSR_CUSTOM7_HS_RO_BASE		0xEC0
+#define CSR_CUSTOM7_HS_RO_COUNT		0x040
+
+#define CSR_CUSTOM8_M_RW_BASE		0x7C0
+#define CSR_CUSTOM8_M_RW_COUNT		0x040
+
+#define CSR_CUSTOM9_M_RW_BASE		0xBC0
+#define CSR_CUSTOM9_M_RW_COUNT		0x040
+
+#define CSR_CUSTOM10_M_RO_BASE		0xFC0
+#define CSR_CUSTOM10_M_RO_COUNT		0x040
+
+unsigned long csr_read_num(unsigned long csr_num, int *out_err)
+{
+#define switchcase_csr_read(__csr_num)				\
+	case (__csr_num):					\
+		return csr_read(__csr_num)
+#define switchcase_csr_read_2(__csr_num)			\
+	switchcase_csr_read(__csr_num + 0);			\
+	switchcase_csr_read(__csr_num + 1)
+#define switchcase_csr_read_4(__csr_num)			\
+	switchcase_csr_read_2(__csr_num + 0);			\
+	switchcase_csr_read_2(__csr_num + 2)
+#define switchcase_csr_read_8(__csr_num)			\
+	switchcase_csr_read_4(__csr_num + 0);			\
+	switchcase_csr_read_4(__csr_num + 4)
+#define switchcase_csr_read_16(__csr_num)			\
+	switchcase_csr_read_8(__csr_num + 0);			\
+	switchcase_csr_read_8(__csr_num + 8)
+#define switchcase_csr_read_32(__csr_num)			\
+	switchcase_csr_read_16(__csr_num + 0);			\
+	switchcase_csr_read_16(__csr_num + 16)
+#define switchcase_csr_read_64(__csr_num)			\
+	switchcase_csr_read_32(__csr_num + 0);			\
+	switchcase_csr_read_32(__csr_num + 32)
+#define switchcase_csr_read_128(__csr_num)			\
+	switchcase_csr_read_64(__csr_num + 0);			\
+	switchcase_csr_read_64(__csr_num + 64)
+#define switchcase_csr_read_256(__csr_num)			\
+	switchcase_csr_read_128(__csr_num + 0);			\
+	switchcase_csr_read_128(__csr_num + 128)
+
+	*out_err = 0;
+	switch (csr_num) {
+	switchcase_csr_read_32(CSR_CYCLE);
+	switchcase_csr_read_32(CSR_CYCLEH);
+	switchcase_csr_read_256(CSR_CUSTOM0_U_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM1_U_RO_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM2_S_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM3_S_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM4_S_RO_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM5_HS_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM6_HS_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM7_HS_RO_BASE);
+#ifdef CONFIG_RISCV_M_MODE
+	switchcase_csr_read_64(CSR_CUSTOM8_M_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM9_M_RW_BASE);
+	switchcase_csr_read_64(CSR_CUSTOM10_M_RO_BASE);
+#endif
+	default:
+		*out_err = -EINVAL;
+		break;
+	}
+
+	return 0;
+#undef switchcase_csr_read_256
+#undef switchcase_csr_read_128
+#undef switchcase_csr_read_64
+#undef switchcase_csr_read_32
+#undef switchcase_csr_read_16
+#undef switchcase_csr_read_8
+#undef switchcase_csr_read_4
+#undef switchcase_csr_read_2
+#undef switchcase_csr_read
+}
+EXPORT_SYMBOL_GPL(csr_read_num);
+
+void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err)
+{
+#define switchcase_csr_write(__csr_num, __val)			\
+	case (__csr_num):					\
+		csr_write(__csr_num, __val);			\
+		break
+#define switchcase_csr_write_2(__csr_num, __val)		\
+	switchcase_csr_write(__csr_num + 0, __val);		\
+	switchcase_csr_write(__csr_num + 1, __val)
+#define switchcase_csr_write_4(__csr_num, __val)		\
+	switchcase_csr_write_2(__csr_num + 0, __val);		\
+	switchcase_csr_write_2(__csr_num + 2, __val)
+#define switchcase_csr_write_8(__csr_num, __val)		\
+	switchcase_csr_write_4(__csr_num + 0, __val);		\
+	switchcase_csr_write_4(__csr_num + 4, __val)
+#define switchcase_csr_write_16(__csr_num, __val)		\
+	switchcase_csr_write_8(__csr_num + 0, __val);		\
+	switchcase_csr_write_8(__csr_num + 8, __val)
+#define switchcase_csr_write_32(__csr_num, __val)		\
+	switchcase_csr_write_16(__csr_num + 0, __val);		\
+	switchcase_csr_write_16(__csr_num + 16, __val)
+#define switchcase_csr_write_64(__csr_num, __val)		\
+	switchcase_csr_write_32(__csr_num + 0, __val);		\
+	switchcase_csr_write_32(__csr_num + 32, __val)
+#define switchcase_csr_write_128(__csr_num, __val)		\
+	switchcase_csr_write_64(__csr_num + 0, __val);		\
+	switchcase_csr_write_64(__csr_num + 64, __val)
+#define switchcase_csr_write_256(__csr_num, __val)		\
+	switchcase_csr_write_128(__csr_num + 0, __val);		\
+	switchcase_csr_write_128(__csr_num + 128, __val)
+
+	*out_err = 0;
+	switch (csr_num) {
+	switchcase_csr_write_256(CSR_CUSTOM0_U_RW_BASE, val);
+	switchcase_csr_write_64(CSR_CUSTOM2_S_RW_BASE, val);
+	switchcase_csr_write_64(CSR_CUSTOM3_S_RW_BASE, val);
+	switchcase_csr_write_64(CSR_CUSTOM5_HS_RW_BASE, val);
+	switchcase_csr_write_64(CSR_CUSTOM6_HS_RW_BASE, val);
+#ifdef CONFIG_RISCV_M_MODE
+	switchcase_csr_write_64(CSR_CUSTOM8_M_RW_BASE, val);
+	switchcase_csr_write_64(CSR_CUSTOM9_M_RW_BASE, val);
+#endif
+	default:
+		*out_err = -EINVAL;
+		break;
+	}
+#undef switchcase_csr_write_256
+#undef switchcase_csr_write_128
+#undef switchcase_csr_write_64
+#undef switchcase_csr_write_32
+#undef switchcase_csr_write_16
+#undef switchcase_csr_write_8
+#undef switchcase_csr_write_4
+#undef switchcase_csr_write_2
+#undef switchcase_csr_write
+}
+EXPORT_SYMBOL_GPL(csr_write_num);
drivers/acpi/riscv/cppc.c +6 -11
index 42c1a9052470..fe491937ed25 100644
@@ -65,24 +65,19 @@ static void sbi_cppc_write(void *write_data)
  static void cppc_ffh_csr_read(void *read_data)
  {
  	struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+	int err;
 
-	switch (data->reg) {
-	/* Support only TIME CSR for now */
-	case CSR_TIME:
-		data->ret.value = csr_read(CSR_TIME);
-		data->ret.error = 0;
-		break;
-	default:
-		data->ret.error = -EINVAL;
-		break;
-	}
+	data->ret.value = csr_read_num(data->reg, &err);
+	data->ret.error = err;
  }
 
  static void cppc_ffh_csr_write(void *write_data)
  {
  	struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+	int err;
 
-	data->ret.error = -EINVAL;
+	csr_write_num(data->reg, data->val, &err);
+	data->ret.error = err;
  }
 
  /*
drivers/perf/riscv_pmu.c +3 -44
index 7644147d50b4..b41f353ba964 100644
@@ -16,6 +16,7 @@
  #include <linux/smp.h>
  #include <linux/sched_clock.h>
 
+#include <asm/csr.h>
  #include <asm/sbi.h>
 
  static bool riscv_perf_user_access(struct perf_event *event)

@@ -88,58 +89,21 @@ void arch_perf_update_userpage(struct perf_event *event,
  	userpg->cap_user_time_short = 1;
  }
 
-static unsigned long csr_read_num(int csr_num)
-{
-#define switchcase_csr_read(__csr_num, __val)		{\
-	case __csr_num:					\
-		__val = csr_read(__csr_num);		\
-		break; }
-#define switchcase_csr_read_2(__csr_num, __val)		{\
-	switchcase_csr_read(__csr_num + 0, __val)	 \
-	switchcase_csr_read(__csr_num + 1, __val)}
-#define switchcase_csr_read_4(__csr_num, __val)		{\
-	switchcase_csr_read_2(__csr_num + 0, __val)	 \
-	switchcase_csr_read_2(__csr_num + 2, __val)}
-#define switchcase_csr_read_8(__csr_num, __val)		{\
-	switchcase_csr_read_4(__csr_num + 0, __val)	 \
-	switchcase_csr_read_4(__csr_num + 4, __val)}
-#define switchcase_csr_read_16(__csr_num, __val)	{\
-	switchcase_csr_read_8(__csr_num + 0, __val)	 \
-	switchcase_csr_read_8(__csr_num + 8, __val)}
-#define switchcase_csr_read_32(__csr_num, __val)	{\
-	switchcase_csr_read_16(__csr_num + 0, __val)	 \
-	switchcase_csr_read_16(__csr_num + 16, __val)}
-
-	unsigned long ret = 0;
-
-	switch (csr_num) {
-	switchcase_csr_read_32(CSR_CYCLE, ret)
-	switchcase_csr_read_32(CSR_CYCLEH, ret)
-	default :
-		break;
-	}
-
-	return ret;
-#undef switchcase_csr_read_32
-#undef switchcase_csr_read_16
-#undef switchcase_csr_read_8
-#undef switchcase_csr_read_4
-#undef switchcase_csr_read_2
-#undef switchcase_csr_read
-}
-
  /*
   * Read the CSR of a corresponding counter.
   */
  unsigned long riscv_pmu_ctr_read_csr(unsigned long csr)
  {
-	if (csr < CSR_CYCLE || csr > CSR_HPMCOUNTER31H ||
-	   (csr > CSR_HPMCOUNTER31 && csr < CSR_CYCLEH)) {
-		pr_err("Invalid performance counter csr %lx\n", csr);
-		return -EINVAL;
+	unsigned long val;
+	int rc;

drivers/perf/riscv_pmu.c void arch_perf_update_userpage(struct perf_event *event, · line 107

Quoted 10 lines
drivers/perf/riscv_pmu.c +6 -1
+
+	val = csr_read_num(csr, &rc);
+	if (rc) {
+		pr_err("Failed to read performance counter csr %lx (error %d)\n", csr, rc);
+		return rc;
  	}
 
-	return csr_read_num(csr);
+	return val;
  }

Otherwise, lgtm.

Reviewed-by Atish Patra <[email protected]>
Quoted 2 lines
drivers/perf/riscv_pmu.c +0 -0
  u64 riscv_pmu_ctr_get_width_mask(struct perf_event *event)
#9 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

In reply to Anup Patel
Quoted 22 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
arch/riscv/include/asm/csr.h +0 -0
index 6fed42e37705..1540626b3540 100644

arch/riscv/include/asm/csr.h line 579

Quoted 5 lines
arch/riscv/include/asm/csr.h +2 -0
@@ -575,6 +575,9 @@
 			      : "memory");			\
 })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);

I think it's more consistent to directly return the error code, and for csr_read_num, we could pass out the read value by a pointer. e.g.

	int csr_read_num(unsigned long csr_num, unsigned long *val);
	int csr_write_num(unsigned long csr_num, unsigned long val);

This allows the caller to eliminate a variable for temporarily storing the error code if they use it just after the invokation, and fits the common convention of Linux better.

Quoted 4 lines
arch/riscv/include/asm/csr.h +1 -0
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_RISCV_CSR_H */

...

Quoted 23 lines
drivers/acpi/riscv/cppc.c +3 -10
index 42c1a9052470..fe491937ed25 100644
@@ -65,24 +65,19 @@ static void sbi_cppc_write(void *write_data)
 static void cppc_ffh_csr_read(void *read_data)
 {
 	struct sbi_cppc_data *data = (struct sbi_cppc_data *)read_data;
+	int err;
 
-	switch (data->reg) {
-	/* Support only TIME CSR for now */
-	case CSR_TIME:
-		data->ret.value = csr_read(CSR_TIME);
-		data->ret.error = 0;
-		break;
-	default:
-		data->ret.error = -EINVAL;
-		break;
-	}
+	data->ret.value = csr_read_num(data->reg, &err);
+	data->ret.error = err;
 }

drivers/acpi/riscv/cppc.c static void sbi_cppc_write(void *write_data) · line 81

Quoted 10 lines
drivers/acpi/riscv/cppc.c +3 -1
 
 static void cppc_ffh_csr_write(void *write_data)
 {
 	struct sbi_cppc_data *data = (struct sbi_cppc_data *)write_data;
+	int err;
 
-	data->ret.error = -EINVAL;
+	csr_write_num(data->reg, data->val, &err);
+	data->ret.error = err;
 }

This could be simplified as

	data->ret.error = csr_write_num(data->reg, data->val);

and variable err could be dropped.

Best regards,
Yao Zi

author
#10 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

Quoted 33 lines · Yao Zi
Quoted 22 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
arch/riscv/include/asm/csr.h +0 -0
index 6fed42e37705..1540626b3540 100644

arch/riscv/include/asm/csr.h line 579

Quoted 5 lines
arch/riscv/include/asm/csr.h +2 -0
@@ -575,6 +575,9 @@
                            : "memory");                      \
 })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);

I think it's more consistent to directly return the error code, and for csr_read_num, we could pass out the read value by a pointer. e.g.

Quoted 6 lines
        int csr_read_num(unsigned long csr_num, unsigned long *val);
        int csr_write_num(unsigned long csr_num, unsigned long val);

This allows the caller to eliminate a variable for temporarily storing the error code if they use it just after the invokation, and fits the common convention of Linux better.

Drew had similar comments so see my response in the previous patch revision. (Refer, https://www.spinics.net/lists/kernel/msg5808113.html)

Regards,
Anup

#11 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

Quoted 37 lines · Anup Patel
Quoted 36 lines · Yao Zi
Quoted 22 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
arch/riscv/include/asm/csr.h +0 -0
index 6fed42e37705..1540626b3540 100644

arch/riscv/include/asm/csr.h line 579

Quoted 5 lines
arch/riscv/include/asm/csr.h +2 -0
@@ -575,6 +575,9 @@
                            : "memory");                      \
 })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);

I think it's more consistent to directly return the error code, and for csr_read_num, we could pass out the read value by a pointer. e.g.

        int csr_read_num(unsigned long csr_num, unsigned long *val);
        int csr_write_num(unsigned long csr_num, unsigned long val);
Quoted 6 lines
Quoted 3 lines

This allows the caller to eliminate a variable for temporarily storing the error code if they use it just after the invokation, and fits the common convention of Linux better.

Drew had similar comments so see my response in the previous patch revision. (Refer, https://www.spinics.net/lists/kernel/msg5808113.html)

Thanks for the reference.

Quoted 4 lines

I had considered this but the problem with this approach is that individual switch cases in csr_read_num() become roughly 4 instructions because value read from CSR has to written to a memory location.

You could return a structure smaller than or equal to 2 * XLEN from csr_read_num(), according to the ABI it could be passed in a0 and a1 and thus should require no memory operation.

Let's assume we have

	struct __csr_read_ret {
		long error;
		unsigned long value;
	};

	struct __csr_read_ret __csr_read_num(unsigned long csr_num);

Then a wrapper like

	/* piece of untested code */
	static inline int csr_read_num(unsigned long csr_num,
				       unsigned long *val)
	{
		struct __csr_read_ret ret = __csr_read_num(csr_num);
		*val = ret.value;
		return ret.error;
	}

could provide an interface that I've talked about earlier, and it follows the kernel's convention.

Quoted 4 lines

The current approach results in just 2 instructions for each switch-case. Additionally, the current prototypes of csr_read_num() and csr_write_num() are closer to csr_read() and csr_write() respectively.

But csr_read() and csr_write() never directly raise errors that is expected to be handled by the caller. I don't think it's a fair comparison.

Quoted 2 lines

Regards,
Anup

Best regards,
Yao Zi

author
#12 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

Quoted 77 lines · Yao Zi
Quoted 37 lines · Anup Patel
Quoted 36 lines · Yao Zi
Quoted 22 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
---
 arch/riscv/include/asm/csr.h |   3 +
 arch/riscv/kernel/Makefile   |   1 +
 arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
 drivers/acpi/riscv/cppc.c    |  17 ++--
 drivers/perf/riscv_pmu.c     |  54 ++----------
 5 files changed, 184 insertions(+), 56 deletions(-)
 create mode 100644 arch/riscv/kernel/csr.c
arch/riscv/include/asm/csr.h +0 -0
index 6fed42e37705..1540626b3540 100644

arch/riscv/include/asm/csr.h line 579

Quoted 5 lines
arch/riscv/include/asm/csr.h +2 -0
@@ -575,6 +575,9 @@
                            : "memory");                      \
 })
 
+extern unsigned long csr_read_num(unsigned long csr_num, int *out_err);
+extern void csr_write_num(unsigned long csr_num, unsigned long val, int *out_err);

I think it's more consistent to directly return the error code, and for csr_read_num, we could pass out the read value by a pointer. e.g.

        int csr_read_num(unsigned long csr_num, unsigned long *val);
        int csr_write_num(unsigned long csr_num, unsigned long val);
Quoted 6 lines
Quoted 3 lines

This allows the caller to eliminate a variable for temporarily storing the error code if they use it just after the invokation, and fits the common convention of Linux better.

Drew had similar comments so see my response in the previous patch revision. (Refer, https://www.spinics.net/lists/kernel/msg5808113.html)

Thanks for the reference.

Quoted 4 lines

I had considered this but the problem with this approach is that individual switch cases in csr_read_num() become roughly 4 instructions because value read from CSR has to written to a memory location.

You could return a structure smaller than or equal to 2 * XLEN from csr_read_num(), according to the ABI it could be passed in a0 and a1 and thus should require no memory operation.

Let's assume we have

        struct __csr_read_ret {
                long error;
                unsigned long value;
        };

        struct __csr_read_ret __csr_read_num(unsigned long csr_num);

Then a wrapper like

        /* piece of untested code */
        static inline int csr_read_num(unsigned long csr_num,
                                       unsigned long *val)
        {
                struct __csr_read_ret ret = __csr_read_num(csr_num);
                *val = ret.value;
                return ret.error;
        }
Quoted 2 lines

could provide an interface that I've talked about earlier, and it follows the kernel's convention.

Like I mentioned previously, the current implementation tries to minimize instructions for each switch case and avoid unnecessary memory load/store. Your alternate suggestion is no better in this respect.

Quoted 9 lines
Quoted 5 lines

The current approach results in just 2 instructions for each switch-case. Additionally, the current prototypes of csr_read_num() and csr_write_num() are closer to csr_read() and csr_write() respectively.

But csr_read() and csr_write() never directly raise errors that is expected to be handled by the caller. I don't think it's a fair comparison.

csr_read_num() and csr_write_num() are different because these functions take CSR number as parameter so caller can pass an unsupported value to these functions which needs to be reported back as an error.

Regards,
Anup

Reviewed-by on v2 2/2
#13 lore raw

Re: [PATCH v2 2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions

In reply to Anup Patel
Quoted 8 lines · Anup Patel

In RISC-V, there is no CSR read/write instruction which takes CSR number via register so add common csr_read_num() and csr_write_num() functions which allow accessing certain CSRs by passing CSR number as parameter. These common functions will be first used by the ACPI CPPC driver and RISC-V PMU driver.

Signed-off-by Anup Patel <[email protected]>
Reviewed-by Sunil V L <[email protected]>
Quoted 8 lines
---
  arch/riscv/include/asm/csr.h |   3 +
  arch/riscv/kernel/Makefile   |   1 +
  arch/riscv/kernel/csr.c      | 165 +++++++++++++++++++++++++++++++++++
  drivers/acpi/riscv/cppc.c    |  17 ++--
  drivers/perf/riscv_pmu.c     |  54 ++----------
  5 files changed, 184 insertions(+), 56 deletions(-)

create mode 100644 arch/riscv/kernel/csr.c

Reviewed-by Nutty Liu <[email protected]>

Thanks,
Nutty

CI
#14 lore raw
In reply to Anup Patel
This series was applied to riscv/linux.git (for-next) by Paul Walmsley <[email protected]>:

Hello:

This series was applied to riscv/linux.git (for-next) by Paul Walmsley <[email protected]>:

Quoted 9 lines · On Mon, 18 Aug 2025 20:05:58 +0530 you wrote:

Some of the RISC-V drivers (such as RISC-V PMU and ACPI CPPC) need to access CSR based on CSR number discovered from somewhere. Add common RISC-V csr_read_num() and csr_write_num() functions under arch/riscv for such drivers.

These patches can be found in the riscv_csr_read_num_v2 branch at:
https://github.com/avpatel/linux.git

[...]

Here is the summary with links:
- [v2,1/2] ACPI: RISC-V: Fix FFH_CPPC_CSR error handling

    https://git.kernel.org/riscv/c/5b3706597b90

- [v2,2/2] RISC-V: Add common csr_read_num() and csr_write_num() functions (no matching commit)

You are awesome, thank you!

Signature · 2 lines
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