nouveau: fix disabling the nonstall irq due to storm code. (v2)
Subsystems (3)
Dave Airlie
maintainerPATCH 1/2 nouveau: fix disabling the nonstall irq due to storm code. (v2)
From: Dave Airlie <[email protected]>
Nouveau has code that when it gets an IRQ with no allowed handler it disables it to avoid storms.
However with nonstall interrupts, we often disable them from the drm driver, but still request their emission via the push submission.
Just don't disable nonstall irqs ever in normal operation, the event handling code will filter them out, and the driver will just enable/disable them at load time.
This fixes timeouts we've been seeing on/off for a long time, but they became a lot more noticable on Blackwell.
This doesn't fix all of them, there is a subsequent fence emission fix to fix the last few.
---
v2: add missing ga102.
--- .../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 2 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/ga100.c | 22 ++++++++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/ga102.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ .../nouveau/nvkm/subdev/gsp/rm/r535/fifo.c | 2 +- 5 files changed, 20 insertions(+), 9 deletions(-)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +2 -0
@@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)nvkm_chid_unref (&fifo->chid);nvkm_event_fini (&fifo->nonstall.event); +if (fifo->func->nonstall_dtor) + fifo->func->nonstall_dtor (fifo);mutex_destroy (&fifo->mutex);if (fifo->func->dtor)
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c +14 -8
@@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)static void ga100_fifo_nonstall_block (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_block (&runl->nonstall.inth); }static void ga100_fifo_nonstall_allow (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_allow (&runl->nonstall.inth); } const struct nvkm_event_func
@@ -564,12 +556,25 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)if (ret)return ret; +nvkm_inth_allow (&runl->nonstall.inth); + nr =max (nr, runl->id +1 ); }return nr; } +void +ga100_fifo_nonstall_dtor (struct nvkm_fifo *fifo) +{ +struct nvkm_runl *runl; + nvkm_runl_foreach(runl, fifo) { +if (runl->nonstall.vector <0 ) +continue ; +nvkm_inth_block (&runl->nonstall.inth); + } +} +int ga100_fifo_runl_ctor (struct nvkm_fifo *fifo) {
@@ -599,6 +604,7 @@ ga100_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c +1 -0
@@ -30,6 +30,7 @@ ga102_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +2 -0
@@ -41,6 +41,7 @@ struct nvkm_fifo_func {void (*start)(struct nvkm_fifo *,unsigned long *);int (*nonstall_ctor)(struct nvkm_fifo *); +void (*nonstall_dtor)(struct nvkm_fifo *);const struct nvkm_event_func *nonstall;const struct nvkm_runl_func *runl;
@@ -200,6 +201,7 @@ u32 tu102_chan_doorbell_handle(struct nvkm_chan *);int ga100_fifo_runl_ctor (struct nvkm_fifo *);int ga100_fifo_nonstall_ctor (struct nvkm_fifo *); +void ga100_fifo_nonstall_dtor (struct nvkm_fifo *);extern const struct nvkm_event_func ga100_fifo_nonstall;extern const struct nvkm_runl_func ga100_runl;extern const struct nvkm_runq_func ga100_runq;
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c +1 -1
@@ -601,7 +601,7 @@ r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device, rm->chan.func = &r535_chan; rm->nonstall = &ga100_fifo_nonstall; rm->nonstall_ctor = ga100_fifo_nonstall_ctor; - + rm->nonstall_dtor = ga100_fifo_nonstall_dtor;return nvkm_fifo_new_ (rm, device, type, inst, pfifo); }
Signature · 1 line
2.50.1
Dave Airlie
maintainerPATCH 2/2 nouveau: Membar before between semaphore writes and the interrupt
From: Faith Ekstrand <[email protected]>
This ensures that the memory write and the interrupt are properly ordered and we won't wake up the kernel before the semaphore write has hit memory.
--- drivers/gpu/drm/nouveau/gv100_fence.c | 7 +- .../drm/nouveau/include/nvhw/class/clc36f.h | 85 +++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-)
drivers/gpu/drm/nouveau/gv100_fence.c +6 -1
@@ -18,7 +18,7 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)struct nvif_push *push = &chan->chan.push;int ret; - ret =PUSH_WAIT (push,8 ); + ret =PUSH_WAIT (push,13 );if (ret)return ret;
@@ -32,6 +32,11 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS)); +PUSH_MTHD (push,NVC36F ,MEM_OP_A ,0 , +MEM_OP_B ,0 , +MEM_OP_C ,NVDEF (NVC36F ,MEM_OP_C ,MEMBAR_TYPE ,SYS_MEMBAR ), +MEM_OP_D ,NVDEF (NVC36F ,MEM_OP_D ,OPERATION ,MEMBAR )); +PUSH_MTHD (push,NVC36F ,NON_STALL_INTERRUPT ,0 );PUSH_KICK (push);
drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h +85 -0
91 lines not on this page · raw message
Signature · 1 line
2.50.1
Re: [PATCH 2/2] nouveau: Membar before between semaphore writes and the interrupt
Quoted 10 lines · Dave Airlie
From: Faith Ekstrand <[email protected]>
This ensures that the memory write and the interrupt are properly ordered and we won't wake up the kernel before the semaphore write has hit memory.
Fixes b1ca384772b6 ("drm/nouveau/gv100-: switch to volta semaphore methods")Signed-off-by Faith Ekstrand <[email protected]>Signed-off-by Dave Airlie <[email protected]>
Applied to drm-misc-fixes, thanks!
Re: [PATCH 2/2] nouveau: Membar before between semaphore writes and the interrupt
In reply to Dave AirlieFor posterity: This surprised me, so I asked our architecture team whether it makes sense. They confirmed the additional sysmembar is required for correct ordering between the interrupt handler's CPU read and the host semaphore release's memory write.
Thanks,
-James
Quoted 136 lines · Dave Airlie
From: Faith Ekstrand <[email protected]>
This ensures that the memory write and the interrupt are properly ordered and we won't wake up the kernel before the semaphore write has hit memory.
Fixes b1ca384772b6 ("drm/nouveau/gv100-: switch to volta semaphore methods")Signed-off-by Faith Ekstrand <[email protected]>Signed-off-by Dave Airlie <[email protected]>--- drivers/gpu/drm/nouveau/gv100_fence.c | 7 +- .../drm/nouveau/include/nvhw/class/clc36f.h | 85 +++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-)drivers/gpu/drm/nouveau/gv100_fence.c +6
-1@@ -18,7 +18,7 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)struct nvif_push *push = &chan->chan.push;int ret; - ret =PUSH_WAIT (push,8 ); + ret =PUSH_WAIT (push,13 );if (ret)return ret;@@ -32,6 +32,11 @@ gv100_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) NVDEF(NVC36F, SEM_EXECUTE, PAYLOAD_SIZE, 32BIT) | NVDEF(NVC36F, SEM_EXECUTE, RELEASE_TIMESTAMP, DIS)); +PUSH_MTHD (push,NVC36F ,MEM_OP_A ,0 , +MEM_OP_B ,0 , +MEM_OP_C ,NVDEF (NVC36F ,MEM_OP_C ,MEMBAR_TYPE ,SYS_MEMBAR ), +MEM_OP_D ,NVDEF (NVC36F ,MEM_OP_D ,OPERATION ,MEMBAR )); +PUSH_MTHD (push,NVC36F ,NON_STALL_INTERRUPT ,0 );PUSH_KICK (push);drivers/gpu/drm/nouveau/include/nvhw/class/clc36f.h +85
-0@@ -7,6 +7,91 @@#define NVC36F_NON_STALL_INTERRUPT (0x00000020)#define NVC36F_NON_STALL_INTERRUPT_HANDLE 31:0 +// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for +// specifying the page address for a targeted TLB invalidate and the uTLB for +// a targeted REPLAY_CANCEL for UVM. +// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly +// rearranged fields. +#define NVC36F_MEM_OP_A (0x00000028) +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 +#define NVC36F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 +#define NVC36F_MEM_OP_B (0x0000002c) +#define NVC36F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 +#define NVC36F_MEM_OP_C (0x00000030) +#define NVC36F_MEM_OP_C_MEMBAR_TYPE 2:0 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 +#define NVC36F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 +#define NVC36F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 +// MEM_OP_D MUST be preceded by MEM_OPs A-C. +#define NVC36F_MEM_OP_D (0x00000034) +#define NVC36F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE +#define NVC36F_MEM_OP_D_OPERATION 31:27 +#define NVC36F_MEM_OP_D_OPERATION_MEMBAR 0x00000005 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 +#define NVC36F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a +#define NVC36F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d +#define NVC36F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e +// CLEAN_LINES is an alias for Tegra/GPU IP usage +#define NVC36F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e +#define NVC36F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f +#define NVC36F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 +#define NVC36F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 +#define NVC36F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 +#define NVC36F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3#define NVC36F_SEM_ADDR_LO (0x0000005c)#define NVC36F_SEM_ADDR_LO_OFFSET 31:2#define NVC36F_SEM_ADDR_HI (0x00000060)
Quoted 16 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Nouveau has code that when it gets an IRQ with no allowed handler it disables it to avoid storms.
However with nonstall interrupts, we often disable them from the drm driver, but still request their emission via the push submission.
Just don't disable nonstall irqs ever in normal operation, the event handling code will filter them out, and the driver will just enable/disable them at load time.
This fixes timeouts we've been seeing on/off for a long time, but they became a lot more noticable on Blackwell.
Quoted 6 lines
This doesn't fix all of them, there is a subsequent fence emission fix to fix the last few.
Fixes 3ebd64aa3c4f ("drm/nouveau/intr: support multiple trees, and explicit interfaces")Signed-off-by Dave Airlie <[email protected]>
I don't 100% grok all the storm stuff but this certainly looks reasonable and I'm convinced it shouldn't break anything
Reviewed-by Faith Ekstrand <[email protected]>
Quoted 130 lines
---
v2: add missing ga102.--- .../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 2 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/ga100.c | 22 ++++++++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/ga102.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ .../nouveau/nvkm/subdev/gsp/rm/r535/fifo.c | 2 +- 5 files changed, 20 insertions(+), 9 deletions(-)drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +2
-0@@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)nvkm_chid_unref (&fifo->chid);nvkm_event_fini (&fifo->nonstall.event); +if (fifo->func->nonstall_dtor) + fifo->func->nonstall_dtor (fifo);mutex_destroy (&fifo->mutex);if (fifo->func->dtor)drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c +14
-8@@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)static void ga100_fifo_nonstall_block (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_block (&runl->nonstall.inth); }static void ga100_fifo_nonstall_allow (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_allow (&runl->nonstall.inth); } const struct nvkm_event_func@@ -564,12 +556,25 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)if (ret)return ret; +nvkm_inth_allow (&runl->nonstall.inth); + nr =max (nr, runl->id +1 ); }return nr; } +void +ga100_fifo_nonstall_dtor (struct nvkm_fifo *fifo) +{ +struct nvkm_runl *runl; + nvkm_runl_foreach(runl, fifo) { +if (runl->nonstall.vector <0 ) +continue ; +nvkm_inth_block (&runl->nonstall.inth); + } +} +int ga100_fifo_runl_ctor (struct nvkm_fifo *fifo) {@@ -599,6 +604,7 @@ ga100_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c +1
-0@@ -30,6 +30,7 @@ ga102_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +2
-0@@ -41,6 +41,7 @@ struct nvkm_fifo_func {void (*start)(struct nvkm_fifo *,unsigned long *);int (*nonstall_ctor)(struct nvkm_fifo *); +void (*nonstall_dtor)(struct nvkm_fifo *);const struct nvkm_event_func *nonstall;const struct nvkm_runl_func *runl;@@ -200,6 +201,7 @@ u32 tu102_chan_doorbell_handle(struct nvkm_chan *);int ga100_fifo_runl_ctor (struct nvkm_fifo *);int ga100_fifo_nonstall_ctor (struct nvkm_fifo *); +void ga100_fifo_nonstall_dtor (struct nvkm_fifo *);extern const struct nvkm_event_func ga100_fifo_nonstall;extern const struct nvkm_runl_func ga100_runl;extern const struct nvkm_runq_func ga100_runq;drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c +1
-2@@ -601,7 +601,7 @@ r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device, rm->chan.func = &r535_chan; rm->nonstall = &ga100_fifo_nonstall; rm->nonstall_ctor = ga100_fifo_nonstall_ctor; - + rm->nonstall_dtor = ga100_fifo_nonstall_dtor;return nvkm_fifo_new_ (rm, device, type, inst, pfifo); } --2.50.1
Quoted 15 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Nouveau has code that when it gets an IRQ with no allowed handler it disables it to avoid storms.
However with nonstall interrupts, we often disable them from the drm driver, but still request their emission via the push submission.
Just don't disable nonstall irqs ever in normal operation, the event handling code will filter them out, and the driver will just enable/disable them at load time.
This fixes timeouts we've been seeing on/off for a long time, but they became a lot more noticable on Blackwell.
Quoted 6 lines
This doesn't fix all of them, there is a subsequent fence emission fix to fix the last few.
Fixes 3ebd64aa3c4f ("drm/nouveau/intr: support multiple trees, and explicit interfaces")Signed-off-by Dave Airlie <[email protected]>
Applied to drm-misc-fixes, thanks!
[ Fix a typo and a minor checkpatch.pl warning; remove "v2" from commit
subject. - Danilo ]
Quoted 150 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Nouveau has code that when it gets an IRQ with no allowed handler it disables it to avoid storms.
However with nonstall interrupts, we often disable them from the drm driver, but still request their emission via the push submission.
Just don't disable nonstall irqs ever in normal operation, the event handling code will filter them out, and the driver will just enable/disable them at load time.
This fixes timeouts we've been seeing on/off for a long time, but they became a lot more noticable on Blackwell.
This doesn't fix all of them, there is a subsequent fence emission fix to fix the last few.
Fixes 3ebd64aa3c4f ("drm/nouveau/intr: support multiple trees, and explicit interfaces")Signed-off-by Dave Airlie <[email protected]>---
v2: add missing ga102.--- .../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 2 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/ga100.c | 22 ++++++++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/ga102.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ .../nouveau/nvkm/subdev/gsp/rm/r535/fifo.c | 2 +- 5 files changed, 20 insertions(+), 9 deletions(-)drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +2
-0@@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)nvkm_chid_unref (&fifo->chid);nvkm_event_fini (&fifo->nonstall.event); +if (fifo->func->nonstall_dtor) + fifo->func->nonstall_dtor (fifo);mutex_destroy (&fifo->mutex);if (fifo->func->dtor)drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c +14
-8@@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)static void ga100_fifo_nonstall_block (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_block (&runl->nonstall.inth); }static void ga100_fifo_nonstall_allow (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_allow (&runl->nonstall.inth); } const struct nvkm_event_func@@ -564,12 +556,25 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)if (ret)return ret; +nvkm_inth_allow (&runl->nonstall.inth); + nr =max (nr, runl->id +1 ); }return nr; } +void +ga100_fifo_nonstall_dtor (struct nvkm_fifo *fifo) +{ +struct nvkm_runl *runl; + nvkm_runl_foreach(runl, fifo) { +if (runl->nonstall.vector <0 ) +continue ; +nvkm_inth_block (&runl->nonstall.inth); + } +} +int ga100_fifo_runl_ctor (struct nvkm_fifo *fifo) {@@ -599,6 +604,7 @@ ga100_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c +1
-0@@ -30,6 +30,7 @@ ga102_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +2
-0@@ -41,6 +41,7 @@ struct nvkm_fifo_func {void (*start)(struct nvkm_fifo *,unsigned long *);int (*nonstall_ctor)(struct nvkm_fifo *); +void (*nonstall_dtor)(struct nvkm_fifo *);const struct nvkm_event_func *nonstall;const struct nvkm_runl_func *runl;@@ -200,6 +201,7 @@ u32 tu102_chan_doorbell_handle(struct nvkm_chan *);int ga100_fifo_runl_ctor (struct nvkm_fifo *);int ga100_fifo_nonstall_ctor (struct nvkm_fifo *); +void ga100_fifo_nonstall_dtor (struct nvkm_fifo *);extern const struct nvkm_event_func ga100_fifo_nonstall;extern const struct nvkm_runl_func ga100_runl;extern const struct nvkm_runq_func ga100_runq;drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c +1
-2@@ -601,7 +601,7 @@ r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device, rm->chan.func = &r535_chan; rm->nonstall = &ga100_fifo_nonstall; rm->nonstall_ctor = ga100_fifo_nonstall_ctor; - + rm->nonstall_dtor = ga100_fifo_nonstall_dtor;return nvkm_fifo_new_ (rm, device, type, inst, pfifo); } --
Quoted 2 lines
2.50.1
Maybe we should also do this for older GPUs? eg. perhaps we should also update gf100_fifo_nonstall_allow / gf100_fifo_nonstall_block ?
Dave Airlie
maintainerQuoted 151 lines · M Henning
Quoted 149 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Nouveau has code that when it gets an IRQ with no allowed handler it disables it to avoid storms.
However with nonstall interrupts, we often disable them from the drm driver, but still request their emission via the push submission.
Just don't disable nonstall irqs ever in normal operation, the event handling code will filter them out, and the driver will just enable/disable them at load time.
This fixes timeouts we've been seeing on/off for a long time, but they became a lot more noticable on Blackwell.
This doesn't fix all of them, there is a subsequent fence emission fix to fix the last few.
Fixes 3ebd64aa3c4f ("drm/nouveau/intr: support multiple trees, and explicit interfaces")Signed-off-by Dave Airlie <[email protected]>---
v2: add missing ga102.--- .../gpu/drm/nouveau/nvkm/engine/fifo/base.c | 2 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/ga100.c | 22 ++++++++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/ga102.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 ++ .../nouveau/nvkm/subdev/gsp/rm/r535/fifo.c | 2 +- 5 files changed, 20 insertions(+), 9 deletions(-)drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +2
-0@@ -350,6 +350,8 @@ nvkm_fifo_dtor(struct nvkm_engine *engine)nvkm_chid_unref (&fifo->chid);nvkm_event_fini (&fifo->nonstall.event); +if (fifo->func->nonstall_dtor) + fifo->func->nonstall_dtor (fifo);mutex_destroy (&fifo->mutex);if (fifo->func->dtor)drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.c +14
-8@@ -517,19 +517,11 @@ ga100_fifo_nonstall_intr(struct nvkm_inth *inth)static void ga100_fifo_nonstall_block (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_block (&runl->nonstall.inth); }static void ga100_fifo_nonstall_allow (struct nvkm_event *event,int type,int index) { -struct nvkm_fifo *fifo =container_of (event,typeof (*fifo), nonstall.event); -struct nvkm_runl *runl =nvkm_runl_get (fifo, index,0 ); - -nvkm_inth_allow (&runl->nonstall.inth); } const struct nvkm_event_func@@ -564,12 +556,25 @@ ga100_fifo_nonstall_ctor(struct nvkm_fifo *fifo)if (ret)return ret; +nvkm_inth_allow (&runl->nonstall.inth); + nr =max (nr, runl->id +1 ); }return nr; } +void +ga100_fifo_nonstall_dtor (struct nvkm_fifo *fifo) +{ +struct nvkm_runl *runl; + nvkm_runl_foreach(runl, fifo) { +if (runl->nonstall.vector <0 ) +continue ; +nvkm_inth_block (&runl->nonstall.inth); + } +} +int ga100_fifo_runl_ctor (struct nvkm_fifo *fifo) {@@ -599,6 +604,7 @@ ga100_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.c +1
-0@@ -30,6 +30,7 @@ ga102_fifo = { .runl_ctor = ga100_fifo_runl_ctor, .mmu_fault = &tu102_fifo_mmu_fault, .nonstall_ctor = ga100_fifo_nonstall_ctor, + .nonstall_dtor = ga100_fifo_nonstall_dtor, .nonstall = &ga100_fifo_nonstall, .runl = &ga100_runl, .runq = &ga100_runq,drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +2
-0@@ -41,6 +41,7 @@ struct nvkm_fifo_func {void (*start)(struct nvkm_fifo *,unsigned long *);int (*nonstall_ctor)(struct nvkm_fifo *); +void (*nonstall_dtor)(struct nvkm_fifo *);const struct nvkm_event_func *nonstall;const struct nvkm_runl_func *runl;@@ -200,6 +201,7 @@ u32 tu102_chan_doorbell_handle(struct nvkm_chan *);int ga100_fifo_runl_ctor (struct nvkm_fifo *);int ga100_fifo_nonstall_ctor (struct nvkm_fifo *); +void ga100_fifo_nonstall_dtor (struct nvkm_fifo *);extern const struct nvkm_event_func ga100_fifo_nonstall;extern const struct nvkm_runl_func ga100_runl;extern const struct nvkm_runq_func ga100_runq;drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c +1
-1@@ -601,7 +601,7 @@ r535_fifo_new(const struct nvkm_fifo_func *hw, struct nvkm_device *device, rm->chan.func = &r535_chan; rm->nonstall = &ga100_fifo_nonstall; rm->nonstall_ctor = ga100_fifo_nonstall_ctor; - + rm->nonstall_dtor = ga100_fifo_nonstall_dtor;return nvkm_fifo_new_ (rm, device, type, inst, pfifo); }
Quoted 6 lines
Quoted 3 lines
--
2.50.1Maybe we should also do this for older GPUs? eg. perhaps we should also update
gf100_fifo_nonstall_allow/gf100_fifo_nonstall_block?
Those actually turn off the irq at the hardware, and therefore shouldn't hit the allowed path check, not touching that without someone showing it's broken.
Dave.
Quoted 10 lines · Dave Airlie
Quoted 2 lines · M Henning
Maybe we should also do this for older GPUs? eg. perhaps we should also update
gf100_fifo_nonstall_allow/gf100_fifo_nonstall_block?Those actually turn off the irq at the hardware, and therefore shouldn't hit the allowed path check, not touching that without someone showing it's broken.
Dave.
I did some testing on kepler and it looks like it is broken. I can reproduce the Talos + transfer queue issue there easily. I wrote
https://gitlab.freedesktop.org/mhenning/linux/-/commit/b3ef72898ae2bf19cf587b8679d193c9570ddb05
to fix the membar half of the issue but that still doesn't load Talos with a transfer queue, which means that we either need to apply this fix (nouveau: fix disabling the nonstall irq due to storm code) for kepler and probably all the other gens, or there's yet another bug lurking somewhere.