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arm64: dts: nuvoton: Add NPCM845 SoC and EVB support

PATCH Superseded Tomer Maimon 2 participants 8 messages Sep 8, 2025 – Sep 22, 2025

Subsystems (2)
Device tree bindings Arm/nuvoton npcm architecture

v2 of 10 Superseded Latest is v10 →

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Tomer Maimon

author maintainer
#0 lore raw

v2 cover arm64: dts: nuvoton: Add NPCM845 SoC and EVB support

This series adds device tree support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation Board (EVB).
The first patch introduces peripheral nodes for Ethernet, MMC, SPI, USB, RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device tree. The second patch enables these peripherals for the NPCM845-EVB, adding MDIO nodes, reserved memory, aliases, and board-specific configurations like PHY modes and SPI flash partitions.

The NPCM8XX device tree tested on NPCM845 evaluation board.

Addressed comments from:

	- Krzysztof Kozlowski: https://lkml.indiana.edu/2507.3/05464.html
						   https://lkml.indiana.edu/2507.3/05465.html

Changes since version 1:
- Fix commit message
- Fix dtbs_check warnings.

Tomer Maimon (2):
arm64: dts: nuvoton: npcm845: Add peripheral nodes
arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702 +++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 439 +++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 3 files changed, 1147 insertions(+), 1 deletion(-)
Signature · 1 line
2.34.1
author maintainer
#1 lore raw

PATCH v2 1/2 arm64: dts: nuvoton: npcm845: Add peripheral nodes

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702 +++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 2 files changed, 708 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +701 -1
index 24133528b8e9..7f120da3310a 100644
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <2>;

@@ -32,9 +33,19 @@ gic: interrupt-controller@dfff9000 {
 			#interrupt-cells = <3>;
 			interrupt-controller;
 			#address-cells = <0>;
+			ppi-partitions {
+				ppi_cluster0: interrupt-partition-0 {
+					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+				};
+			};
 		};
 	};
 
+	udc0_phy: usb-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
 	ahb {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -51,7 +62,260 @@ clk: rstc: reset-controller@f0801000 {
 			#clock-cells = <1>;
 		};
 
-		apb {
+		gmac1: ethernet@f0804000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0804000 0x0 0x2000>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg2_pins
+					&rg2mdio_pins>;
+			status = "disabled";
+		};
+
+		gmac2: ethernet@f0806000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0806000 0x0 0x2000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r1_pins
+					&r1err_pins
+					&r1md_pins>;
+			status = "disabled";
+		};
+
+		gmac3: ethernet@f0808000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0808000 0x0 0x2000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r2_pins
+					&r2err_pins
+					&r2md_pins>;
+			status = "disabled";
+		};
+
+		sdhci: mmc@f0842000 {
+			compatible = "nuvoton,npcm845-sdhci";
+			reg = <0x0 0xf0842000 0x0 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "clk_mmc";
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc8_pins
+				     &mmc_pins>;
+			status = "disabled";
+		};
+
+		fiu0: spi@fb000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI0>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
+		fiu1: spi@fb002000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb002000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI1>;
+			clock-names = "clk_spi1";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
+			status = "disabled";
+		};
+
+		fiu3: spi@c0000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xc0000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI3>;
+			clock-names = "clk_spi3";
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi3_pins>;
+			status = "disabled";
+		};
+
+		fiux: spi@fb001000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb001000 0x0 0x1000>,
+			<0x0 0xf8000000 0x0 0x2000000>;
+			reg-names = "control", "memory";
+			clocks =  <&clk NPCM8XX_CLK_SPIX>;
+			clock-names = "clk_ahb";
+			status = "disabled";
+		};
+
+		mc: memory-controller@f0824000 {
+			compatible = "nuvoton,npcm845-memory-controller";
+			reg = <0x0 0xf0824000 0x0 0x1000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		udc0: usb@f0830000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0830000 0x0 0x1000
+			       0x0 0xfffeb000 0x0 0x800>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc1: usb@f0831000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0831000 0x0 0x1000
+			       0x0 0xfffeb800 0x0 0x800>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc2: usb@f0832000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0832000 0x0 0x1000
+			       0x0 0xfffec000 0x0 0x800>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc3: usb@f0833000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0833000 0x0 0x1000
+			       0x0 0xfffec800 0x0 0x800>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc4: usb@f0834000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0834000 0x0 0x1000
+			       0x0 0xfffed000 0x0 0x800>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc5: usb@f0835000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0835000 0x0 0x1000
+			       0x0 0xfffed800 0x0 0x800>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc6: usb@f0836000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0836000 0x0 0x1000
+			       0x0 0xfffee000 0x0 0x800>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc7: usb@f0837000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0837000 0x0 0x1000
+			       0x0 0xfffee800 0x0 0x800>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc8: usb@f0838000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0838000 0x0 0x1000
+			       0x0 0xfffef000 0x0 0x800>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc9: usb@f0839000 {
+			compatible = "nuvoton,npcm845-udc";
+			reg = <0x0 0xf0839000 0x0 0x1000
+			       0x0 0xfffef800 0x0 0x800>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		apb: bus@f0000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";

@@ -59,6 +323,20 @@ apb {
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
 
+			pspi: spi@201000 {
+				compatible = "nuvoton,npcm845-pspi";
+				reg = <0x201000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks =  <&clk NPCM8XX_CLK_APB5>;
+				clock-names = "clk_apb5";
+				resets = <&rstc 0x24 23>;
+				status = "disabled";
+			};
+
 			peci: peci-controller@100000 {
 				compatible = "nuvoton,npcm845-peci";
 				reg = <0x100000 0x1000>;

@@ -139,6 +417,22 @@ serial6: serial@6000 {
 				status = "disabled";
 			};
 
+			rng: rng@b000 {
+				compatible = "nuvoton,npcm845-rng";
+				reg = <0xb000 0x8>;
+				clocks =  <&clk NPCM8XX_CLK_APB1>;
+				status = "disabled";
+			};
+
+			adc: adc@c000 {
+				compatible = "nuvoton,npcm845-adc";
+				reg = <0xC000 0x8>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM8XX_CLK_ADC>;
+				resets = <&rstc 0x20 27>;
+				status = "disabled";
+			};
+
 			watchdog0: watchdog@801c {
 				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

@@ -165,6 +459,412 @@ watchdog2: watchdog@a01c {
 				clocks = <&refclk>;
 				syscon = <&gcr>;
 			};
+
+			pwm_fan:pwm-fan-controller@103000 {
+				compatible = "nuvoton,npcm845-pwm-fan";
+				reg = <0x103000 0x3000>,
+					<0x180000 0x8000>;
+				reg-names = "pwm", "fan";
+				clocks =  <&clk NPCM8XX_CLK_APB3>,
+					<&clk NPCM8XX_CLK_APB4>;
+				clock-names = "pwm","fan";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pwm0_pins &pwm1_pins
+						&pwm2_pins &pwm3_pins
+						&pwm4_pins &pwm5_pins
+						&pwm6_pins &pwm7_pins
+						&pwm8_pins &pwm9_pins
+						&pwm10_pins &pwm11_pins
+						&fanin0_pins &fanin1_pins
+						&fanin2_pins &fanin3_pins
+						&fanin4_pins &fanin5_pins
+						&fanin6_pins &fanin7_pins
+						&fanin8_pins &fanin9_pins
+						&fanin10_pins &fanin11_pins
+						&fanin12_pins &fanin13_pins
+						&fanin14_pins &fanin15_pins>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@80000 {
+				reg = <0x80000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb0_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@81000 {
+				reg = <0x81000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb1_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@82000 {
+				reg = <0x82000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb2_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@83000 {
+				reg = <0x83000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb3_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@84000 {
+				reg = <0x84000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb4_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@85000 {
+				reg = <0x85000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb5_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@86000 {
+				reg = <0x86000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb6_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@87000 {
+				reg = <0x87000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb7_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@88000 {
+				reg = <0x88000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb8_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@89000 {
+				reg = <0x89000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb9_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@8a000 {
+				reg = <0x8a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb10_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@8b000 {
+				reg = <0x8b000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb11_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@8c000 {
+				reg = <0x8c000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb12_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c13: i2c@8d000 {
+				reg = <0x8d000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb13_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c14: i2c@8e000 {
+				reg = <0x8e000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb14_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c15: i2c@8f000 {
+				reg = <0x8f000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb15_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c16: i2c@fff00000 {
+				reg = <0xfff00000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb16_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c17: i2c@fff01000 {
+				reg = <0xfff01000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb17_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c18: i2c@fff02000 {
+				reg = <0xfff02000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb18_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c19: i2c@fff03000 {
+				reg = <0xfff03000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb19_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c20: i2c@fff04000 {
+				reg = <0xfff04000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb20_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c21: i2c@fff05000 {
+				reg = <0xfff05000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb21_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c22: i2c@fff06000 {
+				reg = <0xfff06000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb22_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c23: i2c@fff07000 {
+				reg = <0xfff07000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb23_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c24: i2c@fff08000 {
+				reg = <0xfff08000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c25: i2c@fff09000 {
+				reg = <0xfff09000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c26: i2c@fff0a000 {
+				reg = <0xfff0a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
 		};
 	};
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +7 -0
index 383938dcd3ce..21dea323612d 100644
@@ -75,4 +75,11 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };
Signature · 1 line
2.34.1
maintainer
#2 lore raw

Re: [PATCH v2 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi Tomer,

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi

Quoted 16 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702 +++++++++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +

 2 files changed, 708 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
index 24133528b8e9..7f120da3310a 100644

*snip*

Quoted 27 lines

+               fiu1: spi@fb002000 {
+                       compatible = "nuvoton,npcm845-fiu"; +                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xfb002000 0x0 0x1000>; +                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI1>; +                       clock-names = "clk_spi1"; +                       pinctrl-names = "default"; +                       pinctrl-0 = <&spi1_pins>; +                       status = "disabled";
+               };

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +15 -0
+
+               fiu3: spi@c0000000 {
+                       compatible = "nuvoton,npcm845-fiu";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xc0000000 0x0 0x1000>;
+                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI3>;
+                       clock-names = "clk_spi3";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi3_pins>;
+                       status = "disabled";
+               };
+
+               fiux: spi@fb001000 {

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 168

Quoted 10 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +10 -0
+                       compatible = "nuvoton,npcm845-fiu";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xfb001000 0x0 0x1000>,
+                       <0x0 0xf8000000 0x0 0x2000000>;
+                       reg-names = "control", "memory";
+                       clocks =  <&clk NPCM8XX_CLK_SPIX>;
+                       clock-names = "clk_ahb";
+                       status = "disabled";
+               };

Can you please audit the patch (and the rest of the dtsi) to make sure all nodes are ordered by ascending unit address, as per the DTS style guide?

https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

Andrew

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 175

Quoted 7 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +7 -0
+
+               mc: memory-controller@f0824000 {
+                       compatible = "nuvoton,npcm845-memory-controller";
+                       reg = <0x0 0xf0824000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               };
+

*snip*

author maintainer
#3 lore raw

Re: [PATCH v2 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi Andrew,

Thanks for your comments.

Quoted 17 lines · Andrew Jeffery

Hi Tomer,

Quoted 13 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node for secure services.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702 +++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +
 2 files changed, 708 insertions(+), 1 deletion(-)
Quoted 31 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi

Quoted 3 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
index 24133528b8e9..7f120da3310a 100644

*snip*

Quoted 25 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +25 -0
+               fiu1: spi@fb002000 {
+                       compatible = "nuvoton,npcm845-fiu";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xfb002000 0x0 0x1000>;
+                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI1>;
+                       clock-names = "clk_spi1";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi1_pins>;
+                       status = "disabled";
+               };
+
+               fiu3: spi@c0000000 {
+                       compatible = "nuvoton,npcm845-fiu";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xc0000000 0x0 0x1000>;
+                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI3>;
+                       clock-names = "clk_spi3";
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&spi3_pins>;
+                       status = "disabled";
+               };

I don't need to move the FIU3 node as ordered by ascending unit address since the FIU3 node is a part of the FIU's group, am I correct?

Quoted 21 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 168

Quoted 12 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +12 -0
+
+               fiux: spi@fb001000 {
+                       compatible = "nuvoton,npcm845-fiu";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xfb001000 0x0 0x1000>,
+                       <0x0 0xf8000000 0x0 0x2000000>;
+                       reg-names = "control", "memory";
+                       clocks =  <&clk NPCM8XX_CLK_SPIX>;
+                       clock-names = "clk_ahb";
+                       status = "disabled";
+               };

Can you please audit the patch (and the rest of the dtsi) to make sure all nodes are ordered by ascending unit address, as per the DTS style guide?

https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

Andrew

Quoted 9 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 175

Quoted 7 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +7 -0
+
+               mc: memory-controller@f0824000 {
+                       compatible = "nuvoton,npcm845-memory-controller";
+                       reg = <0x0 0xf0824000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               };
+

*snip*

I see disorder in the upstream dtsi file, for example, PECI order. Do you suggest fixing it?

peci: peci-controller@100000 {
compatible = "nuvoton,npcm845-peci";
reg = <0x100000 0x1000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk NPCM8XX_CLK_APB3>;
cmd-timeout-ms = <1000>;
status = "disabled";
};

timer0: timer@8000 {
compatible = "nuvoton,npcm845-timer";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x8000 0x1C>;
clocks = <&clk NPCM8XX_CLK_REFCLK>;
clock-names = "refclk";
};

Thanks,

Tomer

maintainer
#4 lore raw

Re: [PATCH v2 1/2] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi Tomer,

Quoted 61 lines · Tomer Maimon

Hi Andrew,

Thanks for your comments.

Quoted 22 lines · Andrew Jeffery

Hi Tomer,

Quoted 18 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 SoC by adding device
nodes for Ethernet controllers, MMC controller, SPI controllers, USB
device controllers, random number generator, ADC, PWM-FAN controller,
and I2C controllers. Include pinmux configurations for relevant peripherals to support hardware operation. Add an OP-TEE firmware node
for secure services.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702
+++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +

 2 files changed, 708 insertions(+), 1 deletion(-)
Quoted 33 lines
Quoted 5 lines
(quoted diff) +0 -0

npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common- npcm8xx.dtsi
index 24133528b8e9..7f120da3310a 100644

*snip*

Quoted 25 lines

+               fiu1: spi@fb002000 {
+                       compatible = "nuvoton,npcm845-fiu"; +                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xfb002000 0x0 0x1000>; +                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI1>; +                       clock-names = "clk_spi1"; +                       pinctrl-names = "default"; +                       pinctrl-0 = <&spi1_pins>; +                       status = "disabled";
+               };
+
+               fiu3: spi@c0000000 {
+                       compatible = "nuvoton,npcm845-fiu"; +                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x0 0xc0000000 0x0 0x1000>; +                       reg-names = "control";
+                       clocks =  <&clk NPCM8XX_CLK_SPI3>; +                       clock-names = "clk_spi3"; +                       pinctrl-names = "default"; +                       pinctrl-0 = <&spi3_pins>; +                       status = "disabled";
+               };

Quoted 3 lines

I don't need to move the FIU3 node as ordered by ascending unit address since the FIU3 node is a part of the FIU's group, am I correct?

It's acceptable by the linked coding standard, but my preference is for the consistency of ordering by unit address.

Quoted 35 lines
Quoted 23 lines
Quoted 4 lines

+
+               fiux: spi@fb001000 {
+                       compatible = "nuvoton,npcm845-fiu"; +                       #address-cells = <1>;

Quoted 8 lines

+                       #size-cells = <0>;
+                       reg = <0x0 0xfb001000 0x0 0x1000>, +                       <0x0 0xf8000000 0x0 0x2000000>; +                       reg-names = "control", "memory"; +                       clocks =  <&clk NPCM8XX_CLK_SPIX>; +                       clock-names = "clk_ahb"; +                       status = "disabled";
+               };

Can you please audit the patch (and the rest of the dtsi) to make sure
all nodes are ordered by ascending unit address, as per the DTS style
guide?

https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

Andrew

Quoted 11 lines
Quoted 9 lines

+
+               mc: memory-controller@f0824000 {
+                       compatible = "nuvoton,npcm845-memory- controller";
+                       reg = <0x0 0xf0824000 0x0 0x1000>; +                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+               };
+

*snip*

Quoted 2 lines

I see disorder in the upstream dtsi file, for example, PECI order. Do you suggest fixing it?

If you don't mind, yes please (... as a separate patch) :)

Andrew

author maintainer
#5 lore raw

PATCH v2 2/2 arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

In reply to Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 439 ++++++++++++++++++
 1 file changed, 439 insertions(+)
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +439 -0
index 2638ee1c3846..145a2e599600 100644
@@ -10,6 +10,42 @@ / {
 
 	aliases {
 		serial0 = &serial0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		ethernet3 = &gmac3;
+		mdio-gpio0 = &mdio0;
+		mdio-gpio1 = &mdio1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
+		fiu3 = &fiu1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		i2c16 = &i2c16;
+		i2c17 = &i2c17;
+		i2c18 = &i2c18;
+		i2c19 = &i2c19;
+		i2c20 = &i2c20;
+		i2c21 = &i2c21;
+		i2c22 = &i2c22;
+		i2c23 = &i2c23;
+		i2c24 = &i2c24;
+		i2c25 = &i2c25;
+		i2c26 = &i2c26;
 	};
 
 	chosen {

@@ -25,12 +61,415 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;
+		};
+	};
+
+	mdio0: mdio-0 {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+			<&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+
+	mdio1: mdio-1 {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
+			<&gpio2 28 GPIO_ACTIVE_HIGH>;
+
+		phy1: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	snps,eee-force-disable;
+	status = "okay";
+};
+
+&gmac2 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r1_pins
+			&r1oen_pins>;
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&gmac3 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r2_pins
+			&r2oen_pins>;
+	phy-handle = <&phy1>;
+	status = "okay";
 };
 
 &serial0 {
 	status = "okay";
 };
 
+&fiu0 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bbuboot1@0 {
+				label = "bb-uboot-1";
+				reg = <0x0000000 0x80000>;
+				read-only;
+				};
+			bbuboot2@80000 {
+				label = "bb-uboot-2";
+				reg = <0x0080000 0x80000>;
+				read-only;
+				};
+			envparam@100000 {
+				label = "env-param";
+				reg = <0x0100000 0x40000>;
+				read-only;
+				};
+			spare@140000 {
+				label = "spare";
+				reg = <0x0140000 0xC0000>;
+				};
+			kernel@200000 {
+				label = "kernel";
+				reg = <0x0200000 0x400000>;
+				};
+			rootfs@600000 {
+				label = "rootfs";
+				reg = <0x0600000 0x700000>;
+				};
+			spare1@D00000 {
+				label = "spare1";
+				reg = <0x0D00000 0x200000>;
+				};
+			spare2@F00000 {
+				label = "spare2";
+				reg = <0x0F00000 0x200000>;
+				};
+			spare3@1100000 {
+				label = "spare3";
+				reg = <0x1100000 0x200000>;
+				};
+			spare4@1300000 {
+				label = "spare4";
+				reg = <0x1300000 0x0>;
+			};
+		};
+	};
+};
+
+&fiu1 {
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi1-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiu3 {
+	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+	status = "okay";
+	spi-nor@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			system1@0 {
+				label = "spi3-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiux {
+	spix-mode;
+};
+
+&sdhci {
+	status = "okay";
+};
+
+&udc0 {
+	status = "okay";
+};
+
+&udc1 {
+	status = "okay";
+};
+
+&udc2 {
+	status = "okay";
+};
+
+&udc3 {
+	status = "okay";
+};
+
+&udc4 {
+	status = "okay";
+};
+
+&udc5 {
+	status = "okay";
+};
+
+&udc6 {
+	status = "okay";
+};
+
+&udc7 {
+	status = "okay";
+};
+
+&mc {
+	status = "okay";
+};
+
+&peci {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc {
+	#io-channel-cells = <1>;
+	status = "okay";
+};
+
 &watchdog1 {
 	status = "okay";
 };
+
+&pwm_fan {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins &pwm1_pins
+		&pwm2_pins &pwm3_pins
+		&pwm4_pins &pwm5_pins
+		&pwm6_pins &pwm7_pins
+		&fanin0_pins &fanin1_pins
+		&fanin2_pins &fanin3_pins
+		&fanin4_pins &fanin5_pins
+		&fanin6_pins &fanin7_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fan@0 {
+		reg = <0x00>;
+		fan-tach-ch = /bits/ 8 <0x00 0x01>;
+		cooling-levels = <127 255>;
+	};
+	fan@1 {
+		reg = <0x01>;
+		fan-tach-ch = /bits/ 8 <0x02 0x03>;
+		cooling-levels = <127 255>;
+	};
+	fan@2 {
+		reg = <0x02>;
+		fan-tach-ch = /bits/ 8 <0x04 0x05>;
+		cooling-levels = <127 255>;
+	};
+	fan@3 {
+		reg = <0x03>;
+		fan-tach-ch = /bits/ 8 <0x06 0x07>;
+		cooling-levels = <127 255>;
+	};
+	fan@4 {
+		reg = <0x04>;
+		fan-tach-ch = /bits/ 8 <0x08 0x09>;
+		cooling-levels = <127 255>;
+	};
+	fan@5 {
+		reg = <0x05>;
+		fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
+		cooling-levels = <127 255>;
+	};
+	fan@6 {
+		reg = <0x06>;
+		fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
+		cooling-levels = <127 255>;
+	};
+	fan@7 {
+		reg = <0x07>;
+		fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
+		cooling-levels = <127 255>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	ipmb@10 {
+		compatible = "ipmb-dev";
+		reg = <0x10>;
+		i2c-protocol;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	ipmb@11 {
+		compatible = "ipmb-dev";
+		reg = <0x11>;
+		i2c-protocol;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	tmp100@48 {
+		compatible = "tmp100";
+		reg = <0x48>;
+		status = "okay";
+	};
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&i2c16 {
+	status = "okay";
+};
+
+&i2c17 {
+	status = "okay";
+};
+
+&i2c18 {
+	status = "okay";
+};
+
+&i2c19 {
+	status = "okay";
+};
+
+&i2c20 {
+	status = "okay";
+};
+
+&i2c21 {
+	status = "okay";
+};
+
+&i2c22 {
+	status = "okay";
+};
+
+&i2c23 {
+	status = "okay";
+};
+
+&i2c24 {
+	status = "okay";
+};
+
+&i2c25 {
+	status = "okay";
+};
+
+&i2c26 {
+	status = "okay";
+};
Signature · 1 line
2.34.1
maintainer
#6 lore raw

Re: [PATCH v2 2/2] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Quoted 90 lines · Tomer Maimon

Enable peripheral support for the Nuvoton NPCM845 Evaluation Board by adding device nodes for Ethernet controllers, MMC controller, SPI controllers, USB device controllers, random number generator, ADC, PWM-FAN controller, I2C controllers, and PECI interface. Include MDIO nodes for Ethernet PHYs, reserved memory for TIP, and aliases for device access.

Signed-off-by Tomer Maimon <[email protected]>

---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 439
++++++++++++++++++

 1 file changed, 439 insertions(+)
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +0 -0
index 2638ee1c3846..145a2e599600 100644
@@ -10,6 +10,42 @@ / {


        aliases {
                serial0 = &serial0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+               ethernet3 = &gmac3;
+               mdio-gpio0 = &mdio0;
+               mdio-gpio1 = &mdio1;
+               fiu0 = &fiu0;
+               fiu1 = &fiu3;
+               fiu2 = &fiux;
+               fiu3 = &fiu1;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+               i2c7 = &i2c7;
+               i2c8 = &i2c8;
+               i2c9 = &i2c9;
+               i2c10 = &i2c10;
+               i2c11 = &i2c11;
+               i2c12 = &i2c12;
+               i2c13 = &i2c13;
+               i2c14 = &i2c14;
+               i2c15 = &i2c15;
+               i2c16 = &i2c16;
+               i2c17 = &i2c17;
+               i2c18 = &i2c18;
+               i2c19 = &i2c19;
+               i2c20 = &i2c20;
+               i2c21 = &i2c21;
+               i2c22 = &i2c22;
+               i2c23 = &i2c23;
+               i2c24 = &i2c24;
+               i2c25 = &i2c25;
+               i2c26 = &i2c26;
        };

        chosen {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +25 -0
@@ -25,12 +61,415 @@ refclk: refclk-25mhz {
                 clock-frequency = <25000000>;
                 #clock-cells = <0>;
         };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               tip_reserved: tip@0 {
+                       reg = <0x0 0x0 0x0 0x6200000>;
+               };
+       };
+
+       mdio0: mdio-0 {
+               compatible = "virtual,mdio-gpio";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+                       <&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+               };
+       };
+
+       mdio1: mdio-1 {
+               compatible = "virtual,mdio-gpio";

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 98

Quoted 10 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0
+               #address-cells = <1>;
+               #size-cells = <0>;
+               gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
+                       <&gpio2 28 GPIO_ACTIVE_HIGH>;
+
+               phy1: ethernet-phy@0 {
+                       reg = <0>;
+               };
+       };
+};

By contrast to ordering the DTSI nodes by unit address, for the referenced nodes that follow here in the DTS, can you please order them alphabetically? Ordering them by unit address is allowed by the DTS style guide, but is super tedious to verify. Alphabetical ordering is also allowed and is straight-forward to enforce:

https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

Cheers,

Andrew

Quoted 24 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +23 -0
+
+&gmac1 {
+       phy-mode = "rgmii-id";
+       snps,eee-force-disable;
+       status = "okay";
+};
+
+&gmac2 {
+       phy-mode = "rmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&r1_pins
+                       &r1oen_pins>;
+       phy-handle = <&phy0>;
+       status = "okay";
+};
+
+&gmac3 {
+       phy-mode = "rmii";
+       pinctrl-names = "default";
+       pinctrl-0 = <&r2_pins
+                       &r2oen_pins>;
+       phy-handle = <&phy1>;
+       status = "okay";
  };
Quoted 6 lines


 &serial0 {
        status = "okay";
 };

+&fiu0 {

*snip*

maintainer
#7 lore raw
In reply to Tomer Maimon

Hi Tomer,

Quoted 17 lines · Tomer Maimon

This series adds device tree support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation Board (EVB).
The first patch introduces peripheral nodes for Ethernet, MMC, SPI, USB, RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device tree. The second patch enables these peripherals for the NPCM845-EVB, adding MDIO nodes, reserved memory, aliases, and board-specific configurations like PHY modes and SPI flash partitions.

The NPCM8XX device tree tested on NPCM845 evaluation board.

Addressed comments from:
        - Krzysztof Kozlowski: https://lkml.indiana.edu/2507.3/05464.html
                                                   https://lkml.indiana.edu/2507.3/05465.html
Changes since version 1:
        - Fix commit message
        - Fix dtbs_check warnings.

Quoted 9 lines

Tomer Maimon (2):
  arm64: dts: nuvoton: npcm845: Add peripheral nodes
  arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 702 +++++++++++++++++- .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 439 +++++++++++ .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |   7 +

 3 files changed, 1147 insertions(+), 1 deletion(-)

Running make CHECK_DTBS=y nuvoton/nuvoton-npcm845-evb.dtb after applying the patches on next-20250908 I get the warnings below. Given

- https://docs.kernel.org/process/maintainer-soc.html#validating-devicetree-files

and

- https://docs.kernel.org/process/maintainer-soc-clean-dts.html

can you please tidy this up?

Thanks,

Andrew

[I] 0 andrew@heihei ~/s/k/l/o/build.arm64.default ((00e2ab2e))> make CHECK_DTBS=y nuvoton/nuvoton-npcm845-evb.dtb
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC [C] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: / (nuvoton,npcm845-evb): memory@0: 'device_type' is a required property
from schema $id: http://devicetree.org/schemas/memory.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: system-controller@f0800000 (nuvoton,npcm845-gcr): compatible: ['nuvoton,npcm845-gcr', 'syscon'] is too short
from schema $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: interrupt-controller@dfff9000 (arm,gic-400): 'ppi-partitions' does not match any of the regexes: '^pinctrl-[0-9]+$', '^v2m@[0-9a-f]+$'
from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: mmc@f0842000 (nuvoton,npcm845-sdhci): Unevaluated properties are not allowed ('clock-names' was unexpected)
from schema $id: http://devicetree.org/schemas/mmc/npcm,sdhci.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/spi@fb000000: failed to match any schema with compatible: ['nuvoton,npcm845-fiu'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): $nodename:0: 'spi-nor@0' does not match '^(flash|.*sram|nand)(@.*)?$'
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): partitions: Unevaluated properties are not allowed ('spare1@D00000', 'spare2@F00000' were unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): Unevaluated properties are not allowed ('partitions' was unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/spi@fb002000: failed to match any schema with compatible: ['nuvoton,npcm845-fiu'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): $nodename:0: 'spi-nor@0' does not match '^(flash|.*sram|nand)(@.*)?$'
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): Unevaluated properties are not allowed ('partitions' was unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/spi@c0000000: failed to match any schema with compatible: ['nuvoton,npcm845-fiu'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): $nodename:0: 'spi-nor@0' does not match '^(flash|.*sram|nand)(@.*)?$'
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: spi-nor@0 (jedec,spi-nor): Unevaluated properties are not allowed ('partitions' was unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/spi@fb001000: failed to match any schema with compatible: ['nuvoton,npcm845-fiu'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0830000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:

        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0830000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0831000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0831000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0832000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0832000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0833000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0833000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0834000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0834000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0835000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0835000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0836000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0836000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0837000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0837000 (nuvoton,npcm845-udc): Unevaluated properties are not allowed ('compatible' was unexpected)
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0838000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: usb@f0839000 (nuvoton,npcm845-udc): compatible: 'oneOf' conditional failed, one must be fixed:
        ['nuvoton,npcm845-udc'] is too short
        'nuvoton,npcm845-udc' is not one of ['chipidea,usb2', 'lsi,zevio-usb', 'nuvoton,npcm750-udc', 'nvidia,tegra20-ehci', 'nvidia,tegra20-udc', 'nvidia,tegra30-ehci', 'nvidia,tegra30-udc', 'nvidia,tegra114-udc', 'nvidia,tegra124-udc', 'nxp,s32g2-usb', 'qcom,ci-hdrc']
        'nuvoton,npcm845-udc' is not one of ['nvidia,tegra114-ehci', 'nvidia,tegra124-ehci', 'nvidia,tegra210-ehci']
        'xlnx,zynq-usb-2.20a' was expected
        'nuvoton,npcm845-udc' is not one of ['nxp,s32g3-usb']
        from schema $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/spi@201000: failed to match any schema with compatible: ['nuvoton,npcm845-pspi'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: timer@8000 (nuvoton,npcm845-timer): 'clock-names' does not match any of the regexes: '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/timer/nuvoton,npcm7xx-timer.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: rng@b000 (nuvoton,npcm845-rng): 'clocks' does not match any of the regexes: '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/rng/nuvoton,npcm-rng.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@801c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@801c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@901c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@901c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@a01c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/watchdog@a01c: failed to match any schema with compatible: ['nuvoton,npcm845-wdt', 'nuvoton,npcm750-wdt'] arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/pwm-fan-controller@103000: failed to match any schema with compatible: ['nuvoton,npcm845-pwm-fan'] /home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@0: fan-tach-ch: b'\x00\x01' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@1: fan-tach-ch: b'\x02\x03' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@2: fan-tach-ch: b'\x04\x05' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@3: fan-tach-ch: b'\x06\x07' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@4: fan-tach-ch: b'\x08\t' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@5: fan-tach-ch: b'\n\x0b' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@6: fan-tach-ch: b'\x0c\r' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
/home/andrew/src/kernel.org/linux/origin/build.arm64.default/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: fan@7: fan-tach-ch: b'\x0e\x0f' is not of type 'object', 'integer', 'array', 'boolean', 'null'
from schema $id: http://devicetree.org/schemas/dt-core.yaml#
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dtb: /ahb/bus@f0000000/i2c@86000/tmp100@48: failed to match any schema with compatible: ['tmp100']