AMD MCA interrupts rework

Hi all,

This set unifies the AMD MCA interrupt handlers with common MCA code. The goal is to avoid duplicating functionality like reading and clearing MCA banks.

Based on feedback, this revision also include changes to the MCA init flow.

Patch 1:
Update MCA init ordering.

Patches 2-5:
Add BSP-only init flow and related changes.

Patches 6-9:
Unify AMD interrupt handlers with common MCE code.

Patches 10-11:
SMCA Corrected Error Interrupt support.

Patches 12-14:
Interrupt storm handling rebased on current set.

Patch 15:
Add support to get threshold limit from APEI HEST.

Thanks,
Yazen

---
Changes in v6:
- Rebase on tip/ras/core.
- Address comments from Boris for patches 1, 8, and 10.
- Link to v5: https://lore.kernel.org/r/[email protected]

Changes in v5:
- Rebase on v6.17-rc1.
- Add tags and address comments from Nikolay.
- Added back patch that was dropped from v4.
- Link to v4: https://lore.kernel.org/r/[email protected]

Changes in v4:
- Rebase on v6.16-rc3.
- Address comments from Boris about function names.
- Redo DFR handler integration.
- Drop AMD APIC LVT rework.
- Include more AMD thresholding reworks and fixes.
- Add support to get threshold limit from APEI HEST.
- Reorder patches so most fixes and reworks are at the beginning.
- Link to v3: https://lore.kernel.org/r/[email protected]

Changes in v3:
- Rebased on tip/x86/merge rather than tip/master.
- Updated MSR access helpers (*msrl -> *msrq).
- Add patch to fix polling after a storm.
- Link to v2: https://lore.kernel.org/r/[email protected]

Changes in v2:
- Add general cleanup pre-patches.
- Add changes for BSP-only init.
- Add interrupt storm handling for AMD.
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Smita Koralahalli (1):
x86/mce: Handle AMD threshold interrupt storms

Yazen Ghannam (14):
x86/mce: Set CR4.MCE last during init
x86/mce: Define BSP-only init
x86/mce: Define BSP-only SMCA init
x86/mce: Do 'UNKNOWN' vendor check early
x86/mce: Separate global and per-CPU quirks
x86/mce: Move machine_check_poll() status checks to helper functions x86/mce: Add clear_bank() helper
x86/mce: Unify AMD THR handler with MCA Polling
x86/mce: Unify AMD DFR handler with MCA Polling x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems x86/mce/amd: Support SMCA Corrected Error Interrupt x86/mce/amd: Remove redundant reset_block()
x86/mce/amd: Define threshold restart function for banks x86/mce: Save and use APEI corrected threshold limit

 arch/x86/include/asm/mce.h          |  14 ++
 arch/x86/kernel/acpi/apei.c         |   2 +
 arch/x86/kernel/cpu/common.c        |   1 +
 arch/x86/kernel/cpu/mce/amd.c       | 367 +++++++++++++++---------------------
 arch/x86/kernel/cpu/mce/core.c      | 280 +++++++++++++++------------
 arch/x86/kernel/cpu/mce/intel.c     |  18 ++
 arch/x86/kernel/cpu/mce/internal.h  |   9 +
 arch/x86/kernel/cpu/mce/threshold.c |  16 ++
 8 files changed, 374 insertions(+), 333 deletions(-)

---
base-commit: 9f34032ec0deef58bd0eb7475f1981adfa998648
change-id: 20250210-wip-mca-updates-bed2a67c9c57

Set the CR4.MCE bit as the last step during init. This brings the MCA init flow closer to what is described in the x86 docs.

x86 docs:

	AMD		Intel
			MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL
	MCG_CTL
	CR4.MCE		CR4.MCE

Current Linux:

	AMD		Intel
	CR4.MCE		CR4.MCE
	MCG_CTL		MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL

Updated Linux:

	AMD		Intel
	MCG_CTL		MCG_CTL
	MCA_CONFIG	MCG_EXT_CTL
	MCi_CTL		MCi_CTL
	CR4.MCE		CR4.MCE

The new init flow will match Intel's docs, but there will still be a mismatch for AMD regarding MCG_CTL. However, there is no known issue with this ordering, so leave it for now.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* Only move CR4.MCE programming.
* Update commit message to match the new change.

v4->v5:
* New in v5.

 arch/x86/kernel/cpu/mce/core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

index 0326fbb83adc..9e31834b3542 100644
@@ -1850,8 +1850,6 @@ static void __mcheck_cpu_init_generic(void)
 {
 	u64 cap;
 
-	cr4_set_bits(X86_CR4_MCE);
-
 	rdmsrq(MSR_IA32_MCG_CAP, cap);
 	if (cap & MCG_CTL_P)
 		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);

@@ -2276,6 +2274,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
 	__mcheck_cpu_init_vendor(c);
 	__mcheck_cpu_init_prepare_banks();
 	__mcheck_cpu_setup_timer();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 /*

@@ -2443,6 +2442,7 @@ static void mce_syscore_resume(void)
 	__mcheck_cpu_init_generic();
 	__mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info));
 	__mcheck_cpu_init_prepare_banks();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 static struct syscore_ops mce_syscore_ops = {

@@ -2462,6 +2462,7 @@ static void mce_cpu_restart(void *data)
 	__mcheck_cpu_init_generic();
 	__mcheck_cpu_init_prepare_banks();
 	__mcheck_cpu_init_timer();
+	cr4_set_bits(X86_CR4_MCE);
 }
 
 /* Reinit MCEs after user configuration changes */

2.51.0

Currently, MCA initialization is executed identically on each CPU as they are brought online. However, a number of MCA initialization tasks only need to be done once.

Define a function to collect all 'global' init tasks and call this from the BSP only. Start with CPU features.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* No change.

v4->v5:
* No change.

v3->v4:
* Change cpu_mca_init() to mca_bsp_init().
* Drop code comment.

v2->v3:
* Add tags from Qiuxu and Tony.

v1->v2:
* New in v2.

 arch/x86/include/asm/mce.h     |  2 ++
 arch/x86/kernel/cpu/common.c   |  1 +
 arch/x86/kernel/cpu/mce/amd.c  |  3 ---
 arch/x86/kernel/cpu/mce/core.c | 28 +++++++++++++++++++++-------
 4 files changed, 24 insertions(+), 10 deletions(-)

index 3224f3862dc8..31e3cb550fb3 100644
@@ -241,12 +241,14 @@ struct cper_ia_proc_ctx;
 
 #ifdef CONFIG_X86_MCE
 int mcheck_init(void);
+void mca_bsp_init(struct cpuinfo_x86 *c);
 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
 			       u64 lapic_id);
 #else
 static inline int mcheck_init(void) { return 0; }
+static inline void mca_bsp_init(struct cpuinfo_x86 *c) {}
 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
 static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,

index 34a054181c4d..8bbfde05f04f 100644
@@ -1784,6 +1784,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 		setup_clear_cpu_cap(X86_FEATURE_LA57);
 
 	detect_nopl();
+	mca_bsp_init(c);
 }
 
 void __init init_cpu_devs(void)

index aa13c9304ad8..3c6c19eb0a18 100644
@@ -653,9 +653,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 	u32 low = 0, high = 0, address = 0;
 	int offset = -1;
 
-	mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV);
-	mce_flags.succor	 = cpu_feature_enabled(X86_FEATURE_SUCCOR);
-	mce_flags.smca		 = cpu_feature_enabled(X86_FEATURE_SMCA);
 	mce_flags.amd_threshold	 = 1;
 
 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {

index 9e31834b3542..79f3dd7f7851 100644
@@ -1837,13 +1837,6 @@ static void __mcheck_cpu_cap_init(void)
 	this_cpu_write(mce_num_banks, b);
 
 	__mcheck_cpu_mce_banks_init();
-
-	/* Use accurate RIP reporting if available. */
-	if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
-		mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
-
-	if (cap & MCG_SER_P)
-		mca_cfg.ser = 1;
 }
 
 static void __mcheck_cpu_init_generic(void)

@@ -2240,6 +2233,27 @@ DEFINE_IDTENTRY_RAW(exc_machine_check)
 }
 #endif
 
+void mca_bsp_init(struct cpuinfo_x86 *c)
+{
+	u64 cap;
+
+	if (!mce_available(c))
+		return;
+
+	mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV);
+	mce_flags.succor	 = cpu_feature_enabled(X86_FEATURE_SUCCOR);
+	mce_flags.smca		 = cpu_feature_enabled(X86_FEATURE_SMCA);
+
+	rdmsrq(MSR_IA32_MCG_CAP, cap);
+
+	/* Use accurate RIP reporting if available. */
+	if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
+		mca_cfg.rip_msr = MSR_IA32_MCG_EIP;
+
+	if (cap & MCG_SER_P)
+		mca_cfg.ser = 1;
+}
+
 /*
  * Called for each booted CPU to set up machine checks.
  * Must be called with preempt off:

2.51.0

<snip>

Thanks Nikokay for the reviews.

I think technically no, they won't be mandated to be identical. We already have per-CPU feature bits, registers, etc. And in Scalable MCA there are also per-bank config bits.

However, this doesn't mean we will have different MCE features between CPUs in a system just yet. The architects do try to make things flexible and scalable just in case there is a need in the future.

We can code to the architectures and be *mostly* future-proof. But it's not guaranteed to be without bugs. And it's not guaranteed that every possible case will be used.

Do you have any concerns or see any issues with the code today in this area? Maybe you're thinking we should have per-CPU config for feature bits? If so, I agree but we don't have a real need today AFAIK.

Maybe others can comment too.

Thanks,
Yazen

Yes, for example in your current code you assume that whatever the value of MSR_IA32_MCG_CAP w.r.t MCG_EXT_P or MCG_SER_P it will be identical for all CPUs. That might be fine, but what if, in the future, we end up with machines where MCG_CAP will have different values for different CPU's/cores.

Or that in a system we can end up with cpu's which have different X86_FEATURE_SMCA value.

OTOH, you are right that when the time comes we can worry about this since there can possibly be infinite number of possible scenarios.

Intel P and E cores have the same architectural MCE behavior (though the model specific bits like IA32_MCi_MISC and IA32_STATUS.MSCOD could be different on cores in the same hybrid part).

-Tony

Currently on AMD systems, MCA interrupt handler functions are set during CPU init. However, the functions only need to be set once for the whole system.

Assign the handlers only during BSP init. Do so only for SMCA systems to maintain the old behavior for legacy systems.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * Change mce_smca_cpu_init() to smca_bsp_init().
    
    v2->v3:
    * No change.
    
    v1->v2:
    * New in v2.

 arch/x86/kernel/cpu/mce/amd.c      | 6 ++++++
 arch/x86/kernel/cpu/mce/core.c     | 3 +++
 arch/x86/kernel/cpu/mce/internal.h | 2 ++
 3 files changed, 11 insertions(+)

index 3c6c19eb0a18..7345e24bf658 100644
@@ -684,6 +684,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 		deferred_error_interrupt_enable(c);
 }
 
+void smca_bsp_init(void)
+{
+	mce_threshold_vector	  = amd_threshold_interrupt;
+	deferred_error_int_vector = amd_deferred_error_interrupt;
+}
+
 /*
  * DRAM ECC errors are reported in the Northbridge (bank 4) with
  * Extended Error Code 8.

index 79f3dd7f7851..a8cb7ff53e32 100644
@@ -2244,6 +2244,9 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
 	mce_flags.succor	 = cpu_feature_enabled(X86_FEATURE_SUCCOR);
 	mce_flags.smca		 = cpu_feature_enabled(X86_FEATURE_SMCA);
 
+	if (mce_flags.smca)
+		smca_bsp_init();
+
 	rdmsrq(MSR_IA32_MCG_CAP, cap);
 
 	/* Use accurate RIP reporting if available. */

index 64ac25b95360..6cb2995f0ec1 100644
@@ -294,12 +294,14 @@ static __always_inline void smca_extract_err_addr(struct mce *m)
 	m->addr &= GENMASK_ULL(55, lsb);
 }
 
+void smca_bsp_init(void);
 #else
 static inline void mce_threshold_create_device(unsigned int cpu)	{ }
 static inline void mce_threshold_remove_device(unsigned int cpu)	{ }
 static inline bool amd_filter_mce(struct mce *m) { return false; }
 static inline bool amd_mce_usable_address(struct mce *m) { return false; }
 static inline void smca_extract_err_addr(struct mce *m) { }
+static inline void smca_bsp_init(void) { }
 #endif
 
 #ifdef CONFIG_X86_ANCIENT_MCE

2.51.0

The 'UNKNOWN' vendor check is handled as a quirk that is run on each online CPU. However, all CPUs are expected to have the same vendor.

Move the 'UNKNOWN' vendor check to the BSP-only init so it is done early and once. Remove the unnecessary return value from the quirks check.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * No change.
    
    v2->v3:
    * Add tags from Qiuxu and Tony.
    
    v1->v2:
    * New in v2.

 arch/x86/kernel/cpu/mce/core.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

index a8cb7ff53e32..515942cbfeb5 100644
@@ -1977,14 +1977,11 @@ static void apply_quirks_zhaoxin(struct cpuinfo_x86 *c)
 }
 
 /* Add per CPU specific workarounds here */
-static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
+static void __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 {
 	struct mca_config *cfg = &mca_cfg;
 
 	switch (c->x86_vendor) {
-	case X86_VENDOR_UNKNOWN:
-		pr_info("unknown CPU type - not enabling MCE support\n");
-		return false;
 	case X86_VENDOR_AMD:
 		apply_quirks_amd(c);
 		break;

@@ -2000,8 +1997,6 @@ static bool __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 		cfg->monarch_timeout = 0;
 	if (cfg->bootlog != 0)
 		cfg->panic_timeout = 30;
-
-	return true;
 }
 
 static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)

@@ -2240,6 +2235,12 @@ void mca_bsp_init(struct cpuinfo_x86 *c)
 	if (!mce_available(c))
 		return;
 
+	if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
+		mca_cfg.disabled = 1;
+		pr_info("unknown CPU type - not enabling MCE support\n");
+		return;
+	}
+
 	mce_flags.overflow_recov = cpu_feature_enabled(X86_FEATURE_OVERFLOW_RECOV);
 	mce_flags.succor	 = cpu_feature_enabled(X86_FEATURE_SUCCOR);
 	mce_flags.smca		 = cpu_feature_enabled(X86_FEATURE_SMCA);

@@ -2274,10 +2275,7 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
 
 	__mcheck_cpu_cap_init();
 
-	if (!__mcheck_cpu_apply_quirks(c)) {
-		mca_cfg.disabled = 1;
-		return;
-	}
+	__mcheck_cpu_apply_quirks(c);
 
 	if (!mce_gen_pool_init()) {
 		mca_cfg.disabled = 1;

2.51.0

Many quirks are global configuration settings and a handful apply to each CPU.

Move the per-CPU quirks to vendor init to execute them on each online CPU. Set the global quirks during BSP-only init so they're only executed once and early.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* No change.

v4->v5:
* Apply consistent naming to quirk functions.

v3->v4:
* Add newline in mce_amd_feature_init().
* Remove __mcheck_cpu_apply_quirks().
* Update code comment ref. __mcheck_cpu_apply_quirks().

v2->v3:
* Update code comment.
* Add tags from Qiuxu and Tony.

v1->v2:
* New in v2.

 arch/x86/kernel/cpu/mce/amd.c   | 24 ++++++++++++
 arch/x86/kernel/cpu/mce/core.c  | 85 +++++++++++------------------------------
 arch/x86/kernel/cpu/mce/intel.c | 18 +++++++++
 3 files changed, 65 insertions(+), 62 deletions(-)

index 7345e24bf658..b8aed0ac765c 100644
@@ -646,6 +646,28 @@ static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
 		wrmsrq(MSR_K7_HWCR, hwcr);
 }
 
+static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c)
+{
+	struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array);
+
+	/* This should be disabled by the BIOS, but isn't always */
+	if (c->x86 == 15 && this_cpu_read(mce_num_banks) > 4) {
+		/*
+		 * disable GART TBL walk error reporting, which
+		 * trips off incorrectly with the IOMMU & 3ware
+		 * & Cerberus:
+		 */
+		clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
+	}
+
+	/*
+	 * Various K7s with broken bank 0 around. Always disable
+	 * by default.
+	 */
+	if (c->x86 == 6 && this_cpu_read(mce_num_banks))
+		mce_banks[0].ctl = 0;
+}
+
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {

@@ -653,6 +675,8 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 	u32 low = 0, high = 0, address = 0;
 	int offset = -1;
 
+	amd_apply_cpu_quirks(c);
+
 	mce_flags.amd_threshold	 = 1;
 
 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {

index 9b149b9c4109..4655223ba560 100644
@@ -468,8 +468,26 @@ static void intel_imc_init(struct cpuinfo_x86 *c)
 	}
 }
 
+static void intel_apply_cpu_quirks(struct cpuinfo_x86 *c)
+{
+	/*
+	 * SDM documents that on family 6 bank 0 should not be written
+	 * because it aliases to another special BIOS controlled
+	 * register.
+	 * But it's not aliased anymore on model 0x1a+
+	 * Don't ignore bank 0 completely because there could be a
+	 * valid event later, merely don't write CTL0.
+	 *
+	 * Older CPUs (prior to family 6) can't reach this point and already
+	 * return early due to the check of __mcheck_cpu_ancient_init().
+	 */
+	if (c->x86_vfm < INTEL_NEHALEM_EP && this_cpu_read(mce_num_banks))
+		this_cpu_ptr(mce_banks_array)[0].init = false;
+}
+
 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 {
+	intel_apply_cpu_quirks(c);
 	intel_init_cmci();
 	intel_init_lmce();
 	intel_imc_init(c);

2.51.0

There are a number of generic and vendor-specific status checks in machine_check_poll(). These are used to determine if an error should be skipped.

Move these into helper functions. Future vendor-specific checks will be added to the helpers.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* No change.

v4->v5:
* No change.

v3->v4:
* No change.

v2->v3:
* Add tags from Qiuxu and Tony.

v1->v2:
* Change log_poll_error() to should_log_poll_error().
* Keep code comment.

 arch/x86/kernel/cpu/mce/core.c | 88 +++++++++++++++++++++++-------------------
 1 file changed, 48 insertions(+), 40 deletions(-)

index 7fd86c8006ba..5dec0da6169e 100644
@@ -714,6 +714,52 @@ static noinstr void mce_read_aux(struct mce_hw_err *err, int i)
 
 DEFINE_PER_CPU(unsigned, mce_poll_count);
 
+/*
+ * Newer Intel systems that support software error
+ * recovery need to make additional checks. Other
+ * CPUs should skip over uncorrected errors, but log
+ * everything else.
+ */
+static bool ser_should_log_poll_error(struct mce *m)
+{
+	/* Log "not enabled" (speculative) errors */
+	if (!(m->status & MCI_STATUS_EN))
+		return true;
+
+	/*
+	 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
+	 * UC == 1 && PCC == 0 && S == 0
+	 */
+	if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S))
+		return true;
+
+	return false;
+}
+
+static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
+{
+	struct mce *m = &err->m;
+
+	/* If this entry is not valid, ignore it. */
+	if (!(m->status & MCI_STATUS_VAL))
+		return false;
+
+	/*
+	 * If we are logging everything (at CPU online) or this
+	 * is a corrected error, then we must log it.
+	 */
+	if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC))
+		return true;
+
+	if (mca_cfg.ser)
+		return ser_should_log_poll_error(m);
+
+	if (m->status & MCI_STATUS_UC)
+		return false;
+
+	return true;
+}
+
 /*
  * Poll for corrected events or events that happened before reset.
  * Those are just logged through /dev/mcelog.

@@ -765,48 +811,10 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 		if (!mca_cfg.cmci_disabled)
 			mce_track_storm(m);
 
-		/* If this entry is not valid, ignore it */
-		if (!(m->status & MCI_STATUS_VAL))
+		/* Verify that the error should be logged based on hardware conditions. */
+		if (!should_log_poll_error(flags, &err))
 			continue;
 
-		/*
-		 * If we are logging everything (at CPU online) or this
-		 * is a corrected error, then we must log it.
-		 */
-		if ((flags & MCP_UC) || !(m->status & MCI_STATUS_UC))
-			goto log_it;
-
-		/*
-		 * Newer Intel systems that support software error
-		 * recovery need to make additional checks. Other
-		 * CPUs should skip over uncorrected errors, but log
-		 * everything else.
-		 */
-		if (!mca_cfg.ser) {
-			if (m->status & MCI_STATUS_UC)
-				continue;
-			goto log_it;
-		}
-
-		/* Log "not enabled" (speculative) errors */
-		if (!(m->status & MCI_STATUS_EN))
-			goto log_it;
-
-		/*
-		 * Log UCNA (SDM: 15.6.3 "UCR Error Classification")
-		 * UC == 1 && PCC == 0 && S == 0
-		 */
-		if (!(m->status & MCI_STATUS_PCC) && !(m->status & MCI_STATUS_S))
-			goto log_it;
-
-		/*
-		 * Skip anything else. Presumption is that our read of this
-		 * bank is racing with a machine check. Leave the log alone
-		 * for do_machine_check() to deal with it.
-		 */
-		continue;
-
-log_it:
 		mce_read_aux(&err, i);
 		m->severity = mce_severity(m, NULL, NULL, false);
 		/*

2.51.0

Add a helper at the end of the MCA polling function to collect vendor and/or feature actions.

Start with a basic skeleton for now. Actions for AMD thresholding and deferred errors will be added later.

---

Notes:

    Link:
    https://lore.kernel.org/r/20250903094859.GGaLgPC_eWQgAqpHHb@fat_crate.local
    
    v5->v6:
    * New in v6.

 arch/x86/kernel/cpu/mce/amd.c      |  5 +++++
 arch/x86/kernel/cpu/mce/core.c     | 12 ++++++++++--
 arch/x86/kernel/cpu/mce/internal.h |  3 +++
 3 files changed, 18 insertions(+), 2 deletions(-)

index b8aed0ac765c..d6906442f49b 100644
@@ -955,6 +955,11 @@ static void amd_threshold_interrupt(void)
 	}
 }
 
+void amd_clear_bank(struct mce *m)
+{
+	mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);
+}
+
 /*
  * Sysfs Interface
  */

index 5dec0da6169e..06645f56b564 100644
@@ -423,7 +423,7 @@ noinstr u64 mce_rdmsrq(u32 msr)
 	return EAX_EDX_VAL(val, low, high);
 }
 
-static noinstr void mce_wrmsrq(u32 msr, u64 v)
+noinstr void mce_wrmsrq(u32 msr, u64 v)
 {
 	u32 low, high;
 

@@ -760,6 +760,14 @@ static bool should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *err)
 	return true;
 }
 
+static void clear_bank(struct mce *m)
+{
+	if (m->cpuvendor == X86_VENDOR_AMD)
+		return amd_clear_bank(m);
+
+	mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);
+}
+
 /*
  * Poll for corrected events or events that happened before reset.
  * Those are just logged through /dev/mcelog.

@@ -834,7 +842,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
 		/*
 		 * Clear state for this bank.
 		 */
-		mce_wrmsrq(mca_msr_reg(i, MCA_STATUS), 0);
+		clear_bank(m);
 	}
 
 	/*

index 6cb2995f0ec1..b0e00ec5cc8c 100644
@@ -269,6 +269,7 @@ void mce_threshold_create_device(unsigned int cpu);
 void mce_threshold_remove_device(unsigned int cpu);
 extern bool amd_filter_mce(struct mce *m);
 bool amd_mce_usable_address(struct mce *m);
+void amd_clear_bank(struct mce *m);
 
 /*
  * If MCA_CONFIG[McaLsbInStatusSupported] is set, extract ErrAddr in bits

@@ -300,6 +301,7 @@ static inline void mce_threshold_create_device(unsigned int cpu)	{ }
 static inline void mce_threshold_remove_device(unsigned int cpu)	{ }
 static inline bool amd_filter_mce(struct mce *m) { return false; }
 static inline bool amd_mce_usable_address(struct mce *m) { return false; }
+static inline void amd_clear_bank(struct mce *m) { }
 static inline void smca_extract_err_addr(struct mce *m) { }
 static inline void smca_bsp_init(void) { }
 #endif

@@ -319,6 +321,7 @@ static __always_inline void winchip_machine_check(struct pt_regs *regs) {}
 #endif
 
 noinstr u64 mce_rdmsrq(u32 msr);
+noinstr void mce_wrmsrq(u32 msr, u64 v);
 
 static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
 {

2.51.0

AMD systems optionally support an MCA thresholding interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how the Intel Corrected Machine Check interrupt (CMCI) is handled.

AMD MCA thresholding is managed using the MCA_MISC registers within an MCA bank. The OS will need to modify the hardware error count field in order to reset the threshold limit and rearm the interrupt. Management of the MCA_MISC register should be done as a follow up to the basic MCA polling flow. It should not be the main focus of the interrupt handler.

Furthermore, future systems will have the ability to send an MCA thresholding interrupt to the OS even when the OS does not manage the feature, i.e. MCA_MISC registers are Read-as-Zero/Locked.

Call the common MCA polling function when handling the MCA thresholding interrupt. This will allow the OS to find any valid errors whether or not the MCA thresholding feature is OS-managed. Also, this allows the common MCA polling options and kernel parameters to apply to AMD systems.

Add a callback to the MCA polling function to check and reset any threshold blocks that have reached their threshold limit.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* Move bank/block reset code to new helper.

v4->v5:
* No change.

v3->v4:
* No change.

v2->v3:
* Add tags from Qiuxu and Tony.

v1->v2:
* Start collecting per-CPU items in a struct.
* Keep and use mce_flags.amd_threshold.

 arch/x86/kernel/cpu/mce/amd.c | 51 +++++++++++++++++++------------------------
 1 file changed, 23 insertions(+), 28 deletions(-)

index d6906442f49b..ac6a98aa7bc2 100644
@@ -54,6 +54,12 @@
 
 static bool thresholding_irq_en;
 
+struct mce_amd_cpu_data {
+	mce_banks_t     thr_intr_banks;
+};
+
+static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data);
+
 static const char * const th_names[] = {
 	"load_store",
 	"insn_fetch",

@@ -556,6 +562,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 	if (!b.interrupt_capable)
 		goto done;
 
+	__set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks);
 	b.interrupt_enable = 1;
 
 	if (!mce_flags.smca) {

@@ -896,12 +903,7 @@ static void amd_deferred_error_interrupt(void)
 		log_error_deferred(bank);
 }
 
-static void log_error_thresholding(unsigned int bank, u64 misc)
-{
-	_log_error_deferred(bank, misc);
-}
-
-static void log_and_reset_block(struct threshold_block *block)
+static void reset_block(struct threshold_block *block)
 {
 	struct thresh_restart tr;
 	u32 low = 0, high = 0;

@@ -915,23 +917,14 @@ static void log_and_reset_block(struct threshold_block *block)
 	if (!(high & MASK_OVERFLOW_HI))
 		return;
 
-	/* Log the MCE which caused the threshold event. */
-	log_error_thresholding(block->bank, ((u64)high << 32) | low);
-
-	/* Reset threshold block after logging error. */
 	memset(&tr, 0, sizeof(tr));
 	tr.b = block;
 	threshold_restart_block(&tr);
 }
 
-/*
- * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
- * goes off when error_count reaches threshold_limit.
- */
-static void amd_threshold_interrupt(void)
+static void amd_reset_thr_limit(unsigned int bank)
 {
-	struct threshold_bank **bp = this_cpu_read(threshold_banks), *thr_bank;
-	unsigned int bank, cpu = smp_processor_id();
+	struct threshold_bank **bp = this_cpu_read(threshold_banks);
 	struct threshold_block *block, *tmp;
 
 	/*

@@ -939,24 +932,26 @@ static void amd_threshold_interrupt(void)
 	 * handler is installed at boot time, but on a hotplug event the
 	 * interrupt might fire before the data has been initialized.
 	 */
-	if (!bp)
+	if (!bp || !bp[bank])
 		return;
 
-	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
-		if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))
-			continue;
-
-		thr_bank = bp[bank];
-		if (!thr_bank)
-			continue;
+	list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj)
+		reset_block(block);
+}
 
-		list_for_each_entry_safe(block, tmp, &thr_bank->miscj, miscj)
-			log_and_reset_block(block);
-	}
+/*
+ * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
+ * goes off when error_count reaches threshold_limit.
+ */
+static void amd_threshold_interrupt(void)
+{
+	machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->thr_intr_banks);
 }
 
 void amd_clear_bank(struct mce *m)
 {
+	amd_reset_thr_limit(m->bank);
+
 	mce_wrmsrq(mca_msr_reg(m->bank, MCA_STATUS), 0);
 }
 

2.51.0

AMD systems optionally support a deferred error interrupt. The interrupt should be used as another signal to trigger MCA polling. This is similar to how other MCA interrupts are handled.

Deferred errors do not require any special handling related to the interrupt, e.g. resetting or rearming the interrupt, etc.

However, Scalable MCA systems include a pair of registers, MCA_DESTAT and MCA_DEADDR, that should be checked for valid errors. This check should be done whenever MCA registers are polled. Currently, the deferred error interrupt does this check, but the MCA polling function does not.

Call the MCA polling function when handling the deferred error interrupt. This keeps all "polling" cases in a common function.

Call the polling function only for banks that have the deferred error interrupt enabled.

Add an SMCA status check helper. This will do the same status check and register clearing that the interrupt handler has done. And it extends the common polling flow to find AMD deferred errors.

Remove old code whose functionality is already covered in the common MCA code.

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* Move status clearing code to new helper.

v4->v5:
* No change.

v3->v4:
* Add kflag for checking DFR registers.

v2->v3:
* Add tags from Qiuxu and Tony.

v1->v2:
* Keep code comment.
* Log directly from helper function rather than pass values.

Link:
https://lore.kernel.org/r/[email protected]

v2->v3:
* Add tags from Qiuxu and Tony.

v1->v2:
* Keep code comment.
* Log directly from helper function rather than pass values.

 arch/x86/include/asm/mce.h     |   6 +++
 arch/x86/kernel/cpu/mce/amd.c  | 108 ++++-------------------------------------
 arch/x86/kernel/cpu/mce/core.c |  45 ++++++++++++++++-
 3 files changed, 59 insertions(+), 100 deletions(-)

index 31e3cb550fb3..7d6588195d56 100644
@@ -165,6 +165,12 @@
  */
 #define MCE_IN_KERNEL_COPYIN	BIT_ULL(7)
 
+/*
+ * Indicates that handler should check and clear Deferred error registers
+ * rather than common ones.
+ */
+#define MCE_CHECK_DFR_REGS	BIT_ULL(8)
+
 /*
  * This structure contains all data related to the MCE log.  Also
  * carries a signature to make it easier to find from external

2.51.0

Scalable MCA systems have a per-CPU register that gives the APIC LVT offset for the thresholding and deferred error interrupts.

Currently, this register is read once to set up the deferred error interrupt and then read again for each thresholding block. Furthermore, the APIC LVT registers are configured each time, but they only need to be configured once per-CPU.

Move the APIC LVT setup to the early part of CPU init, so that the registers are set up once. Also, this ensures that the kernel is ready to service the interrupts before the individual error sources (each MCA bank) are enabled.

Apply this change only to SMCA systems to avoid breaking any legacy behavior. The deferred error interrupt is technically advertised by the SUCCOR feature. However, this was first made available on SMCA systems. Therefore, only set up the deferred error interrupt on SMCA systems and simplify the code.

Guidance from hardware designers is that the LVT offsets provided from the platform should be used. The kernel should not try to enforce specific values. However, the kernel should check that an LVT offset is not reused for multiple sources.

Therefore, remove the extra checking and value enforcement from the MCE code. The "reuse/conflict" case is already handled in setup_APIC_eilvt().

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* Applied "bools to flags" and other fixups from Boris.

v4->v5:
* Added back to set.
* Updated commit message with more details.

v3->v4:
* Dropped from set.

v2->v3:
* Add tags from Tony.

v1->v2:
* Use new per-CPU struct.
* Don't set up interrupt vectors.

 arch/x86/kernel/cpu/mce/amd.c | 121 ++++++++++++++++++------------------------
 1 file changed, 53 insertions(+), 68 deletions(-)

index 1b1b83b3aef9..a6f5c9339d7c 100644
@@ -43,9 +43,6 @@
 /* Deferred error settings */
 #define MSR_CU_DEF_ERR		0xC0000410
 #define MASK_DEF_LVTOFF		0x000000F0
-#define MASK_DEF_INT_TYPE	0x00000006
-#define DEF_LVT_OFF		0x2
-#define DEF_INT_TYPE_APIC	0x2
 
 /* Scalable MCA: */
 

@@ -57,6 +54,10 @@ static bool thresholding_irq_en;
 struct mce_amd_cpu_data {
 	mce_banks_t     thr_intr_banks;
 	mce_banks_t     dfr_intr_banks;
+
+	u32		thr_intr_en: 1,
+			dfr_intr_en: 1,
+			__resv: 30;
 };
 
 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_amd_cpu_data, mce_amd_data);

@@ -271,6 +272,7 @@ void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
 
 static void smca_configure(unsigned int bank, unsigned int cpu)
 {
+	struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data);
 	u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
 	const struct smca_hwid *s_hwid;
 	unsigned int i, hwid_mcatype;

@@ -301,8 +303,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
 		 * APIC based interrupt. First, check that no interrupt has been
 		 * set.
 		 */
-		if ((low & BIT(5)) && !((high >> 5) & 0x3)) {
-			__set_bit(bank, this_cpu_ptr(&mce_amd_data)->dfr_intr_banks);
+		if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) {
+			__set_bit(bank, data->dfr_intr_banks);
 			high |= BIT(5);
 		}
 

@@ -377,6 +379,14 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 {
 	int msr = (hi & MASK_LVTOFF_HI) >> 20;
 
+	/*
+	 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
+	 * the BIOS provides the value. The original field where LVT offset
+	 * was set is reserved. Return early here:
+	 */
+	if (mce_flags.smca)
+		return false;
+
 	if (apic < 0) {
 		pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,

@@ -385,14 +395,6 @@ static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
 	}
 
 	if (apic != msr) {
-		/*
-		 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
-		 * the BIOS provides the value. The original field where LVT offset
-		 * was set is reserved. Return early here:
-		 */
-		if (mce_flags.smca)
-			return false;
-
 		pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
 		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
 		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);

@@ -473,41 +475,6 @@ static int setup_APIC_mce_threshold(int reserved, int new)
 	return reserved;
 }
 
-static int setup_APIC_deferred_error(int reserved, int new)
-{
-	if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
-					      APIC_EILVT_MSG_FIX, 0))
-		return new;
-
-	return reserved;
-}
-
-static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
-{
-	u32 low = 0, high = 0;
-	int def_offset = -1, def_new;
-
-	if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
-		return;
-
-	def_new = (low & MASK_DEF_LVTOFF) >> 4;
-	if (!(low & MASK_DEF_LVTOFF)) {
-		pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
-		def_new = DEF_LVT_OFF;
-		low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
-	}
-
-	def_offset = setup_APIC_deferred_error(def_offset, def_new);
-	if ((def_offset == def_new) &&
-	    (deferred_error_int_vector != amd_deferred_error_interrupt))
-		deferred_error_int_vector = amd_deferred_error_interrupt;
-
-	if (!mce_flags.smca)
-		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
-
-	wrmsr(MSR_CU_DEF_ERR, low, high);
-}
-
 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
 			     unsigned int bank, unsigned int block,
 			     unsigned int cpu)

@@ -543,12 +510,10 @@ static u32 get_block_address(u32 current_addr, u32 low, u32 high,
 	return addr;
 }
 
-static int
-prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
-			int offset, u32 misc_high)
+static int prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
+				   int offset, u32 misc_high)
 {
 	unsigned int cpu = smp_processor_id();
-	u32 smca_low, smca_high;
 	struct threshold_block b;
 	int new;
 

@@ -568,18 +533,10 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 	__set_bit(bank, this_cpu_ptr(&mce_amd_data)->thr_intr_banks);
 	b.interrupt_enable = 1;
 
-	if (!mce_flags.smca) {
-		new = (misc_high & MASK_LVTOFF_HI) >> 20;
-		goto set_offset;
-	}
-
-	/* Gather LVT offset for thresholding: */
-	if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
-		goto out;
-
-	new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
+	if (mce_flags.smca)
+		goto done;
 
-set_offset:
+	new = (misc_high & MASK_LVTOFF_HI) >> 20;
 	offset = setup_APIC_mce_threshold(offset, new);
 	if (offset == new)
 		thresholding_irq_en = true;

@@ -587,7 +544,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
 done:
 	mce_threshold_block_init(&b, offset);
 
-out:
 	return offset;
 }
 

@@ -678,6 +634,32 @@ static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c)
 		mce_banks[0].ctl = 0;
 }
 
+/*
+ * Enable the APIC LVT interrupt vectors once per-CPU. This should be done before hardware is
+ * ready to send interrupts.
+ *
+ * Individual error sources are enabled later during per-bank init.
+ */
+static void smca_enable_interrupt_vectors(void)
+{
+	struct mce_amd_cpu_data *data = this_cpu_ptr(&mce_amd_data);
+	u64 mca_intr_cfg, offset;
+
+	if (!mce_flags.smca || !mce_flags.succor)
+		return;
+
+	if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg))
+		return;
+
+	offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12;
+	if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0))
+		data->thr_intr_en = 1;
+
+	offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4;
+	if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0))
+		data->dfr_intr_en = 1;
+}
+
 /* cpu init entry point, called from mce.c with preempt off */
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {

@@ -689,10 +671,16 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 
 	mce_flags.amd_threshold	 = 1;
 
+	smca_enable_interrupt_vectors();
+
 	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
-		if (mce_flags.smca)
+		if (mce_flags.smca) {
 			smca_configure(bank, cpu);
 
+			if (!this_cpu_ptr(&mce_amd_data)->thr_intr_en)
+				continue;
+		}
+
 		disable_err_thresholding(c, bank);
 
 		for (block = 0; block < NR_BLOCKS; ++block) {

@@ -713,9 +701,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 			offset = prepare_threshold_block(bank, block, address, offset, high);
 		}
 	}
-
-	if (mce_flags.succor)
-		deferred_error_interrupt_enable(c);
 }
 
 void smca_bsp_init(void)

2.51.0

Yep, thanks for noticing. :)

IIRC, I tried to reduce this set down to (mostly) functional changes.

I think that there is still more worthwhile refactoring to do.

Thanks,
Yazen

AMD systems optionally support MCA thresholding which provides the ability for hardware to send an interrupt when a set error threshold is reached. This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling.

Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA thresholding interrupt, and it will need to poll for correctable errors.

A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA thresholding. However, the Platform will now be able to send the MCA thresholding interrupt to the OS.

Check for, and enable, this feature during per-CPU SMCA init.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * Add code comment describing bits.
    
    v2->v3:
    * Add tags from Tony.
    
    v1->v2:
    * Use new per-CPU struct.

 arch/x86/kernel/cpu/mce/amd.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

index a6f5c9339d7c..34268940c88a 100644
@@ -308,6 +308,23 @@ static void smca_configure(unsigned int bank, unsigned int cpu)
 			high |= BIT(5);
 		}
 
+		/*
+		 * SMCA Corrected Error Interrupt
+		 *
+		 * MCA_CONFIG[IntPresent] is bit 10, and tells us if the bank can
+		 * send an MCA Thresholding interrupt without the OS initializing
+		 * this feature. This can be used if the threshold limit is managed
+		 * by the platform.
+		 *
+		 * MCA_CONFIG[IntEn] is bit 40 (8 in the high portion of the MSR).
+		 * The OS should set this to inform the platform that the OS is ready
+		 * to handle the MCA Thresholding interrupt.
+		 */
+		if ((low & BIT(10)) && data->thr_intr_en) {
+			__set_bit(bank, data->thr_intr_banks);
+			high |= BIT(8);
+		}
+
 		this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
 
 		wrmsr(smca_config, low, high);

2.51.0

Many of the checks in reset_block() are done again in the block reset function. So drop the redundant checks.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * New in v4.

 arch/x86/kernel/cpu/mce/amd.c | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

index 34268940c88a..9ca4079ff342 100644
@@ -812,29 +812,11 @@ static void amd_deferred_error_interrupt(void)
 	machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_banks);
 }
 
-static void reset_block(struct threshold_block *block)
-{
-	struct thresh_restart tr;
-	u32 low = 0, high = 0;
-
-	if (!block)
-		return;
-
-	if (rdmsr_safe(block->address, &low, &high))
-		return;
-
-	if (!(high & MASK_OVERFLOW_HI))
-		return;
-
-	memset(&tr, 0, sizeof(tr));
-	tr.b = block;
-	threshold_restart_block(&tr);
-}
-
 static void amd_reset_thr_limit(unsigned int bank)
 {
 	struct threshold_bank **bp = this_cpu_read(threshold_banks);
 	struct threshold_block *block, *tmp;
+	struct thresh_restart tr;
 
 	/*
 	 * Validate that the threshold bank has been initialized already. The

@@ -844,8 +826,12 @@ static void amd_reset_thr_limit(unsigned int bank)
 	if (!bp || !bp[bank])
 		return;
 
-	list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj)
-		reset_block(block);
+	memset(&tr, 0, sizeof(tr));
+
+	list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) {
+		tr.b = block;
+		threshold_restart_block(&tr);
+	}
 }
 
 /*

2.51.0

Yes, and the MCA register space is predefined even if not all registers are occupied/implemented/backed by hardware.

The behavior on AMD is that an unused MSR will be Read-as-Zero (RAZ) rather than cause a #GP.

Yes, correct. We may have extra unnecessary writes. This would only happen if we find a valid error to begin with. And the error is a deferred error or a corrected error found during polling.

In effect, the register value won't be changed. The control bits will be set the same way as during initialization.

We could add another flag and try to affect the code flow. But I don't know that the overhead is worth it.

A lot of this set is trying to do away with extra overhead, duplicate code, etc.

Thanks,
Yazen

Prepare for CMCI storm support by moving the common bank/block iterator code to a helper function.

Include a parameter to switch the interrupt enable. This will be used by the CMCI storm handling function.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * New in v4.

 arch/x86/kernel/cpu/mce/amd.c | 37 +++++++++++++++++++------------------
 1 file changed, 19 insertions(+), 18 deletions(-)

index 9ca4079ff342..fbdb0cec5737 100644
@@ -471,6 +471,24 @@ static void threshold_restart_block(void *_tr)
 	wrmsr(tr->b->address, lo, hi);
 }
 
+static void threshold_restart_bank(unsigned int bank, bool intr_en)
+{
+	struct threshold_bank **thr_banks = this_cpu_read(threshold_banks);
+	struct threshold_block *block, *tmp;
+	struct thresh_restart tr;
+
+	if (!thr_banks || !thr_banks[bank])
+		return;
+
+	memset(&tr, 0, sizeof(tr));
+
+	list_for_each_entry_safe(block, tmp, &thr_banks[bank]->miscj, miscj) {
+		tr.b = block;
+		tr.b->interrupt_enable = intr_en;
+		threshold_restart_block(&tr);
+	}
+}
+
 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 {
 	struct thresh_restart tr = {

@@ -814,24 +832,7 @@ static void amd_deferred_error_interrupt(void)
 
 static void amd_reset_thr_limit(unsigned int bank)
 {
-	struct threshold_bank **bp = this_cpu_read(threshold_banks);
-	struct threshold_block *block, *tmp;
-	struct thresh_restart tr;
-
-	/*
-	 * Validate that the threshold bank has been initialized already. The
-	 * handler is installed at boot time, but on a hotplug event the
-	 * interrupt might fire before the data has been initialized.
-	 */
-	if (!bp || !bp[bank])
-		return;
-
-	memset(&tr, 0, sizeof(tr));
-
-	list_for_each_entry_safe(block, tmp, &bp[bank]->miscj, miscj) {
-		tr.b = block;
-		threshold_restart_block(&tr);
-	}
+	threshold_restart_bank(bank, true);
 }
 
 /*

2.51.0

From: Smita Koralahalli <[email protected]>

Extend the logic of handling CMCI storms to AMD threshold interrupts.

Rely on the similar approach as of Intel's CMCI to mitigate storms per CPU and per bank. But, unlike CMCI, do not set thresholds and reduce interrupt rate on a storm. Rather, disable the interrupt on the corresponding CPU and bank. Re-enable back the interrupts if enough consecutive polls of the bank show no corrected errors (30, as programmed by Intel).

Turning off the threshold interrupts would be a better solution on AMD systems as other error severities will still be handled even if the threshold interrupts are disabled.

[Tony: Small tweak because mce_handle_storm() isn't a pointer now] [Yazen: Rebase and simplify]

---

Notes:
Link:
https://lore.kernel.org/r/[email protected]

v5->v6:
* No change.

v4->v5:
* No change.

v3->v4:
* Simplify based on new patches in this set.

v2->v3:
* Add tag from Qiuxu.

v1->v2:
* New in v2, but based on older patch.
* Rebased on current set and simplified.
* Kept old tags.

 arch/x86/kernel/cpu/mce/amd.c       | 5 +++++
 arch/x86/kernel/cpu/mce/internal.h  | 2 ++
 arch/x86/kernel/cpu/mce/threshold.c | 3 +++
 3 files changed, 10 insertions(+)

index fbdb0cec5737..b895559e80ad 100644
@@ -830,6 +830,11 @@ static void amd_deferred_error_interrupt(void)
 	machine_check_poll(MCP_TIMESTAMP, &this_cpu_ptr(&mce_amd_data)->dfr_intr_banks);
 }
 
+void mce_amd_handle_storm(unsigned int bank, bool on)
+{
+	threshold_restart_bank(bank, on);
+}
+
 static void amd_reset_thr_limit(unsigned int bank)
 {
 	threshold_restart_bank(bank, true);

index b0e00ec5cc8c..9920ee5fb34c 100644
@@ -267,6 +267,7 @@ void mce_prep_record_per_cpu(unsigned int cpu, struct mce *m);
 #ifdef CONFIG_X86_MCE_AMD
 void mce_threshold_create_device(unsigned int cpu);
 void mce_threshold_remove_device(unsigned int cpu);
+void mce_amd_handle_storm(unsigned int bank, bool on);
 extern bool amd_filter_mce(struct mce *m);
 bool amd_mce_usable_address(struct mce *m);
 void amd_clear_bank(struct mce *m);

@@ -299,6 +300,7 @@ void smca_bsp_init(void);
 #else
 static inline void mce_threshold_create_device(unsigned int cpu)	{ }
 static inline void mce_threshold_remove_device(unsigned int cpu)	{ }
+static inline void mce_amd_handle_storm(unsigned int bank, bool on)	{ }
 static inline bool amd_filter_mce(struct mce *m) { return false; }
 static inline bool amd_mce_usable_address(struct mce *m) { return false; }
 static inline void amd_clear_bank(struct mce *m) { }

index f4a007616468..45144598ec74 100644
@@ -63,6 +63,9 @@ static void mce_handle_storm(unsigned int bank, bool on)
 	case X86_VENDOR_INTEL:
 		mce_intel_handle_storm(bank, on);
 		break;
+	case X86_VENDOR_AMD:
+		mce_amd_handle_storm(bank, on);
+		break;
 	}
 }
 

2.51.0

The MCA threshold limit generally is not something that needs to change during runtime. It is common for a system administrator to decide on a policy for their managed systems.

If MCA thresholding is OS-managed, then the threshold limit must be set at every boot. However, many systems allow the user to set a value in their BIOS. And this is reported through an APEI HEST entry even if thresholding is not in FW-First mode.

Use this value, if available, to set the OS-managed threshold limit. Users can still override it through sysfs if desired for testing or debug.

APEI is parsed after MCE is initialized. So reset the thresholding blocks later to pick up the threshold limit.

---

Notes:

    Link:
    https://lore.kernel.org/r/[email protected]
    
    v5->v6:
    * No change.
    
    v4->v5:
    * No change.
    
    v3->v4:
    * New in v4.

 arch/x86/include/asm/mce.h          |  6 ++++++
 arch/x86/kernel/acpi/apei.c         |  2 ++
 arch/x86/kernel/cpu/mce/amd.c       | 18 ++++++++++++++++--
 arch/x86/kernel/cpu/mce/internal.h  |  2 ++
 arch/x86/kernel/cpu/mce/threshold.c | 13 +++++++++++++
 5 files changed, 39 insertions(+), 2 deletions(-)

index 7d6588195d56..1cfbfff0be3f 100644
@@ -308,6 +308,12 @@ DECLARE_PER_CPU(struct mce, injectm);
 /* Disable CMCI/polling for MCA bank claimed by firmware */
 extern void mce_disable_bank(int bank);
 
+#ifdef CONFIG_X86_MCE_THRESHOLD
+void mce_save_apei_thr_limit(u32 thr_limit);
+#else
+static inline void mce_save_apei_thr_limit(u32 thr_limit) { }
+#endif /* CONFIG_X86_MCE_THRESHOLD */
+
 /*
  * Exception handler
  */

index 0916f00a992e..e21419e686eb 100644
@@ -19,6 +19,8 @@ int arch_apei_enable_cmcff(struct acpi_hest_header *hest_hdr, void *data)
 	if (!cmc->enabled)
 		return 0;
 
+	mce_save_apei_thr_limit(cmc->notify.error_threshold_value);
+
 	/*
 	 * We expect HEST to provide a list of MC banks that report errors
 	 * in firmware first mode. Otherwise, return non-zero value to

index b895559e80ad..9b746080351f 100644
@@ -489,6 +489,18 @@ static void threshold_restart_bank(unsigned int bank, bool intr_en)
 	}
 }
 
+/* Try to use the threshold limit reported through APEI. */
+static u16 get_thr_limit(void)
+{
+	u32 thr_limit = mce_get_apei_thr_limit();
+
+	/* Fallback to old default if APEI limit is not available. */
+	if (!thr_limit)
+		return THRESHOLD_MAX;
+
+	return min(thr_limit, THRESHOLD_MAX);
+}
+
 static void mce_threshold_block_init(struct threshold_block *b, int offset)
 {
 	struct thresh_restart tr = {

@@ -497,7 +509,7 @@ static void mce_threshold_block_init(struct threshold_block *b, int offset)
 		.lvt_off		= offset,
 	};
 
-	b->threshold_limit		= THRESHOLD_MAX;
+	b->threshold_limit		= get_thr_limit();
 	threshold_restart_block(&tr);
 };
 

@@ -1071,7 +1083,7 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
 	b->address		= address;
 	b->interrupt_enable	= 0;
 	b->interrupt_capable	= lvt_interrupt_supported(bank, high);
-	b->threshold_limit	= THRESHOLD_MAX;
+	b->threshold_limit	= get_thr_limit();
 
 	if (b->interrupt_capable) {
 		default_attrs[2] = &interrupt_enable.attr;

@@ -1082,6 +1094,8 @@ static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb
 
 	list_add(&b->miscj, &tb->miscj);
 
+	mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20);
+
 	err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
 	if (err)
 		goto out_free;

index 9920ee5fb34c..a31cf984619c 100644
@@ -67,6 +67,7 @@ void mce_track_storm(struct mce *mce);
 void mce_inherit_storm(unsigned int bank);
 bool mce_get_storm_mode(void);
 void mce_set_storm_mode(bool storm);
+u32  mce_get_apei_thr_limit(void);
 #else
 static inline void cmci_storm_begin(unsigned int bank) {}
 static inline void cmci_storm_end(unsigned int bank) {}

@@ -74,6 +75,7 @@ static inline void mce_track_storm(struct mce *mce) {}
 static inline void mce_inherit_storm(unsigned int bank) {}
 static inline bool mce_get_storm_mode(void) { return false; }
 static inline void mce_set_storm_mode(bool storm) {}
+static inline u32  mce_get_apei_thr_limit(void) { return 0; }
 #endif
 
 /*

index 45144598ec74..d00d5bf9959d 100644
@@ -13,6 +13,19 @@
 
 #include "internal.h"
 
+static u32 mce_apei_thr_limit;
+
+void mce_save_apei_thr_limit(u32 thr_limit)
+{
+	mce_apei_thr_limit = thr_limit;
+	pr_info("HEST: Corrected error threshold limit = %u\n", thr_limit);
+}
+
+u32 mce_get_apei_thr_limit(void)
+{
+	return mce_apei_thr_limit;
+}
+
 static void default_threshold_interrupt(void)
 {
 	pr_err("Unexpected threshold interrupt at vector %x\n",

2.51.0

It is necessary to apply the threshold limit to the hardware register. The MCA thresholding registers are accessed in two passes: first during per-CPU init, and second when the MCE subsystem devices are created.

The hardware registers are updated in the first pass, and they are left as-is in the second pass assuming no configuration has changed. That's why there isn't a "reset" in the second pass.

The APEI tables are parsed between the first and second passes. So now we need to update the registers during the second pass to apply the value found from HEST.

Thanks,
Yazen

So APEI is initialized as part of the subsys_initcall which is processed via:

start_kernel
rest_init
kernel_init
kernel_init_freeable
do_basic_setup
do_initcalls

And the first mce_threshold_block_init() happens from :

start_kernel
arch_cpu_finalize_init <---- way before rest_init() identify_boot_cpu
identify_cpu
mcheck_cpu_init
mcheck_cpu_init_vendor
mce_amd_feature_init prepare_threshold_block mce_threshold_block_init

Finally the per-cpu hotplug callback is installed via:

mcheck_init_device <- initiated from a device_initcall, happens after APEI subsys init. mce_cpu_online - called on every cpu from the HP machinery
mce_threshold_create_device
threshold_create_bank
allocate_threshold_blocks
mce_threshold_block_init - newly added call in alloc block, used to update the register with the new limit

Given that mce_cpu_online is already called on every online cpu at the time of installation of the callback, and every subsequent cpu that will come online I can't help but wonder why do we have to do the mce initialization from start_kernel, can't we move the mcheck_cpu_init call into mce_cpu_online, or have the latter subsume the former?

Sorry if I'm being too nitpicky, I just want to have proper understanding of the subsystem and the various (implicit) requirements it has.

At the very least I believe this commit message should at least allude to the fact that mce threshold devices have a strict requirement to be created after the APEI subsys has been created.

No worries. It is a bit convoluted. I'd like to clean this up eventually. I have an old attempt here:
https://github.com/AMDESE/linux/commit/640db92eca07804e889fac88856904552a4466bd

In general, I'd like to do the hardware and data structure init in a single pass. And the sysfs interface can be optionally added separately.

The commit message has this:

"APEI is parsed after MCE is initialized. So reset the thresholding blocks later to pick up the threshold limit."

The "devices" are already created after APEI subsys init. The missing step is updating the hardware registers.

Thanks,
Yazen

Still works fine on Intel Icelake system. Tested poison recovery, and CMCI storm handling.

-Tony

Thanks for testing!

-Yazen

On my MSI Alpha 15 (amd64) laptop running debian stable(trixie) and kernel next-20250912 I noticed the following mce error message in demsg:

[   T10] mce: [Hardware Error]: Machine check events logged
[   T10] [Hardware Error]: Corrected error, no action required.
[   T10] [Hardware Error]: CPU:0 (19:50:0) MC11_STATUS[-|CE|-|AddrV|-|-|-|UECC|-|Poison|-]: 0x8400aa4800a90139
[   T10] [Hardware Error]: Error Addr: 0x006637a200000020
[   T10] [Hardware Error]: IPID: 0x000700b040000000
[   T10] [Hardware Error]: L3 Cache Ext. Error Code: 41
[   T10] [Hardware Error]: cache level: L1, tx: GEN, mem-tx: DRD
[   T10] mce: [Hardware Error]: Machine check events logged
[   T10] [Hardware Error]: Corrected error, no action required.
[   T10] [Hardware Error]: CPU:0 (19:50:0) MC14_STATUS[-|CE|-|AddrV|PCC|-|SyndV|UECC|-|Poison|-]: 0x8724ac0800000000
[   T10] [Hardware Error]: Error Addr: 0x002bf52e00000020
[   T10] [Hardware Error]: IPID: 0x000700b040000000, Syndrome: 0x0000000000000042
[   T10] 
[   T10] [Hardware Error]: L3 Cache Ext. Error Code: 0
[   T10] [Hardware Error]: cache level: RESV, tx: INSN

The messages start about 333.34s after boot and usually appear 327.68s appart (Yes, these timings are reproducible!):

$ dmesg | grep mce
[  333.338334] [     T10] mce: [Hardware Error]: Machine check events logged
[  333.338354] [     T10] mce: [Hardware Error]: Machine check events logged
[  661.018322] [     T10] mce: [Hardware Error]: Machine check events logged
[  661.018347] [     T10] mce: [Hardware Error]: Machine check events logged
[  988.698305] [     T10] mce: [Hardware Error]: Machine check events logged
[  988.698329] [     T10] mce: [Hardware Error]: Machine check events logged
[ 1316.378283] [     T10] mce: [Hardware Error]: Machine check events logged
[ 1316.378311] [     T10] mce: [Hardware Error]: Machine check events logged
[ 1644.058284] [     T10] mce: [Hardware Error]: Machine check events logged
[ 1644.058303] [     T10] mce: [Hardware Error]: Machine check events logged

As these messages do not appear in v6.17-rc5 I bisected the issue (from v6.17-rc5 to next-20250912) and found this as the first bad commit:

cf6f155e848b ("x86/mce: Unify AMD DFR handler with MCA Polling")

Are these error messages a new error that was not reported previously or are these error messages a sign that the new code erroneously reports errors?

Hardware used:

$ lspci
00:00.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne Root Complex
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne IOMMU
00:01.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge
00:01.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe GPP Bridge
00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge
00:02.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne PCIe GPP Bridge
00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne PCIe GPP Bridge
00:02.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne PCIe GPP Bridge
00:02.4 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne PCIe GPP Bridge
00:08.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Renoir PCIe Dummy Host Bridge
00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Renoir Internal PCIe GPP Bridge to Bus
00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 51)
00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 51)
00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 0
00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 1
00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 2
00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 3
00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 4
00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 5
00:18.6 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 6
00:18.7 Host bridge: Advanced Micro Devices, Inc. [AMD] Cezanne Data Fabric; Function 7
01:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Upstream Port of PCI Express Switch (rev c3)
02:00.0 PCI bridge: Advanced Micro Devices, Inc. [AMD/ATI] Navi 10 XL Downstream Port of PCI Express Switch
03:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Navi 23 [Radeon RX 6600/6600 XT/6600M] (rev c3)
03:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Navi 21/23 HDMI/DP Audio Controller
04:00.0 Network controller: MEDIATEK Corp. MT7921K (RZ608) Wi-Fi 6E 80MHz
05:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8211/8411 PCI Express Gigabit Ethernet Controller (rev 15)
06:00.0 Non-Volatile memory controller: Kingston Technology Company, Inc. KC3000/FURY Renegade NVMe SSD [E18] (rev 01)
07:00.0 Non-Volatile memory controller: Micron/Crucial Technology P1 NVMe PCIe SSD[Frampton] (rev 03)
08:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Cezanne [Radeon Vega Series / Radeon Vega Mobile Series] (rev c5)
08:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Renoir Radeon High Definition Audio Controller
08:00.2 Encryption controller: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 10h-1fh) Platform Security Processor
08:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne USB 3.1
08:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Renoir/Cezanne USB 3.1
08:00.5 Multimedia controller: Advanced Micro Devices, Inc. [AMD] Audio Coprocessor (rev 01)
08:00.6 Audio device: Advanced Micro Devices, Inc. [AMD] Family 17h/19h/1ah HD Audio Controller
08:00.7 Signal processing controller: Advanced Micro Devices, Inc. [AMD] Sensor Fusion Hub

$ cat /proc/cpuinfo
processor	: 0
vendor_id	: AuthenticAMD
cpu family	: 25
model		: 80
model name	: AMD Ryzen 7 5800H with Radeon Graphics
stepping	: 0
microcode	: 0xa50000c
cpu MHz		: 2145.090
cache size	: 512 KB
physical id	: 0
siblings	: 16
core id		: 0
cpu cores	: 8
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 16
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm debug_swap
bugs		: sysret_ss_attrs spectre_v1 spectre_v2 spec_store_bypass srso ibpb_no_ret spectre_v2_user tsa
bogomips	: 6388.44
TLB size	: 2560 4K pages
clflush size	: 64
cache_alignment	: 64
address sizes	: 48 bits physical, 48 bits virtual
power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14]

Bert Karwatzki

The error messages are very odd. The MCA_STATUS bits are inconsistent. They show "corrected" errors with "uncorrected" bits like "PCC" and "Poison".

This is likely because the errors are found during MCA polling. The default polling interval is 300 seconds. There may be some drift if other tasks are scheduled at the same time.

You can change this interval by writing to this file:
/sys/devices/system/machinecheck/machinecheck0/check_interval

Do the messages follow that setting? IOW, if you set it to '10', do you see error messages every 10 seconds?

Could you try another recent linux-next build without the MCA updates?

It looks like 'next-20250911' doesn't include the commit above.

It could be that the recent code updates broke something. Or there may be other kernel changes causing new, spurious errors.

We could also be picking up errors from the hardware that were previously ignored. I'll ask our hardware folks if this is a case we should address.

Thanks for reporting this!

-Yazen

Am Montag, dem 15.09.2025 um 13:55 -0400 schrieb Yazen Ghannam:

Yes, if I set this to 10 I see these message every 10 seconds.

Somehow I cannot find next-20250911 in my linux-next git:

$ git checkout next-202509(TAB TAB)
next-20250901   next-20250902   next-20250905   next-20250908   next-20250912   

I'm currently re-cloning linux-next.

Perhaps these are errors which were not reported previously, when I check the L3 cache error count I get this (these error_counts seem to be persistent across reboots and also do not increase when I get an mce error message):

root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_0/l3_cache_0/error_count
0
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_1/l3_cache_1/error_count
0
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_2/l3_cache_2/error_count
9
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_3/l3_cache_3/error_count
0
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_4/l3_cache_4/error_count
72
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_5/l3_cache_5/error_count
0
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_6/l3_cache_6/error_count
3165
root@lisa:~# cat /sys/devices/system/machinecheck/machinecheck0/l3_cache_7/l3_cache_7/error_count
72

Bert Karwatzki

Am Montag, dem 15.09.2025 um 23:03 +0200 schrieb Bert Karwatzki:

After re-cloning linux-next I tested next-20250911 and I get no mce error messages even if I set the check_interval to 10.

Bert Karwatzki

Yazen, I've zapped everything from the handler unification onwards:

28e82d6f03b0 x86/mce: Save and use APEI corrected threshold limit c8f4cea38959 x86/mce: Handle AMD threshold interrupt storms 5a92e88ffc49 x86/mce/amd: Define threshold restart function for banks 922300abd79d x86/mce/amd: Remove redundant reset_block() 9b92e18973ce x86/mce/amd: Support SMCA corrected error interrupt fe02d3d00b06 x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems cf6f155e848b x86/mce: Unify AMD DFR handler with MCA Polling 53b3be0e79ef x86/mce: Unify AMD THR handler with MCA Polling

until this is properly sorted out, now this close to the merge window.

Thanks, Bert, for reporting!

Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

No problem, thanks Boris.

Bert, can you please try the following patch on next-20250912?

I expect that you will see the "debug" message, but the regular MCA logging should be gone.

Also, we haven't been able to reproduce this issue yet. So thank you for your help. It's much appreciated.

Thanks,
Yazen

From 6674a70f2369711aa28a20b88de7d89a9b6d03e0 Mon Sep 17 00:00:00 2001
From: Yazen Ghannam <[email protected]>
Date: Tue, 16 Sep 2025 09:44:24 -0400
Subject: [PATCH] x86/mce: Debug spurious MCA errors

Suspect that unexpected error information is present in MCA_DESTAT register.

Print some info for debug.

Check for the "Deferred" status bit to decide if the deferred error registers should be logged. Only deferred errors should be logged in these registers, so anything else should be ignored.

---
 arch/x86/kernel/cpu/mce/core.c | 5 +++++
 1 file changed, 5 insertions(+)

index 6e48290a3844..741473ef7fdc 100644
@@ -741,6 +741,11 @@ static bool smca_should_log_poll_error(enum mcp_flags flags, struct mce_hw_err *
 	if (!(m->status & MCI_STATUS_VAL))
 		return false;
 
+	pr_err("DEBUG: CPU%d Bank:%d Status:0x%016llx\n", m->extcpu, m->bank, m->status);
+
+	if (!(m->status & MCI_STATUS_DEFERRED))
+		return false;
+
 	m->kflags |= MCE_CHECK_DFR_REGS;
 	return true;
 }

2.51.0

Am Dienstag, dem 16.09.2025 um 10:07 -0400 schrieb Yazen Ghannam:

Applied your patch on next-20250912, these are now the only messages I get from mce:

[  333.337544] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa0800000000
[  333.337556] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[  661.017608] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413b
[  661.017619] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[  988.697243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa0800000000
[  988.697250] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724ab8800000000
[ 1316.377571] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700a28800000000
[ 1316.377582] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400aa4800a7413c

It could still be a hardware error, I'm also going to run memtest86+.

Bert Karwatzki

Am Dienstag, dem 16.09.2025 um 22:27 +0200 schrieb Bert Karwatzki:

I ran a test for 10h and got one real deferred error, I also looked through older logs (which only go back to 2025-08-17) and they do not contain any mce Hardware errors. Here's the output of

$ dmesg | grep -E "mce|Hardware Error"
[  333.338548] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[  333.338559] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[  661.018541] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa8800000000
[  661.018553] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[  988.698558] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013b
[  988.698568] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[ 1316.378440] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013b
[ 1316.378452] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[ 1644.058491] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9413b
[ 1644.058503] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[ 1971.738263] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[ 1971.738271] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 2299.418242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413a
[ 2299.418249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[ 2627.098248] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 2627.098256] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 2954.778252] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 2954.778259] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 3282.458257] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a2c800b0c155
[ 3282.458264] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400a2c800ae8156
[ 3610.139239] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a2c800b0c155
[ 3610.139244] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 3937.818244] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 3937.818251] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 4265.498243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[ 4265.498251] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400aa4800a7813b
[ 4593.178503] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 4593.178509] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 4920.858243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413a
[ 4920.858250] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a7813b
[ 5248.538455] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 5248.538462] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 5576.218247] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 5576.218255] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 5903.898266] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424ac4800a68133
[ 5903.898273] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424abc800ab814f
[ 6231.578280] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013a
[ 6231.578291] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400aa4800a7813b
[ 6559.258262] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424ac4800a34133
[ 6559.258269] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 6886.938260] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 6886.938267] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 7214.618259] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[ 7214.618265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 7542.298249] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 7542.298259] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 7869.978261] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 7869.978268] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 8197.658242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424ac4800a68133
[ 8197.658249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[ 8525.338253] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[ 8525.338263] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 8853.018261] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[ 8853.018268] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[ 9180.698246] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413a
[ 9180.698253] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a7813b
[ 9508.378244] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[ 9508.378251] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[ 9836.058240] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[ 9836.058246] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[10163.738241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[10163.738248] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700900800000000
[10163.739261] [   T9326] mce: [Hardware Error]: Machine check events logged
[10163.739265] [   T9326] [Hardware Error]: Deferred error, no action required.
[10163.739267] [   T9326] [Hardware Error]: CPU:0 (19:50:0) MC14_STATUS[-|-|-|AddrV|PCC|-|-|Deferred|-|-]: 0x8700900800000000
[10163.739275] [   T9326] [Hardware Error]: Error Addr: 0x0095464100000020
[10163.739276] [   T9326] [Hardware Error]: IPID: 0x000700b040000000
[10163.739278] [   T9326] [Hardware Error]: L3 Cache Ext. Error Code: 0
[10163.739279] [   T9326] [Hardware Error]: cache level: RESV, tx: INSN
[10491.418242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[10491.418248] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[10819.098244] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[10819.098251] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[11146.778265] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[11146.778273] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424abc800a50134
[11474.458240] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[11474.458247] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[11802.138254] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[11802.138265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400a5c800aa014b
[12129.818252] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[12129.818259] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[12457.498260] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9013a
[12457.498267] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[12785.178246] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[12785.178253] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[13112.858251] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[13112.858257] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[13440.538242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[13440.538249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[13768.218258] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[13768.218265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[14095.898258] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[14095.898265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[14423.578241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[14423.578249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424abc800a14134
[14751.258243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a8c139
[14751.258251] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a7413a
[15078.938245] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[15078.938253] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[15406.618241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[15406.618248] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400a3c800acc152
[15734.298248] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[15734.298255] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[16061.978243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[16061.978250] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[16389.658247] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[16389.658254] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[16717.338261] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[16717.338268] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[17045.018239] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[17045.018246] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[17372.698252] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a4c800adc14e
[17372.698259] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x84008ec800c80188
[17700.378422] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa0800000000
[17700.378433] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[18028.058269] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424ac4800a30134
[18028.058278] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424abc800a18135
[18355.738423] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa8800000000
[18355.738435] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[18683.418450] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa8800000000
[18683.418462] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[19011.098284] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa8800000000
[19011.098294] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[19338.778473] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa8800000000
[19338.778483] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a28800000000
[19666.458480] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724ac0800000000
[19666.458493] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a28800000000
[19994.138515] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa8800000000
[19994.138527] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[20321.818576] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[20321.818587] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a28800000000
[20649.498506] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9013c
[20649.498517] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724ab8800000000
[20977.178462] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9013c
[20977.178474] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a7413d
[21304.858526] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[21304.858538] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[21632.538259] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[21632.538270] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a28800000000
[21960.218257] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[21960.218268] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[22287.898426] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[22287.898437] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[22615.578456] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[22615.578467] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[22943.258444] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[22943.258454] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[23270.938455] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x84008dc800cc818f
[23270.938467] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[23598.618475] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[23598.618485] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[23926.298262] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9013c
[23926.298273] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[24253.978513] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[24253.978524] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724ab8800000000
[24581.658496] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa0800000000
[24581.658507] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[24909.338474] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[24909.338486] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[25237.018513] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700aa0800000000
[25237.018520] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a20800000000
[25564.698280] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[25564.698292] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[25892.378257] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[25892.378268] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[26220.058272] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13c
[26220.058279] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[26547.738258] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[26547.738265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[26875.418266] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a34135
[26875.418276] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424abc800a10136
[27203.098459] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400aa4800a9013c
[27203.098472] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[27530.778493] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[27530.778504] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[27858.458406] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[27858.458414] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724ab8800000000
[28186.138241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013b
[28186.138249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13c
[28513.818242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013b
[28513.818249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424a9c800a4013c
[28841.498247] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a5c13a
[28841.498254] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[29169.178271] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[29169.178281] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[29496.858247] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413a
[29496.858254] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[29824.538243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[29824.538256] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[30152.218241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[30152.218248] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[30479.898242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[30479.898249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[30807.578254] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[30807.578261] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8400a44800ac0150
[31135.258244] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a34800b00153
[31135.258252] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[31462.938242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[31462.938249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[31790.618243] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[31790.618250] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[32118.298254] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[32118.298261] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x84008f4800c78187
[32445.978248] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[32445.978254] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[32773.658242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a6013a
[32773.658249] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[33101.338251] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424ac4800a30132
[33101.338259] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3c13b
[33429.018251] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a58139
[33429.018262] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a3813a
[33756.698247] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a54800ad414d
[33756.698254] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8424aa4800a7813b
[34084.378241] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aa4800a9413a
[34084.378247] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724ab8800000000
[34412.058256] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8700a28800000000
[34412.058265] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[34739.738409] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8400a4c800ae4151
[34739.738421] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000
[35067.418242] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[35067.418248] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700aa0800000000
[35395.098491] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8724aa0800000000
[35395.098501] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8700a28800000000
[35722.778629] [      C0] mce: DEBUG: CPU0 Bank:11 Status:0x8424aac800a8c13b
[35722.778640] [      C0] mce: DEBUG: CPU0 Bank:14 Status:0x8724aa0800000000

Bert Karwatzki

[...]

Summary so far:
1) Errors are found on CPU0 banks 11 and 14.
2) Errors are found during MCA timer-based polling.
3) The data is coming from MCA_DESTAT register.
4) The status bits are not consistent with documentation.
5) Likely these errors are not generating a deferred error interrupt.

Bert, can you please collecting the following data?

1) Output of "/proc/interrupts".
a) The MCE, MCP, THR, and DFR lines are of interest.
b) We should verify if any other notification types occur besides "MCP" (MCA polling).

2) Using an older kernel, read the MCA_DESTAT registers for L3 cache.
a) CPU0 bank 11: "sudo rdmsr -p 0 0xC00020b8"
b) CPU0 bank 14: "sudo rdmsr -p 0 0xC00020e8"
c) If these are non-zero, then I think we can confirm that the spurious data was always there.

Thanks,
Yazen

Am Mittwoch, dem 17.09.2025 um 10:41 -0400 schrieb Yazen Ghannam:

This seems to be a real deferred errror.

This is from next-20250916 (without the debug patch), unfortunately I've already rebooted after the testrun with next-20250912 and your debug patch.

$ cat /proc/interrupts | grep -E "DFR|THR|MCE|MCP"
 THR:          0          0          0          0          0          0          0          0          0          0          0          0          0          0
0          0   Threshold APIC interrupts
 DFR:          0          0          0          0          0          0          0          0          0          0          0          0          0          0
0          0   Deferred Error APIC interrupts
 MCE:          0          0          0          0          0          0          0          0          0          0          0          0          0          0
0          0   Machine check exceptions
 MCP:         39         39         39         39         39         39         39         39         39         39         39         39         39         39
39         39   Machine check polls

This is from 6.12.43+deb13-amd64 (the stock debian trixie kernel, currently the oldest version I have installed):

# rdmsr -p 0 0xC00020b8
8700aa0800000000
# rdmsr -p 0 0xC00020e8
8700a28800000000

Bert Karwatzki

The "Deferred" status bit is set, but that seems to be coincidence. This error code shouldn't have this bit set. Likewise, in previous examples we saw the "Poison" status bit set when it shouldn't be.

Right, so it seems we have bogus data logged in these registers. And this is unrelated to the recent patches.

We have some combination of bits set in MCA_DESTAT registers. The deferred error interrupt hasn't fired (at least from the latest example).

There does seem to be some combination of bits that are always set and others flip between examples.

I'll highlight this to our hardware folks. But I don't think there's much we can do other than filter these out somehow.

I can add two checks to the patch to make it more like the current behavior.

1) Check for 'Deferred' status bit when logging from the MCA_DESTAT. This was in the debug patch I shared.
2) Only check MCA_DESTAT when we are notified by the deferred error interrupt.

Technically, both of these shouldn't be necessary based on the architecture.

So there's a third option: add this error signature to our filter_mce() function.

As I write this out, I feel more inclined to option #3. I think it would be better to stick to the architecture. We may get error reports like this. But that may be preferable so that any potential hardware issues can be investigated sooner. If there's a real problem, better to get it fixed in future products rather than implicitly mask it by our code flow.

Any thoughts from others?

Thanks,
Yazen

Bert, can you please run the following script to print all MCA registers? We'd like to see if there are any other unusual values.

Also, can you please share the complete dmesg output from any boot?

Thanks,
Yazen

#!/bin/bash

regnames=(

		"CTL"
		"STATUS"
		"ADDR"
		"MISC0"
		"CONFIG"
		"IPID"
		"SYND"
		"RESV"
		"DESTAT"
		"DEADDR"
		"MISC1"
		"MISC2"
		"MISC3"
		"MISC4"
		"SYND1"
		"SYND2"
	 )

for bank in $(seq 0 31)
do

	echo Bank ${bank}
	for reg in $(seq 0 15)
	do
		echo -n "${regnames[$reg]}:	"
		rdmsr -p 0 -c0x $(printf 0x%x $((0xC0002000 + 0x10 * bank + reg)))
	done
	echo

done

Am Mittwoch, dem 17.09.2025 um 17:15 -0400 schrieb Yazen Ghannam:

Here's the output from the script, kernel version is next-20250912 with your debugging patch.

# bash rdmsr.sh 
Bank 0
CTL:	0x0000000000ffffff
STATUS:	0x0000000000000000
ADDR:	0x0000000000000000
MISC0:	0xd01a000000000000
CONFIG:	0x00000027000001fd
IPID:	0x001000b000000000
SYND:	0x0000000000000000
RESV:	0x0000000000000000
DESTAT:	0x0000000000000000
DEADDR:	0x0000000000000000
MISC1:	0x0000000000000000
MISC2:	0x0000000000000000
MISC3:	0x0000000000000000
MISC4:	0x0000000000000000
SYND1:	0x0000000000000000
SYND2:	0x0000000000000000

Bank 1
CTL: 0x000000000007ffff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000023000001f9
IPID: 0x000100b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 2
CTL: 0x000000000000000f
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000025000001ff
IPID: 0x000200b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 3
CTL: 0x00000000000003ff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000023000001f9
IPID: 0x000300b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 4
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0000000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 5
CTL: 0x0000000000003fff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000023000001f9
IPID: 0x000500b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 6
CTL: 0x000000000000007f
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000023000001f9
IPID: 0x000600b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 7
CTL: 0x00000000000000ff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000025000001ff
IPID: 0x000700b020350000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 8
CTL: 0x00000000000000ff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x00000025000001ff
IPID: 0x000700b020350100
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 9
CTL: 0x000000000000000c
STATUS: 0x054358400005d2b0
ADDR: 0x0000000000000000
MISC0: 0x0010000900000000
CONFIG: 0x00000000000001ff
IPID: 0x000750b00005d2b0
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0050000018a0000c
DEADDR: 0x054358400005d2b0
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 10
CTL: 0x0000000000000000
STATUS: 0x0050000018a0000c
ADDR: 0x054358400005d2b0
MISC0: 0x0010000000000000
CONFIG: 0x00000029000001ff
IPID: 0x000700b018a0000c
SYND: 0x000158400005d2b0
RESV: 0x0000000000000000
DESTAT: 0x0001803100070600
DEADDR: 0x0050000018a0000c
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 11
CTL: 0x0000000000000000
STATUS: 0x0000000300070600
ADDR: 0x4f83058100208912
MISC0: 0x0010004800000000
CONFIG: 0x00000000000001ff
IPID: 0x000700b040000000
SYND: 0x0000000000000042
RESV: 0x0000000000000000
DESTAT: 0x8400a34800b04155
DEADDR: 0x009a064800000020
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 12
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x00000000000001ff
IPID: 0x000700b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0a50000c00000000
DEADDR: 0x0020891200000003
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 13
CTL: 0x0000000000000048
STATUS: 0x0000000000300000
ADDR: 0x00000000005b50a7
MISC0: 0x00100c5d00000000
CONFIG: 0x0000001500000006
IPID: 0x000700b000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 14
CTL: 0x00000000000000ff
STATUS: 0x000000030a50000c
ADDR: 0x4f83058100208912
MISC0: 0x0010004800000000
CONFIG: 0x00000000000001ff
IPID: 0x000700b040000000
SYND: 0x0000000000000042
RESV: 0x0000000000000000
DESTAT: 0x8724a98800000000
DEADDR: 0x003352dc00000020
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 15
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 16
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 17
CTL: 0x000000000000003f
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000001000000
CONFIG: 0x000000270000007d
IPID: 0x0000009600050f00
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0xd01a000001000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 18
CTL: 0x000000000000003f
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000001000000
CONFIG: 0x000000270000007d
IPID: 0x0000009600150f00
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0xd01a000001000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 19
CTL: 0x0000000000003fff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x000000250000007f
IPID: 0x0002002e00000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 20
CTL: 0x0000000000003fff
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x000000250000007f
IPID: 0x0002002e00000001
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 21
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 22
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 23
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 24
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 25
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 26
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0010000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 27
CTL: 0x000000000000001f
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0xd01a000000000000
CONFIG: 0x000000270000007d
IPID: 0x0001002e0000000b
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0010000000000000
MISC2: 0x0010000000000000
MISC3: 0x0010000000000000
MISC4: 0x0010000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 28
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0000000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 29
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0000000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 30
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0000000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Bank 31
CTL: 0x0000000000000000
STATUS: 0x0000000000000000
ADDR: 0x0000000000000000
MISC0: 0x0000000000000000
CONFIG: 0x0000000000000000
IPID: 0x0000000000000000
SYND: 0x0000000000000000
RESV: 0x0000000000000000
DESTAT: 0x0000000000000000
DEADDR: 0x0000000000000000
MISC1: 0x0000000000000000
MISC2: 0x0000000000000000
MISC3: 0x0000000000000000
MISC4: 0x0000000000000000
SYND1: 0x0000000000000000
SYND2: 0x0000000000000000

Here's the dmesg from next-20250912 with your debugging patch:

[    0.000000] [      T0] Linux version 6.17.0-rc5-next-20250912-master-00001-g68697fae2855 (bert@lisa) (gcc (Debian 14.2.0-19) 14.2.0, GNU ld (GNU Binutils for
Debian) 2.44) #2 SMP PREEMPT_RT Tue Sep 16 21:53:59 CEST 2025
[    0.000000] [      T0] Command line: BOOT_IMAGE=/boot/vmlinuz-6.17.0-rc5-next-20250912-master-00001-g68697fae2855 root=UUID=73e0f015-c115-4eb2-92cb-
dbf7da2b6112 ro clocksource=hpet amdgpu.noretry=0 tsc=unstable log_buf_len=1073741824 acpi.debug_layer=0xf acpi.debug_level=0x307
[    0.000000] [      T0] KERNEL supported cpus:
[    0.000000] [      T0]   AMD AuthenticAMD
[    0.000000] [      T0] BIOS-provided physical RAM map:
[    0.000000] [      T0] BIOS-e820: [mem 0x0000000000000000-0x000000000009ffff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x0000000000100000-0x0000000009bfefff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x0000000009bff000-0x000000000a000fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x000000000a001000-0x000000000a1fffff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x000000000a200000-0x000000000a20efff] ACPI NVS
[    0.000000] [      T0] BIOS-e820: [mem 0x000000000a20f000-0x00000000e9cdefff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000e9cdf000-0x00000000eb1fdfff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000eb1fe000-0x00000000eb25dfff] ACPI data
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000eb25e000-0x00000000eb555fff] ACPI NVS
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000eb556000-0x00000000ed1fefff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000ed1ff000-0x00000000edffffff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000ee000000-0x00000000f7ffffff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fd000000-0x00000000fdffffff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000feb80000-0x00000000fec01fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fec10000-0x00000000fec10fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed00fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fed40000-0x00000000fed44fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fed80000-0x00000000fed8ffff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fedc4000-0x00000000fedc9fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fedcc000-0x00000000fedcefff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000fedd5000-0x00000000fedd5fff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[    0.000000] [      T0] BIOS-e820: [mem 0x0000000100000000-0x00000003ee2fffff] usable
[    0.000000] [      T0] BIOS-e820: [mem 0x00000003ee300000-0x000000040fffffff] reserved
[    0.000000] [      T0] NX (Execute Disable) protection: active
[    0.000000] [      T0] APIC: Static calls initialized
[    0.000000] [      T0] efi: EFI v2.7 by American Megatrends
[    0.000000] [      T0] efi: ACPI=0xeb53f000 ACPI 2.0=0xeb53f014 TPMFinalLog=0xeb50b000 SMBIOS=0xed01f000 SMBIOS 3.0=0xed01e000 MEMATTR=0xe61a7818
ESRT=0xe868b998 INITRD=0xe619d118 RNG=0xeb210018 TPMEventLog=0xeb20b018 
[    0.000000] [      T0] random: crng init done
[    0.000000] [      T0] efi: Remove mem50: MMIO range=[0xf0000000-0xf7ffffff] (128MB) from e820 map
[    0.000000] [      T0] e820: remove [mem 0xf0000000-0xf7ffffff] reserved
[    0.000000] [      T0] efi: Remove mem51: MMIO range=[0xfd000000-0xfdffffff] (16MB) from e820 map
[    0.000000] [      T0] e820: remove [mem 0xfd000000-0xfdffffff] reserved
[    0.000000] [      T0] efi: Remove mem52: MMIO range=[0xfeb80000-0xfec01fff] (0MB) from e820 map
[    0.000000] [      T0] e820: remove [mem 0xfeb80000-0xfec01fff] reserved
[    0.000000] [      T0] efi: Not removing mem53: MMIO range=[0xfec10000-0xfec10fff] (4KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem54: MMIO range=[0xfed00000-0xfed00fff] (4KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem55: MMIO range=[0xfed40000-0xfed44fff] (20KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem56: MMIO range=[0xfed80000-0xfed8ffff] (64KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem57: MMIO range=[0xfedc4000-0xfedc9fff] (24KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem58: MMIO range=[0xfedcc000-0xfedcefff] (12KB) from e820 map
[    0.000000] [      T0] efi: Not removing mem59: MMIO range=[0xfedd5000-0xfedd5fff] (4KB) from e820 map
[    0.000000] [      T0] efi: Remove mem60: MMIO range=[0xff000000-0xffffffff] (16MB) from e820 map
[    0.000000] [      T0] e820: remove [mem 0xff000000-0xffffffff] reserved
[    0.000000] [      T0] SMBIOS 3.3.0 present.
[    0.000000] [      T0] DMI: Micro-Star International Co., Ltd. Alpha 15 B5EEK/MS-158L, BIOS E158LAMS.10F 11/11/2024
[    0.000000] [      T0] DMI: Memory slots populated: 2/2
[    0.000000] [      T0] tsc: Fast TSC calibration using PIT
[    0.000000] [      T0] tsc: Detected 3194.225 MHz processor
[    0.000127] [      T0] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[    0.000129] [      T0] e820: remove [mem 0x000a0000-0x000fffff] usable
[    0.000134] [      T0] last_pfn = 0x3ee300 max_arch_pfn = 0x400000000
[    0.000138] [      T0] MTRR map: 5 entries (3 fixed + 2 variable; max 20), built from 9 variable MTRRs
[    0.000140] [      T0] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[    0.000226] [      T0] e820: update [mem 0xf0000000-0xffffffff] usable ==> reserved
[    0.000230] [      T0] last_pfn = 0xee000 max_arch_pfn = 0x400000000
[    0.000237] [      T0] esrt: Reserving ESRT space from 0x00000000e868b998 to 0x00000000e868b9d0.
[    0.000241] [      T0] e820: update [mem 0xe868b000-0xe868bfff] usable ==> reserved
[    0.000251] [      T0] Using GB pages for direct mapping
[    0.536952] [      T0] printk: log buffer data + meta data: 1073741824 + 3758096384 = 4831838208 bytes
[    0.536954] [      T0] printk: early log buf free: 126144(96%)
[    0.536955] [      T0] Secure boot disabled
[    0.536955] [      T0] RAMDISK: [mem 0xdc3ad000-0xdeb2afff]
[    0.536994] [      T0] ACPI: Early table checksum verification disabled
[    0.536997] [      T0] ACPI: RSDP 0x00000000EB53F014 000024 (v02 MSI_NB)
[    0.537000] [      T0] ACPI: XSDT 0x00000000EB53E728 000114 (v01 MSI_NB MEGABOOK 01072009 AMI  01000013)
[    0.537003] [      T0] ACPI: FACP 0x00000000EB24F000 000114 (v06 MSI_NB MEGABOOK 01072009 AMI  00010013)
[    0.537006] [      T0] ACPI: DSDT 0x00000000EB242000 00C6FB (v02 MSI_NB MEGABOOK 01072009 INTL 20190509)
[    0.537008] [      T0] ACPI: FACS 0x00000000EB509000 000040
[    0.537009] [      T0] ACPI: SLIC 0x00000000EB25D000 000176 (v01 MSI_NB MEGABOOK 01072009 AMI  01000013)
[    0.537010] [      T0] ACPI: SSDT 0x00000000EB255000 0072B0 (v02 AMD    AmdTable 00000002 MSFT 04000000)
[    0.537011] [      T0] ACPI: IVRS 0x00000000EB254000 0001A4 (v02 AMD    AmdTable 00000001 AMD  00000000)
[    0.537012] [      T0] ACPI: SSDT 0x00000000EB250000 003A21 (v01 AMD    AMD AOD  00000001 INTL 20190509)
[    0.537014] [      T0] ACPI: FIDT 0x00000000EB241000 00009C (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
[    0.537015] [      T0] ACPI: ECDT 0x00000000EB240000 0000C1 (v01 MSI_NB MEGABOOK 01072009 AMI. 00010013)
[    0.537016] [      T0] ACPI: MCFG 0x00000000EB23F000 00003C (v01 MSI_NB MEGABOOK 01072009 MSFT 00010013)
[    0.537017] [      T0] ACPI: HPET 0x00000000EB23E000 000038 (v01 MSI_NB MEGABOOK 01072009 AMI  00000005)
[    0.537018] [      T0] ACPI: VFCT 0x00000000EB230000 00D884 (v01 MSI_NB MEGABOOK 00000001 AMD  31504F47)
[    0.537019] [      T0] ACPI: BGRT 0x00000000EB22F000 000038 (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
[    0.537021] [      T0] ACPI: TPM2 0x00000000EB22E000 00004C (v04 MSI_NB MEGABOOK 00000001 AMI  00000000)
[    0.537022] [      T0] ACPI: SSDT 0x00000000EB228000 005354 (v02 AMD    AmdTable 00000001 AMD  00000001)
[    0.537023] [      T0] ACPI: CRAT 0x00000000EB227000 000EE8 (v01 AMD    AmdTable 00000001 AMD  00000001)
[    0.537024] [      T0] ACPI: CDIT 0x00000000EB226000 000029 (v01 AMD    AmdTable 00000001 AMD  00000001)
[    0.537025] [      T0] ACPI: SSDT 0x00000000EB225000 000149 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537026] [      T0] ACPI: SSDT 0x00000000EB223000 00148E (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537028] [      T0] ACPI: SSDT 0x00000000EB221000 00153F (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537029] [      T0] ACPI: SSDT 0x00000000EB220000 000696 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537030] [      T0] ACPI: SSDT 0x00000000EB21E000 001A56 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537031] [      T0] ACPI: SSDT 0x00000000EB21D000 0005DE (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537032] [      T0] ACPI: SSDT 0x00000000EB219000 0036E9 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537033] [      T0] ACPI: WSMT 0x00000000EB218000 000028 (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
[    0.537034] [      T0] ACPI: APIC 0x00000000EB217000 0000DE (v03 MSI_NB MEGABOOK 01072009 AMI  00010013)
[    0.537035] [      T0] ACPI: SSDT 0x00000000EB216000 00008D (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537036] [      T0] ACPI: SSDT 0x00000000EB215000 0008A8 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537037] [      T0] ACPI: SSDT 0x00000000EB214000 0001B7 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537038] [      T0] ACPI: SSDT 0x00000000EB213000 0007B1 (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537039] [      T0] ACPI: SSDT 0x00000000EB212000 00097D (v01 AMD    AmdTable 00000001 INTL 20190509)
[    0.537041] [      T0] ACPI: FPDT 0x00000000EB211000 000044 (v01 MSI_NB MEGABOOK 01072009 AMI  01000013)
[    0.537042] [      T0] ACPI: Reserving FACP table memory at [mem 0xeb24f000-0xeb24f113]
[    0.537043] [      T0] ACPI: Reserving DSDT table memory at [mem 0xeb242000-0xeb24e6fa]
[    0.537043] [      T0] ACPI: Reserving FACS table memory at [mem 0xeb509000-0xeb50903f]
[    0.537044] [      T0] ACPI: Reserving SLIC table memory at [mem 0xeb25d000-0xeb25d175]
[    0.537044] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb255000-0xeb25c2af]
[    0.537044] [      T0] ACPI: Reserving IVRS table memory at [mem 0xeb254000-0xeb2541a3]
[    0.537045] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb250000-0xeb253a20]
[    0.537045] [      T0] ACPI: Reserving FIDT table memory at [mem 0xeb241000-0xeb24109b]
[    0.537045] [      T0] ACPI: Reserving ECDT table memory at [mem 0xeb240000-0xeb2400c0]
[    0.537046] [      T0] ACPI: Reserving MCFG table memory at [mem 0xeb23f000-0xeb23f03b]
[    0.537046] [      T0] ACPI: Reserving HPET table memory at [mem 0xeb23e000-0xeb23e037]
[    0.537046] [      T0] ACPI: Reserving VFCT table memory at [mem 0xeb230000-0xeb23d883]
[    0.537047] [      T0] ACPI: Reserving BGRT table memory at [mem 0xeb22f000-0xeb22f037]
[    0.537047] [      T0] ACPI: Reserving TPM2 table memory at [mem 0xeb22e000-0xeb22e04b]
[    0.537047] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb228000-0xeb22d353]
[    0.537048] [      T0] ACPI: Reserving CRAT table memory at [mem 0xeb227000-0xeb227ee7]
[    0.537048] [      T0] ACPI: Reserving CDIT table memory at [mem 0xeb226000-0xeb226028]
[    0.537048] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb225000-0xeb225148]
[    0.537049] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb223000-0xeb22448d]
[    0.537049] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb221000-0xeb22253e]
[    0.537049] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb220000-0xeb220695]
[    0.537050] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb21e000-0xeb21fa55]
[    0.537050] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb21d000-0xeb21d5dd]
[    0.537051] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb219000-0xeb21c6e8]
[    0.537051] [      T0] ACPI: Reserving WSMT table memory at [mem 0xeb218000-0xeb218027]
[    0.537051] [      T0] ACPI: Reserving APIC table memory at [mem 0xeb217000-0xeb2170dd]
[    0.537052] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb216000-0xeb21608c]
[    0.537052] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb215000-0xeb2158a7]
[    0.537052] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb214000-0xeb2141b6]
[    0.537053] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb213000-0xeb2137b0]
[    0.537053] [      T0] ACPI: Reserving SSDT table memory at [mem 0xeb212000-0xeb21297c]
[    0.537053] [      T0] ACPI: Reserving FPDT table memory at [mem 0xeb211000-0xeb211043]
[    0.537088] [      T0] Zone ranges:
[    0.537089] [      T0]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
[    0.537090] [      T0]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
[    0.537090] [      T0]   Normal   [mem 0x0000000100000000-0x00000003ee2fffff]
[    0.537091] [      T0] Movable zone start for each node
[    0.537092] [      T0] Early memory node ranges
[    0.537092] [      T0]   node   0: [mem 0x0000000000001000-0x000000000009ffff]
[    0.537093] [      T0]   node   0: [mem 0x0000000000100000-0x0000000009bfefff]
[    0.537093] [      T0]   node   0: [mem 0x000000000a001000-0x000000000a1fffff]
[    0.537094] [      T0]   node   0: [mem 0x000000000a20f000-0x00000000e9cdefff]
[    0.537094] [      T0]   node   0: [mem 0x00000000ed1ff000-0x00000000edffffff]
[    0.537094] [      T0]   node   0: [mem 0x0000000100000000-0x00000003ee2fffff]
[    0.537096] [      T0] Initmem setup node 0 [mem 0x0000000000001000-0x00000003ee2fffff]
[    0.537100] [      T0] On node 0, zone DMA: 1 pages in unavailable ranges
[    0.537122] [      T0] On node 0, zone DMA: 96 pages in unavailable ranges
[    0.537317] [      T0] On node 0, zone DMA32: 1026 pages in unavailable ranges
[    0.542073] [      T0] On node 0, zone DMA32: 15 pages in unavailable ranges
[    0.542162] [      T0] On node 0, zone DMA32: 13600 pages in unavailable ranges
[    0.542374] [      T0] On node 0, zone Normal: 8192 pages in unavailable ranges
[    0.542408] [      T0] On node 0, zone Normal: 7424 pages in unavailable ranges
[    0.543115] [      T0] ACPI: PM-Timer IO Port: 0x808
[    0.543121] [      T0] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
[    0.543131] [      T0] IOAPIC[0]: apic_id 33, version 33, address 0xfec00000, GSI 0-23
[    0.543136] [      T0] IOAPIC[1]: apic_id 34, version 33, address 0xfec01000, GSI 24-55
[    0.543137] [      T0] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.543138] [      T0] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
[    0.543140] [      T0] ACPI: Using ACPI (MADT) for SMP configuration information
[    0.543141] [      T0] ACPI: HPET id: 0x10228201 base: 0xfed00000
[    0.543147] [      T0] e820: update [mem 0xe6058000-0xe614bfff] usable ==> reserved
[    0.543158] [      T0] CPU topo: Max. logical packages:   1
[    0.543159] [      T0] CPU topo: Max. logical dies:       1
[    0.543159] [      T0] CPU topo: Max. dies per package:   1
[    0.543161] [      T0] CPU topo: Max. threads per core:   2
[    0.543162] [      T0] CPU topo: Num. cores per package:     8
[    0.543162] [      T0] CPU topo: Num. threads per package:  16
[    0.543162] [      T0] CPU topo: Allowing 16 present CPUs plus 0 hotplug CPUs
[    0.543175] [      T0] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[    0.543176] [      T0] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000fffff]
[    0.543177] [      T0] PM: hibernation: Registered nosave memory: [mem 0x09bff000-0x0a000fff]
[    0.543178] [      T0] PM: hibernation: Registered nosave memory: [mem 0x0a200000-0x0a20efff]
[    0.543179] [      T0] PM: hibernation: Registered nosave memory: [mem 0xe6058000-0xe614bfff]
[    0.543180] [      T0] PM: hibernation: Registered nosave memory: [mem 0xe868b000-0xe868bfff]
[    0.543181] [      T0] PM: hibernation: Registered nosave memory: [mem 0xe9cdf000-0xed1fefff]
[    0.543181] [      T0] PM: hibernation: Registered nosave memory: [mem 0xee000000-0xffffffff]
[    0.543183] [      T0] [mem 0xf0000000-0xfec0ffff] available for PCI devices
[    0.543184] [      T0] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
[    0.545436] [      T0] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:16 nr_node_ids:1
[    0.545777] [      T0] percpu: Embedded 44 pages/cpu s142704 r8192 d29328 u262144
[    0.545780] [      T0] pcpu-alloc: s142704 r8192 d29328 u262144 alloc=1*2097152
[    0.545782] [      T0] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 12 13 14 15 
[    0.545793] [      T0] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-6.17.0-rc5-next-20250912-master-00001-g68697fae2855 root=UUID=73e0f015-c115-4eb2-92cb-
dbf7da2b6112 ro clocksource=hpet amdgpu.noretry=0 tsc=unstable log_buf_len=1073741824 acpi.debug_layer=0xf acpi.debug_level=0x307
[    0.545819] [      T0] tsc: Marking TSC unstable due to boot parameter
[    0.546932] [      T0] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[    0.547506] [      T0] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
[    0.547602] [      T0] software IO TLB: area num 16.
[    0.556369] [      T0] Built 1 zonelists, mobility grouping on.  Total pages: 4032878
[    0.556372] [      T0] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.568323] [      T0] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=16, Nodes=1
[    0.568381] [      T0] Dynamic Preempt: full
[    0.568431] [      T0] rcu: Preemptible hierarchical RCU implementation.
[    0.568432] [      T0] rcu: 	RCU priority boosting: priority 1 delay 500 ms.
[    0.568433] [      T0] rcu: 	RCU_SOFTIRQ processing moved to rcuc kthreads.
[    0.568433] [      T0] 	No expedited grace period (rcu_normal_after_boot).
[    0.568434] [      T0] 	Trampoline variant of Tasks RCU enabled.
[    0.568434] [      T0] 	Tracing variant of Tasks RCU enabled.
[    0.568435] [      T0] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
[    0.568445] [      T0] RCU Tasks: Setting shift to 4 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=16.
[    0.568446] [      T0] RCU Tasks Trace: Setting shift to 4 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=16.
[    0.568453] [      T0] NR_IRQS: 4352, nr_irqs: 1096, preallocated irqs: 16
[    0.568638] [      T0] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.568710] [      T0] Console: colour dummy device 80x25
[    0.568712] [      T0] printk: legacy console [tty0] enabled
[    0.568719] [      T0] ACPI: Core revision 20250404
[    0.568862] [      T0] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484873504 ns
[    0.568880] [      T0] APIC: Switch to symmetric I/O mode setup
[    0.569275] [      T0] AMD-Vi: ivrs, add hid:AMDI0020, uid:\_SB.FUR0, rdevid:0xa0
[    0.569276] [      T0] AMD-Vi: ivrs, add hid:AMDI0020, uid:\_SB.FUR1, rdevid:0xa0
[    0.569276] [      T0] AMD-Vi: ivrs, add hid:AMDI0020, uid:\_SB.FUR2, rdevid:0xa0
[    0.569277] [      T0] AMD-Vi: ivrs, add hid:AMDI0020, uid:\_SB.FUR3, rdevid:0xa0
[    0.569277] [      T0] AMD-Vi: Using global IVHD EFR:0x206d73ef22254ade, EFR2:0x0
[    0.569544] [      T0] x2apic enabled
[    0.569585] [      T0] APIC: Switched APIC routing to: cluster x2apic
[    0.570193] [      T0] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.574885] [      T0] Calibrating delay loop (skipped), value calculated using timer frequency.. 6388.45 BogoMIPS (lpj=3194225)
[    0.574899] [      T0] x86/cpu: User Mode Instruction Prevention (UMIP) activated
[    0.574910] [      T0] LVT offset 1 assigned for vector 0xf9
[    0.574911] [      T0] LVT offset 2 assigned for vector 0xf4
[    0.574982] [      T0] Last level iTLB entries: 4KB 512, 2MB 512, 4MB 256
[    0.574983] [      T0] Last level dTLB entries: 4KB 2048, 2MB 2048, 4MB 1024, 1GB 0
[    0.574985] [      T0] process: using mwait in idle threads
[    0.574986] [      T0] mitigations: Enabled attack vectors: user_kernel, user_user, SMT mitigations: auto
[    0.574989] [      T0] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl
[    0.574989] [      T0] Speculative Return Stack Overflow: IBPB-extending microcode not applied!
[    0.574990] [      T0] Speculative Return Stack Overflow: WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation
options.
[    0.574990] [      T0] Transient Scheduler Attacks: Vulnerable: No microcode
[    0.574990] [      T0] Spectre V2 : Mitigation: Retpolines
[    0.574991] [      T0] Spectre V2 : User space: Mitigation: STIBP always-on protection
[    0.574991] [      T0] Speculative Return Stack Overflow: Vulnerable: Safe RET, no microcode
[    0.574992] [      T0] VMSCAPE: Vulnerable
[    0.574992] [      T0] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[    0.574992] [      T0] Spectre V2 : Spectre v2 / SpectreRSB: Filling RSB on context switch and VMEXIT
[    0.574993] [      T0] Spectre V2 : Enabling Restricted Speculation for firmware calls
[    0.574993] [      T0] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier
[    0.574994] [      T0] active return thunk: srso_alias_return_thunk
[    0.575000] [      T0] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[    0.575001] [      T0] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[    0.575002] [      T0] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[    0.575002] [      T0] x86/fpu: Supporting XSAVE feature 0x200: 'Protection Keys User registers'
[    0.575002] [      T0] x86/fpu: Supporting XSAVE feature 0x800: 'Control-flow User registers'
[    0.575003] [      T0] x86/fpu: Supporting XSAVE feature 0x1000: 'Control-flow Kernel registers (KVM only)'
[    0.575004] [      T0] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[    0.575005] [      T0] x86/fpu: xstate_offset[9]:  832, xstate_sizes[9]:    8
[    0.575005] [      T0] x86/fpu: xstate_offset[11]:  840, xstate_sizes[11]:   16
[    0.575005] [      T0] x86/fpu: xstate_offset[12]:  856, xstate_sizes[12]:   24
[    0.575006] [      T0] x86/fpu: Enabled xstate features 0x1a07, context size is 880 bytes, using 'compacted' format.
[    0.590770] [      T0] Freeing SMP alternatives memory: 36K
[    0.590772] [      T0] pid_max: default: 32768 minimum: 301
[    0.590842] [      T0] LSM: initializing lsm=capability,apparmor
[    0.590942] [      T0] AppArmor: AppArmor initialized
[    0.590990] [      T0] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.591007] [      T0] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[    0.694935] [      T1] smpboot: CPU0: AMD Ryzen 7 5800H with Radeon Graphics (family: 0x19, model: 0x50, stepping: 0x0)
[    0.695133] [      T1] Performance Events: Fam17h+ core perfctr, AMD PMU driver.
[    0.695137] [      T1] ... version:                   0
[    0.695138] [      T1] ... bit width:                 48
[    0.695139] [      T1] ... generic counters:          6
[    0.695139] [      T1] ... generic bitmap:            000000000000003f
[    0.695140] [      T1] ... fixed-purpose counters:    0
[    0.695141] [      T1] ... fixed-purpose bitmap:      0000000000000000
[    0.695141] [      T1] ... value mask:                0000ffffffffffff
[    0.695142] [      T1] ... max period:                00007fffffffffff
[    0.695142] [      T1] ... global_ctrl mask:          000000000000003f
[    0.695218] [      T1] signal: max sigframe size: 3376
[    0.695928] [      T1] rcu: Hierarchical SRCU implementation.
[    0.695929] [      T1] rcu: 	Max phase no-delay instances is 400.
[    0.696008] [      T1] Timer migration: 2 hierarchy levels; 8 children per group; 2 crossnode level
[    0.697333] [      T1] MCE: In-kernel MCE decoding enabled.
[    0.697353] [     T10] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter.
[    0.697521] [      T1] smp: Bringing up secondary CPUs ...
[    0.697673] [      T1] smpboot: x86: Booting SMP configuration:
[    0.697674] [      T1] .... node  #0, CPUs:        #2  #4  #6  #8 #10 #12 #14  #1  #3  #5  #7  #9 #11 #13 #15
[    0.702525] [      T1] Spectre V2 : Update user space SMT mitigation: STIBP always-on
[    0.702927] [      T1] smp: Brought up 1 node, 16 CPUs
[    0.702927] [      T1] smpboot: Total of 16 processors activated (102215.20 BogoMIPS)
[    0.712898] [    T145] node 0 deferred pages initialised in 9ms
[    0.712908] [      T1] Memory: 10985032K/16131512K available (11691K kernel code, 1087K rwdata, 4084K rodata, 1400K init, 2096K bss, 5133172K reserved, 0K
cma-reserved)
[    0.713109] [      T1] devtmpfs: initialized
[    0.714133] [      T1] ACPI: PM: Registering ACPI NVS region [mem 0x0a200000-0x0a20efff] (61440 bytes)
[    0.714133] [      T1] ACPI: PM: Registering ACPI NVS region [mem 0xeb25e000-0xeb555fff] (3112960 bytes)
[    0.714133] [      T1] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
[    0.714133] [      T1] posixtimers hash table entries: 8192 (order: 6, 327680 bytes, linear)
[    0.714133] [      T1] futex hash table entries: 4096 (262144 bytes on 1 NUMA nodes, total 256 KiB, linear).
[    0.714133] [      T1] pinctrl core: initialized pinctrl subsystem
[    0.714975] [      T1] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.715182] [      T1] audit: initializing netlink subsys (disabled)
[    0.715189] [    T165] audit: type=2000 audit(1758146029.145:1): state=initialized audit_enabled=0 res=1
[    0.715189] [      T1] thermal_sys: Registered thermal governor 'fair_share'
[    0.715189] [      T1] thermal_sys: Registered thermal governor 'bang_bang'
[    0.715189] [      T1] thermal_sys: Registered thermal governor 'step_wise'
[    0.715189] [      T1] thermal_sys: Registered thermal governor 'user_space'
[    0.715189] [      T1] thermal_sys: Registered thermal governor 'power_allocator'
[    0.715189] [      T1] cpuidle: using governor ladder
[    0.715189] [      T1] cpuidle: using governor menu
[    0.715189] [      T1] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[    0.715189] [      T1] PCI: ECAM [mem 0xf0000000-0xf7ffffff] (base 0xf0000000) for domain 0000 [bus 00-7f]
[    0.715189] [      T1] PCI: Using configuration type 1 for base access
[    0.715969] [      T1] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.715969] [      T1] HugeTLB: 16380 KiB vmemmap can be freed for a 1.00 GiB page
[    0.715969] [      T1] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.715969] [      T1] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page
[    0.716270] [      T1] ACPI: Added _OSI(Module Device)
[    0.716271] [      T1] ACPI: Added _OSI(Processor Device)
[    0.716272] [      T1] ACPI: Added _OSI(Processor Aggregator Device)
[    0.739363] [      T1] ACPI: 16 ACPI AML tables successfully acquired and loaded
[    0.740922] [      T1] ACPI: EC: EC started
[    0.740923] [      T1] ACPI: EC: interrupt blocked
[    0.741517] [      T1] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
[    0.741518] [      T1] ACPI: EC: Boot ECDT EC used to handle transactions
[    0.742487] [      T1] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
[    0.746056] [      T1] ACPI: Interpreter enabled
[    0.746073] [      T1] ACPI: PM: (supports S0 S4 S5)
[    0.746074] [      T1] ACPI: Using IOAPIC for interrupt routing
[    0.746329] [      T1] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.746330] [      T1] PCI: Ignoring E820 reservations for host bridge windows
[    0.746970] [      T1] ACPI: Enabled 1 GPEs in block 00 to 1F
[    0.747952] [      T1] ACPI: \_SB_.PCI0.GPP0.M237: New power resource
[    0.748214] [      T1] ACPI: \_SB_.PCI0.GPP0.SWUS.M237: New power resource
[    0.748353] [      T1] ACPI: \_SB_.PCI0.GPP0.SWUS.SWDS.M237: New power resource
[    0.750078] [      T1] ACPI: \_SB_.PCI0.GP17.XHC0.P0U0: New power resource
[    0.750123] [      T1] ACPI: \_SB_.PCI0.GP17.XHC0.P3U0: New power resource
[    0.751024] [      T1] ACPI: \_SB_.PCI0.GP17.XHC1.P0U1: New power resource
[    0.751068] [      T1] ACPI: \_SB_.PCI0.GP17.XHC1.P3U1: New power resource
[    0.753869] [      T1] ACPI: \_SB_.PCI0.GPP6.P0NV: New power resource
[    0.754178] [      T1] ACPI: \_SB_.PCI0.GPP5.P0NX: New power resource
[    0.763849] [      T1] ACPI: \_SB_.PRWB: New power resource
[    0.766645] [      T1] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.766650] [      T1] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI EDR HPX-Type3]
[    0.766759] [      T1] acpi PNP0A08:00: _OSC: platform does not support [LTR DPC]
[    0.766966] [      T1] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
[    0.766968] [      T1] acpi PNP0A08:00: [Firmware Info]: ECAM [mem 0xf0000000-0xf7ffffff] for domain 0000 [bus 00-7f] only partially covers this bridge
[    0.767584] [      T1] PCI host bridge to bus 0000:00
[    0.767588] [      T1] pci_bus 0000:00: root bus resource [io  0x0000-0x03af window]
[    0.767590] [      T1] pci_bus 0000:00: root bus resource [io  0x03e0-0x0cf7 window]
[    0.767592] [      T1] pci_bus 0000:00: root bus resource [io  0x03b0-0x03df window]
[    0.767593] [      T1] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
[    0.767594] [      T1] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000dffff window]
[    0.767596] [      T1] pci_bus 0000:00: root bus resource [mem 0xf0000000-0xfcffffff window]
[    0.767597] [      T1] pci_bus 0000:00: root bus resource [mem 0x410000000-0xffffffffff window]
[    0.767598] [      T1] pci_bus 0000:00: root bus resource [bus 00-ff]
[    0.767616] [      T1] pci 0000:00:00.0: [1022:1630] type 00 class 0x060000 conventional PCI endpoint
[    0.767763] [      T1] pci 0000:00:00.2: [1022:1631] type 00 class 0x080600 conventional PCI endpoint
[    0.767916] [      T1] pci 0000:00:01.0: [1022:1632] type 00 class 0x060000 conventional PCI endpoint
[    0.768042] [      T1] pci 0000:00:01.1: [1022:1633] type 01 class 0x060400 PCIe Root Port
[    0.768054] [      T1] pci 0000:00:01.1: PCI bridge to [bus 01-03]
[    0.768059] [      T1] pci 0000:00:01.1:   bridge window [mem 0xfca00000-0xfccfffff]
[    0.768065] [      T1] pci 0000:00:01.1:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.768107] [      T1] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[    0.768276] [      T1] pci 0000:00:02.0: [1022:1632] type 00 class 0x060000 conventional PCI endpoint
[    0.768399] [      T1] pci 0000:00:02.1: [1022:1634] type 01 class 0x060400 PCIe Root Port
[    0.768412] [      T1] pci 0000:00:02.1: PCI bridge to [bus 04]
[    0.768421] [      T1] pci 0000:00:02.1:   bridge window [mem 0xfe30300000-0xfe304fffff 64bit pref]
[    0.768461] [      T1] pci 0000:00:02.1: PME# supported from D0 D3hot D3cold
[    0.768596] [      T1] pci 0000:00:02.2: [1022:1634] type 01 class 0x060400 PCIe Root Port
[    0.768610] [      T1] pci 0000:00:02.2: PCI bridge to [bus 05]
[    0.768614] [      T1] pci 0000:00:02.2:   bridge window [io  0xf000-0xffff]
[    0.768616] [      T1] pci 0000:00:02.2:   bridge window [mem 0xfcf00000-0xfcffffff]
[    0.768627] [      T1] pci 0000:00:02.2: enabling Extended Tags
[    0.768662] [      T1] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[    0.768799] [      T1] pci 0000:00:02.3: [1022:1634] type 01 class 0x060400 PCIe Root Port
[    0.768812] [      T1] pci 0000:00:02.3: PCI bridge to [bus 06]
[    0.768816] [      T1] pci 0000:00:02.3:   bridge window [mem 0xfce00000-0xfcefffff]
[    0.768859] [      T1] pci 0000:00:02.3: PME# supported from D0 D3hot D3cold
[    0.769009] [      T1] pci 0000:00:02.4: [1022:1634] type 01 class 0x060400 PCIe Root Port
[    0.769021] [      T1] pci 0000:00:02.4: PCI bridge to [bus 07]
[    0.769026] [      T1] pci 0000:00:02.4:   bridge window [mem 0xfcd00000-0xfcdfffff]
[    0.769036] [      T1] pci 0000:00:02.4: enabling Extended Tags
[    0.769071] [      T1] pci 0000:00:02.4: PME# supported from D0 D3hot D3cold
[    0.769214] [      T1] pci 0000:00:08.0: [1022:1632] type 00 class 0x060000 conventional PCI endpoint
[    0.769337] [      T1] pci 0000:00:08.1: [1022:1635] type 01 class 0x060400 PCIe Root Port
[    0.769349] [      T1] pci 0000:00:08.1: PCI bridge to [bus 08]
[    0.769352] [      T1] pci 0000:00:08.1:   bridge window [io  0xe000-0xefff]
[    0.769354] [      T1] pci 0000:00:08.1:   bridge window [mem 0xfc500000-0xfc9fffff]
[    0.769359] [      T1] pci 0000:00:08.1:   bridge window [mem 0xfe20000000-0xfe301fffff 64bit pref]
[    0.769365] [      T1] pci 0000:00:08.1: enabling Extended Tags
[    0.769399] [      T1] pci 0000:00:08.1: PME# supported from D0 D3hot D3cold
[    0.769612] [      T1] pci 0000:00:14.0: [1022:790b] type 00 class 0x0c0500 conventional PCI endpoint
[    0.769769] [      T1] pci 0000:00:14.3: [1022:790e] type 00 class 0x060100 conventional PCI endpoint
[    0.769950] [      T1] pci 0000:00:18.0: [1022:166a] type 00 class 0x060000 conventional PCI endpoint
[    0.770049] [      T1] pci 0000:00:18.1: [1022:166b] type 00 class 0x060000 conventional PCI endpoint
[    0.770146] [      T1] pci 0000:00:18.2: [1022:166c] type 00 class 0x060000 conventional PCI endpoint
[    0.770245] [      T1] pci 0000:00:18.3: [1022:166d] type 00 class 0x060000 conventional PCI endpoint
[    0.770342] [      T1] pci 0000:00:18.4: [1022:166e] type 00 class 0x060000 conventional PCI endpoint
[    0.770440] [      T1] pci 0000:00:18.5: [1022:166f] type 00 class 0x060000 conventional PCI endpoint
[    0.770538] [      T1] pci 0000:00:18.6: [1022:1670] type 00 class 0x060000 conventional PCI endpoint
[    0.770636] [      T1] pci 0000:00:18.7: [1022:1671] type 00 class 0x060000 conventional PCI endpoint
[    0.770812] [      T1] pci 0000:01:00.0: [1002:1478] type 01 class 0x060400 PCIe Switch Upstream Port
[    0.770833] [      T1] pci 0000:01:00.0: BAR 0 [mem 0xfcc00000-0xfcc03fff]
[    0.770837] [      T1] pci 0000:01:00.0: PCI bridge to [bus 02-03]
[    0.770845] [      T1] pci 0000:01:00.0:   bridge window [mem 0xfca00000-0xfcbfffff]
[    0.770853] [      T1] pci 0000:01:00.0:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.770942] [      T1] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[    0.771020] [      T1] pci 0000:01:00.0: 63.008 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x8 link at 0000:00:01.1 (capable of 126.024 Gb/s with
16.0 GT/s PCIe x8 link)
[    0.771172] [      T1] pci 0000:00:01.1: PCI bridge to [bus 01-03]
[    0.771252] [      T1] pci 0000:02:00.0: [1002:1479] type 01 class 0x060400 PCIe Switch Downstream Port
[    0.771274] [      T1] pci 0000:02:00.0: PCI bridge to [bus 03]
[    0.771282] [      T1] pci 0000:02:00.0:   bridge window [mem 0xfca00000-0xfcbfffff]
[    0.771290] [      T1] pci 0000:02:00.0:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.771373] [      T1] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
[    0.772164] [      T1] pci 0000:01:00.0: PCI bridge to [bus 02-03]
[    0.772254] [      T1] pci 0000:03:00.0: [1002:73ff] type 00 class 0x038000 PCIe Legacy Endpoint
[    0.772288] [      T1] pci 0000:03:00.0: BAR 0 [mem 0xfc00000000-0xfdffffffff 64bit pref]
[    0.772291] [      T1] pci 0000:03:00.0: BAR 2 [mem 0xfe00000000-0xfe0fffffff 64bit pref]
[    0.772294] [      T1] pci 0000:03:00.0: BAR 5 [mem 0xfca00000-0xfcafffff]
[    0.772296] [      T1] pci 0000:03:00.0: ROM [mem 0xfcb00000-0xfcb1ffff pref]
[    0.772386] [      T1] pci 0000:03:00.0: PME# supported from D1 D2 D3hot D3cold
[    0.772466] [      T1] pci 0000:03:00.0: 63.008 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x8 link at 0000:00:01.1 (capable of 252.048 Gb/s with
16.0 GT/s PCIe x16 link)
[    0.772616] [      T1] pci 0000:03:00.1: [1002:ab28] type 00 class 0x040300 PCIe Legacy Endpoint
[    0.772648] [      T1] pci 0000:03:00.1: BAR 0 [mem 0xfcb20000-0xfcb23fff]
[    0.772714] [      T1] pci 0000:03:00.1: PME# supported from D1 D2 D3hot D3cold
[    0.772911] [      T1] pci 0000:02:00.0: PCI bridge to [bus 03]
[    0.773008] [      T1] pci 0000:04:00.0: [14c3:0608] type 00 class 0x028000 PCIe Endpoint
[    0.773052] [      T1] pci 0000:04:00.0: BAR 0 [mem 0xfe30300000-0xfe303fffff 64bit pref]
[    0.773056] [      T1] pci 0000:04:00.0: BAR 2 [mem 0xfe30400000-0xfe30403fff 64bit pref]
[    0.773059] [      T1] pci 0000:04:00.0: BAR 4 [mem 0xfe30404000-0xfe30404fff 64bit pref]
[    0.773131] [      T1] pci 0000:04:00.0: supports D1 D2
[    0.773133] [      T1] pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.773356] [      T1] pci 0000:00:02.1: PCI bridge to [bus 04]
[    0.773435] [      T1] pci 0000:05:00.0: [10ec:8168] type 00 class 0x020000 PCIe Endpoint
[    0.773480] [      T1] pci 0000:05:00.0: BAR 0 [io  0xf000-0xf0ff]
[    0.773485] [      T1] pci 0000:05:00.0: BAR 2 [mem 0xfcf04000-0xfcf04fff 64bit]
[    0.773488] [      T1] pci 0000:05:00.0: BAR 4 [mem 0xfcf00000-0xfcf03fff 64bit]
[    0.773576] [      T1] pci 0000:05:00.0: supports D1 D2
[    0.773577] [      T1] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[    0.773812] [      T1] pci 0000:00:02.2: PCI bridge to [bus 05]
[    0.773929] [      T1] pci 0000:06:00.0: [2646:5013] type 00 class 0x010802 PCIe Endpoint
[    0.774033] [      T1] pci 0000:06:00.0: BAR 0 [mem 0xfce00000-0xfce03fff 64bit]
[    0.774567] [      T1] pci 0000:06:00.0: 31.504 Gb/s available PCIe bandwidth, limited by 8.0 GT/s PCIe x4 link at 0000:00:02.3 (capable of 63.012 Gb/s with
16.0 GT/s PCIe x4 link)
[    0.774823] [      T1] pci 0000:00:02.3: PCI bridge to [bus 06]
[    0.775238] [      T1] pci 0000:07:00.0: [c0a9:2263] type 00 class 0x010802 PCIe Endpoint
[    0.775281] [      T1] pci 0000:07:00.0: BAR 0 [mem 0xfcd00000-0xfcd03fff 64bit]
[    0.775596] [      T1] pci 0000:00:02.4: PCI bridge to [bus 07]
[    0.775699] [      T1] pci 0000:08:00.0: [1002:1638] type 00 class 0x030000 PCIe Legacy Endpoint
[    0.775722] [      T1] pci 0000:08:00.0: BAR 0 [mem 0xfe20000000-0xfe2fffffff 64bit pref]
[    0.775724] [      T1] pci 0000:08:00.0: BAR 2 [mem 0xfe30000000-0xfe301fffff 64bit pref]
[    0.775726] [      T1] pci 0000:08:00.0: BAR 4 [io  0xe000-0xe0ff]
[    0.775728] [      T1] pci 0000:08:00.0: BAR 5 [mem 0xfc900000-0xfc97ffff]
[    0.775733] [      T1] pci 0000:08:00.0: enabling Extended Tags
[    0.775785] [      T1] pci 0000:08:00.0: PME# supported from D1 D2 D3hot D3cold
[    0.775954] [      T1] pci 0000:08:00.1: [1002:1637] type 00 class 0x040300 PCIe Legacy Endpoint
[    0.775975] [      T1] pci 0000:08:00.1: BAR 0 [mem 0xfc9c8000-0xfc9cbfff]
[    0.775982] [      T1] pci 0000:08:00.1: enabling Extended Tags
[    0.776014] [      T1] pci 0000:08:00.1: PME# supported from D1 D2 D3hot D3cold
[    0.776142] [      T1] pci 0000:08:00.2: [1022:15df] type 00 class 0x108000 PCIe Endpoint
[    0.776164] [      T1] pci 0000:08:00.2: BAR 2 [mem 0xfc800000-0xfc8fffff]
[    0.776167] [      T1] pci 0000:08:00.2: BAR 5 [mem 0xfc9ce000-0xfc9cffff]
[    0.776172] [      T1] pci 0000:08:00.2: enabling Extended Tags
[    0.776321] [      T1] pci 0000:08:00.3: [1022:1639] type 00 class 0x0c0330 PCIe Endpoint
[    0.776343] [      T1] pci 0000:08:00.3: BAR 0 [mem 0xfc700000-0xfc7fffff 64bit]
[    0.776350] [      T1] pci 0000:08:00.3: enabling Extended Tags
[    0.776384] [      T1] pci 0000:08:00.3: PME# supported from D0 D3hot D3cold
[    0.776528] [      T1] pci 0000:08:00.4: [1022:1639] type 00 class 0x0c0330 PCIe Endpoint
[    0.776550] [      T1] pci 0000:08:00.4: BAR 0 [mem 0xfc600000-0xfc6fffff 64bit]
[    0.776557] [      T1] pci 0000:08:00.4: enabling Extended Tags
[    0.776591] [      T1] pci 0000:08:00.4: PME# supported from D0 D3hot D3cold
[    0.776731] [      T1] pci 0000:08:00.5: [1022:15e2] type 00 class 0x048000 PCIe Endpoint
[    0.776752] [      T1] pci 0000:08:00.5: BAR 0 [mem 0xfc980000-0xfc9bffff]
[    0.776760] [      T1] pci 0000:08:00.5: enabling Extended Tags
[    0.776791] [      T1] pci 0000:08:00.5: PME# supported from D0 D3hot D3cold
[    0.776933] [      T1] pci 0000:08:00.6: [1022:15e3] type 00 class 0x040300 PCIe Endpoint
[    0.776954] [      T1] pci 0000:08:00.6: BAR 0 [mem 0xfc9c0000-0xfc9c7fff]
[    0.776962] [      T1] pci 0000:08:00.6: enabling Extended Tags
[    0.776994] [      T1] pci 0000:08:00.6: PME# supported from D0 D3hot D3cold
[    0.777123] [      T1] pci 0000:08:00.7: [1022:15e4] type 00 class 0x118000 PCIe Endpoint
[    0.777145] [      T1] pci 0000:08:00.7: BAR 2 [mem 0xfc500000-0xfc5fffff]
[    0.777148] [      T1] pci 0000:08:00.7: BAR 5 [mem 0xfc9cc000-0xfc9cdfff]
[    0.777153] [      T1] pci 0000:08:00.7: enabling Extended Tags
[    0.777336] [      T1] pci 0000:00:08.1: PCI bridge to [bus 08]
[    0.777358] [      T1] pci_bus 0000:00: on NUMA node 0
[    0.779571] [      T1] ACPI: PCI: Interrupt link LNKA configured for IRQ 0
[    0.779636] [      T1] ACPI: PCI: Interrupt link LNKB configured for IRQ 0
[    0.779691] [      T1] ACPI: PCI: Interrupt link LNKC configured for IRQ 0
[    0.779756] [      T1] ACPI: PCI: Interrupt link LNKD configured for IRQ 0
[    0.779816] [      T1] ACPI: PCI: Interrupt link LNKE configured for IRQ 0
[    0.779866] [      T1] ACPI: PCI: Interrupt link LNKF configured for IRQ 0
[    0.779921] [      T1] ACPI: PCI: Interrupt link LNKG configured for IRQ 0
[    0.779971] [      T1] ACPI: PCI: Interrupt link LNKH configured for IRQ 0
[    0.781620] [      T1] Low-power S0 idle used by default for system suspend
[    0.782458] [      T1] ACPI: EC: interrupt unblocked
[    0.782459] [      T1] ACPI: EC: event unblocked
[    0.782461] [      T1] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
[    0.782462] [      T1] ACPI: EC: GPE=0x3
[    0.782463] [      T1] ACPI: \_SB_.PCI0.SBRG.EC__: Boot ECDT EC initialization complete
[    0.782465] [      T1] ACPI: \_SB_.PCI0.SBRG.EC__: EC: Used to handle transactions and events
[    0.782532] [      T1] iommu: Default domain type: Passthrough
[    0.782547] [      T1] EDAC MC: Ver: 3.0.0
[    0.782962] [      T1] efivars: Registered efivars operations
[    0.783051] [      T1] NetLabel: Initializing
[    0.783052] [      T1] NetLabel:  domain hash size = 128
[    0.783053] [      T1] NetLabel:  protocols = UNLABELED CIPSOv4 CALIPSO
[    0.783071] [      T1] NetLabel:  unlabeled traffic allowed by default
[    0.783072] [      T1] PCI: Using ACPI for IRQ routing
[    0.787815] [      T1] PCI: pci_cache_line_size set to 64 bytes
[    0.788055] [      T1] e820: reserve RAM buffer [mem 0x09bff000-0x0bffffff]
[    0.788057] [      T1] e820: reserve RAM buffer [mem 0x0a200000-0x0bffffff]
[    0.788058] [      T1] e820: reserve RAM buffer [mem 0xe6058000-0xe7ffffff]
[    0.788059] [      T1] e820: reserve RAM buffer [mem 0xe868b000-0xebffffff]
[    0.788060] [      T1] e820: reserve RAM buffer [mem 0xe9cdf000-0xebffffff]
[    0.788061] [      T1] e820: reserve RAM buffer [mem 0xee000000-0xefffffff]
[    0.788062] [      T1] e820: reserve RAM buffer [mem 0x3ee300000-0x3efffffff]
[    0.788179] [      T1] pci 0000:08:00.0: vgaarb: setting as boot VGA device
[    0.788179] [      T1] pci 0000:08:00.0: vgaarb: bridge control possible
[    0.788179] [      T1] pci 0000:08:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none
[    0.788179] [      T1] vgaarb: loaded
[    0.788524] [      T1] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
[    0.788528] [      T1] hpet0: 3 comparators, 32-bit 14.318180 MHz counter
[    0.790927] [      T1] clocksource: Switched to clocksource hpet
[    0.791202] [      T1] AppArmor: AppArmor Filesystem Enabled
[    0.791219] [      T1] pnp: PnP ACPI init
[    0.791324] [      T1] system 00:00: [mem 0xf0000000-0xf7ffffff] has been reserved
[    0.791967] [      T1] system 00:04: [io  0x04d0-0x04d1] has been reserved
[    0.791969] [      T1] system 00:04: [io  0x040b] has been reserved
[    0.791971] [      T1] system 00:04: [io  0x04d6] has been reserved
[    0.791973] [      T1] system 00:04: [io  0x0c00-0x0c01] has been reserved
[    0.791974] [      T1] system 00:04: [io  0x0c14] has been reserved
[    0.791975] [      T1] system 00:04: [io  0x0c50-0x0c51] has been reserved
[    0.791977] [      T1] system 00:04: [io  0x0c52] has been reserved
[    0.791978] [      T1] system 00:04: [io  0x0c6c] has been reserved
[    0.791980] [      T1] system 00:04: [io  0x0c6f] has been reserved
[    0.791981] [      T1] system 00:04: [io  0x0cd8-0x0cdf] has been reserved
[    0.791982] [      T1] system 00:04: [io  0x0800-0x089f] has been reserved
[    0.791984] [      T1] system 00:04: [io  0x0b00-0x0b0f] has been reserved
[    0.791985] [      T1] system 00:04: [io  0x0b20-0x0b3f] has been reserved
[    0.791987] [      T1] system 00:04: [io  0x0900-0x090f] has been reserved
[    0.791988] [      T1] system 00:04: [io  0x0910-0x091f] has been reserved
[    0.791990] [      T1] system 00:04: [mem 0xfec00000-0xfec00fff] could not be reserved
[    0.791992] [      T1] system 00:04: [mem 0xfec01000-0xfec01fff] could not be reserved
[    0.791993] [      T1] system 00:04: [mem 0xfedc0000-0xfedc0fff] has been reserved
[    0.791995] [      T1] system 00:04: [mem 0xfee00000-0xfee00fff] has been reserved
[    0.791996] [      T1] system 00:04: [mem 0xfed80000-0xfed8ffff] could not be reserved
[    0.791998] [      T1] system 00:04: [mem 0xfec10000-0xfec10fff] has been reserved
[    0.791999] [      T1] system 00:04: [mem 0xff000000-0xffffffff] has been reserved
[    0.792988] [      T1] pnp: PnP ACPI: found 5 devices
[    0.800043] [      T1] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[    0.800150] [      T1] NET: Registered PF_INET protocol family
[    0.800458] [      T1] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.802709] [      T1] tcp_listen_portaddr_hash hash table entries: 8192 (order: 6, 327680 bytes, linear)
[    0.802789] [      T1] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    0.802793] [      T1] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.802965] [      T1] TCP bind hash table entries: 65536 (order: 10, 5242880 bytes, vmalloc hugepage)
[    0.803796] [      T1] TCP: Hash tables configured (established 131072 bind 65536)
[    0.804042] [      T1] MPTCP token hash table entries: 16384 (order: 7, 917504 bytes, linear)
[    0.804175] [      T1] UDP hash table entries: 8192 (order: 8, 1310720 bytes, linear)
[    0.804428] [      T1] UDP-Lite hash table entries: 8192 (order: 8, 1310720 bytes, linear)
[    0.804710] [      T1] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    0.804721] [      T1] NET: Registered PF_XDP protocol family
[    0.804730] [      T1] pci 0000:00:01.1: bridge window [io  0x1000-0x0fff] to [bus 01-03] add_size 1000
[    0.804740] [      T1] pci 0000:00:01.1: bridge window [io  0x1000-0x1fff]: assigned
[    0.804743] [      T1] pci 0000:02:00.0: PCI bridge to [bus 03]
[    0.804752] [      T1] pci 0000:02:00.0:   bridge window [mem 0xfca00000-0xfcbfffff]
[    0.804756] [      T1] pci 0000:02:00.0:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804762] [      T1] pci 0000:01:00.0: PCI bridge to [bus 02-03]
[    0.804766] [      T1] pci 0000:01:00.0:   bridge window [mem 0xfca00000-0xfcbfffff]
[    0.804769] [      T1] pci 0000:01:00.0:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804774] [      T1] pci 0000:00:01.1: PCI bridge to [bus 01-03]
[    0.804776] [      T1] pci 0000:00:01.1:   bridge window [io  0x1000-0x1fff]
[    0.804779] [      T1] pci 0000:00:01.1:   bridge window [mem 0xfca00000-0xfccfffff]
[    0.804782] [      T1] pci 0000:00:01.1:   bridge window [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804786] [      T1] pci 0000:00:02.1: PCI bridge to [bus 04]
[    0.804790] [      T1] pci 0000:00:02.1:   bridge window [mem 0xfe30300000-0xfe304fffff 64bit pref]
[    0.804794] [      T1] pci 0000:00:02.2: PCI bridge to [bus 05]
[    0.804796] [      T1] pci 0000:00:02.2:   bridge window [io  0xf000-0xffff]
[    0.804799] [      T1] pci 0000:00:02.2:   bridge window [mem 0xfcf00000-0xfcffffff]
[    0.804804] [      T1] pci 0000:00:02.3: PCI bridge to [bus 06]
[    0.804807] [      T1] pci 0000:00:02.3:   bridge window [mem 0xfce00000-0xfcefffff]
[    0.804812] [      T1] pci 0000:00:02.4: PCI bridge to [bus 07]
[    0.804815] [      T1] pci 0000:00:02.4:   bridge window [mem 0xfcd00000-0xfcdfffff]
[    0.804821] [      T1] pci 0000:00:08.1: PCI bridge to [bus 08]
[    0.804823] [      T1] pci 0000:00:08.1:   bridge window [io  0xe000-0xefff]
[    0.804826] [      T1] pci 0000:00:08.1:   bridge window [mem 0xfc500000-0xfc9fffff]
[    0.804828] [      T1] pci 0000:00:08.1:   bridge window [mem 0xfe20000000-0xfe301fffff 64bit pref]
[    0.804832] [      T1] pci_bus 0000:00: resource 4 [io  0x0000-0x03af window]
[    0.804834] [      T1] pci_bus 0000:00: resource 5 [io  0x03e0-0x0cf7 window]
[    0.804835] [      T1] pci_bus 0000:00: resource 6 [io  0x03b0-0x03df window]
[    0.804836] [      T1] pci_bus 0000:00: resource 7 [io  0x0d00-0xffff window]
[    0.804837] [      T1] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000dffff window]
[    0.804838] [      T1] pci_bus 0000:00: resource 9 [mem 0xf0000000-0xfcffffff window]
[    0.804840] [      T1] pci_bus 0000:00: resource 10 [mem 0x410000000-0xffffffffff window]
[    0.804841] [      T1] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
[    0.804842] [      T1] pci_bus 0000:01: resource 1 [mem 0xfca00000-0xfccfffff]
[    0.804843] [      T1] pci_bus 0000:01: resource 2 [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804844] [      T1] pci_bus 0000:02: resource 1 [mem 0xfca00000-0xfcbfffff]
[    0.804845] [      T1] pci_bus 0000:02: resource 2 [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804847] [      T1] pci_bus 0000:03: resource 1 [mem 0xfca00000-0xfcbfffff]
[    0.804848] [      T1] pci_bus 0000:03: resource 2 [mem 0xfc00000000-0xfe0fffffff 64bit pref]
[    0.804849] [      T1] pci_bus 0000:04: resource 2 [mem 0xfe30300000-0xfe304fffff 64bit pref]
[    0.804851] [      T1] pci_bus 0000:05: resource 0 [io  0xf000-0xffff]
[    0.804852] [      T1] pci_bus 0000:05: resource 1 [mem 0xfcf00000-0xfcffffff]
[    0.804853] [      T1] pci_bus 0000:06: resource 1 [mem 0xfce00000-0xfcefffff]
[    0.804854] [      T1] pci_bus 0000:07: resource 1 [mem 0xfcd00000-0xfcdfffff]
[    0.804855] [      T1] pci_bus 0000:08: resource 0 [io  0xe000-0xefff]
[    0.804856] [      T1] pci_bus 0000:08: resource 1 [mem 0xfc500000-0xfc9fffff]
[    0.804857] [      T1] pci_bus 0000:08: resource 2 [mem 0xfe20000000-0xfe301fffff 64bit pref]
[    0.804992] [      T1] pci 0000:03:00.1: D0 power state depends on 0000:03:00.0
[    0.805182] [      T1] pci 0000:08:00.1: D0 power state depends on 0000:08:00.0
[    0.805232] [      T1] pci 0000:08:00.3: extending delay after power-on from D3hot to 20 msec
[    0.805414] [      T1] pci 0000:08:00.4: extending delay after power-on from D3hot to 20 msec
[    0.805515] [      T1] PCI: CLS 64 bytes, default 64
[    0.805531] [      T1] pci 0000:00:00.2: AMD-Vi: IOMMU performance counters supported
[    0.805594] [    T147] Trying to unpack rootfs image as initramfs...
[    0.805625] [      T1] pci 0000:00:00.0: Adding to iommu group 0
[    0.805657] [      T1] pci 0000:00:01.0: Adding to iommu group 1
[    0.805679] [      T1] pci 0000:00:01.1: Adding to iommu group 2
[    0.805713] [      T1] pci 0000:00:02.0: Adding to iommu group 3
[    0.805736] [      T1] pci 0000:00:02.1: Adding to iommu group 4
[    0.805759] [      T1] pci 0000:00:02.2: Adding to iommu group 5
[    0.805781] [      T1] pci 0000:00:02.3: Adding to iommu group 6
[    0.805803] [      T1] pci 0000:00:02.4: Adding to iommu group 7
[    0.805835] [      T1] pci 0000:00:08.0: Adding to iommu group 8
[    0.805858] [      T1] pci 0000:00:08.1: Adding to iommu group 9
[    0.805896] [      T1] pci 0000:00:14.0: Adding to iommu group 10
[    0.805915] [      T1] pci 0000:00:14.3: Adding to iommu group 10
[    0.806007] [      T1] pci 0000:00:18.0: Adding to iommu group 11
[    0.806029] [      T1] pci 0000:00:18.1: Adding to iommu group 11
[    0.806051] [      T1] pci 0000:00:18.2: Adding to iommu group 11
[    0.806072] [      T1] pci 0000:00:18.3: Adding to iommu group 11
[    0.806093] [      T1] pci 0000:00:18.4: Adding to iommu group 11
[    0.806119] [      T1] pci 0000:00:18.5: Adding to iommu group 11
[    0.806139] [      T1] pci 0000:00:18.6: Adding to iommu group 11
[    0.806160] [      T1] pci 0000:00:18.7: Adding to iommu group 11
[    0.806185] [      T1] pci 0000:01:00.0: Adding to iommu group 12
[    0.806209] [      T1] pci 0000:02:00.0: Adding to iommu group 13
[    0.806260] [      T1] pci 0000:03:00.0: Adding to iommu group 14
[    0.806286] [      T1] pci 0000:03:00.1: Adding to iommu group 15
[    0.806308] [      T1] pci 0000:04:00.0: Adding to iommu group 16
[    0.806330] [      T1] pci 0000:05:00.0: Adding to iommu group 17
[    0.806352] [      T1] pci 0000:06:00.0: Adding to iommu group 18
[    0.806375] [      T1] pci 0000:07:00.0: Adding to iommu group 19
[    0.806400] [      T1] pci 0000:08:00.0: Adding to iommu group 20
[    0.806422] [      T1] pci 0000:08:00.1: Adding to iommu group 21
[    0.806445] [      T1] pci 0000:08:00.2: Adding to iommu group 22
[    0.806469] [      T1] pci 0000:08:00.3: Adding to iommu group 23
[    0.806494] [      T1] pci 0000:08:00.4: Adding to iommu group 24
[    0.806517] [      T1] pci 0000:08:00.5: Adding to iommu group 25
[    0.806542] [      T1] pci 0000:08:00.6: Adding to iommu group 26
[    0.806566] [      T1] pci 0000:08:00.7: Adding to iommu group 27
[    0.807268] [      T1] AMD-Vi: Extended features (0x206d73ef22254ade, 0x0): PPR X2APIC NX GT IA GA PC GA_vAPIC
[    0.807274] [      T1] AMD-Vi: Interrupt remapping enabled
[    0.807274] [      T1] AMD-Vi: X2APIC enabled
[    0.807555] [      T1] AMD-Vi: Virtual APIC enabled
[    0.807561] [      T1] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[    0.807563] [      T1] software IO TLB: mapped [mem 0x00000000e1bd7000-0x00000000e5bd7000] (64MB)
[    0.807615] [      T1] RAPL PMU: API unit is 2^-32 Joules, 2 fixed counters, 163840 ms ovfl timer
[    0.807616] [      T1] RAPL PMU: hw unit of domain package 2^-16 Joules
[    0.807617] [      T1] RAPL PMU: hw unit of domain core 2^-16 Joules
[    0.807619] [      T1] LVT offset 0 assigned for vector 0x400
[    0.809358] [      T1] perf: AMD IBS detected (0x000003ff)
[    0.809502] [     T24] amd_uncore: 4 amd_df counters detected
[    0.809509] [     T24] amd_uncore: 6 amd_l3 counters detected
[    0.809647] [      T1] perf/amd_iommu: Detected AMD IOMMU #0 (2 banks, 4 counters/bank).
[    0.810600] [      T1] Initialise system trusted keyrings
[    0.810657] [      T1] workingset: timestamp_bits=46 max_order=22 bucket_order=0
[    0.820142] [      T1] Key type asymmetric registered
[    0.820144] [      T1] Asymmetric key parser 'x509' registered
[    0.820162] [      T1] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[    0.820215] [      T1] io scheduler mq-deadline registered
[    0.821871] [      T1] pcieport 0000:00:01.1: PME: Signaling with IRQ 43
[    0.821906] [      T1] pcieport 0000:00:01.1: pciehp: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ IbPresDis-
LLActRep+
[    0.822241] [      T1] pcieport 0000:00:02.1: PME: Signaling with IRQ 44
[    0.822470] [      T1] pcieport 0000:00:02.2: PME: Signaling with IRQ 45
[    0.822685] [      T1] pcieport 0000:00:02.3: PME: Signaling with IRQ 46
[    0.822915] [      T1] pcieport 0000:00:02.4: PME: Signaling with IRQ 47
[    0.823134] [      T1] pcieport 0000:00:08.1: PME: Signaling with IRQ 48
[    0.823774] [      T1] ACPI: video: Video Device [VGA] (multi-head: yes  rom: no  post: no)
[    0.824068] [      T1] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:13/LNXVIDEO:00/input/input0
[    0.824509] [     T10] Monitor-Mwait will be used to enter C-1 state
[    0.827446] [      T1] Estimated ratio of average max frequency by base frequency (times 1024): 1226
[    0.828395] [      T1] thermal LNXTHERM:00: registered as thermal_zone0
[    0.828397] [      T1] ACPI: thermal: Thermal Zone [THRM] (62 C)
[    0.828517] [      T1] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.829405] [      T1] ACPI: bus type drm_connector registered
[    0.831395] [      T1] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
[    0.834746] [      T1] serio: i8042 KBD port at 0x60,0x64 irq 1
[    0.834757] [      T1] serio: i8042 AUX port at 0x60,0x64 irq 12
[    0.835027] [      T1] mousedev: PS/2 mouse device common for all mice
[    0.835064] [      T1] rtc_cmos 00:01: RTC can wake from S4
[    0.835437] [      T1] rtc_cmos 00:01: registered as rtc0
[    0.835483] [      T1] rtc_cmos 00:01: setting system clock to 2025-09-17T21:53:50 UTC (1758146030)
[    0.835526] [      T1] rtc_cmos 00:01: alarms up to one month, y3k, 114 bytes nvram
[    0.837635] [      T1] efifb: probing for efifb
[    0.837646] [      T1] efifb: framebuffer at 0xfe20000000, using 8100k, total 8100k
[    0.837647] [      T1] efifb: mode is 1920x1080x32, linelength=7680, pages=1
[    0.837649] [      T1] efifb: scrolling: redraw
[    0.837650] [      T1] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
[    0.847383] [     T87] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input1
[    0.861971] [      T1] Console: switching to colour frame buffer device 240x67
[    0.884027] [      T1] fb0: EFI VGA frame buffer device
[    0.884546] [      T1] NET: Registered PF_INET6 protocol family
[    0.885274] [      T1] Segment Routing with IPv6
[    0.885283] [      T1] In-situ OAM (IOAM) with IPv6
[    0.885302] [      T1] mip6: Mobile IPv6
[    0.885305] [      T1] NET: Registered PF_PACKET protocol family
[    0.885359] [      T1] mpls_gso: MPLS GSO support
[    0.887850] [      T1] x86/amd: Previous system reset reason [0x00080800]: software wrote 0x6 to reset control register 0xCF9
[    0.887858] [      T1] microcode: Current revision: 0x0a50000c
[    0.891487] [      T1] resctrl: L3 allocation detected
[    0.891488] [      T1] resctrl: MB allocation detected
[    0.891489] [      T1] resctrl: L3 monitoring detected
[    0.891522] [      T1] IPI shorthand broadcast: enabled
[    0.894438] [      T1] registered taskstats version 1
[    0.894543] [      T1] Loading compiled-in X.509 certificates
[    0.898311] [      T1] Key type .fscrypt registered
[    0.898312] [      T1] Key type fscrypt-provisioning registered
[    0.898328] [      T1] AppArmor: AppArmor sha256 policy hashing enabled
[    0.900358] [      T1] ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0.GP17.MP2], AE_NOT_FOUND (20250404/psargs-332)
[    0.900366] [      T1] ACPI Error: Aborting method \_SB.GPIO._EVT due to previous error (AE_NOT_FOUND) (20250404/psparse-529)
[    0.900427] [      T1] clk: Disabling unused clocks
[    0.900429] [      T1] PM: genpd: Disabling unused power domains
[    1.005658] [    T147] Freeing initrd memory: 40440K
[    1.006552] [      T1] Freeing unused kernel image (initmem) memory: 1400K
[    1.006560] [      T1] Write protecting the kernel read-only data: 16384k
[    1.006875] [      T1] Freeing unused kernel image (text/rodata gap) memory: 596K
[    1.006942] [      T1] Freeing unused kernel image (rodata/data gap) memory: 12K
[    1.049925] [      T1] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[    1.049931] [      T1] Run /init as init process
[    1.049933] [      T1]   with arguments:
[    1.049934] [      T1]     /init
[    1.049935] [      T1]   with environment:
[    1.049936] [      T1]     HOME=/
[    1.049937] [      T1]     TERM=linux
[    1.166212] [    T304] piix4_smbus 0000:00:14.0: SMBus Host Controller at 0xb00, revision 0
[    1.166216] [    T304] piix4_smbus 0000:00:14.0: Using register 0x02 for SMBus port selection
[    1.167451] [    T304] i2c i2c-1: Successfully instantiated SPD at 0x50
[    1.168095] [    T304] piix4_smbus 0000:00:14.0: Auxiliary SMBus Host Controller at 0xb20
[    1.172217] [    T307] hid: raw HID events driver (C) Jiri Kosina
[    1.180413] [     T12] nvme 0000:06:00.0: platform quirk: setting simple suspend
[    1.180443] [    T152] nvme 0000:07:00.0: platform quirk: setting simple suspend
[    1.192644] [     T12] nvme nvme0: pci function 0000:06:00.0
[    1.192756] [    T152] nvme nvme1: pci function 0000:07:00.0
[    1.207081] [    T333] pcie_mp2_amd 0000:08:00.7: enabling device (0000 -> 0002)
[    1.212995] [    T152] nvme nvme1: missing or invalid SUBNQN field.
[    1.219591] [    T329] ACPI: bus type USB registered
[    1.225829] [    T329] usbcore: registered new interface driver usbfs
[    1.226085] [     T12] nvme nvme0: D3 entry latency set to 10 seconds
[    1.236805] [    T329] usbcore: registered new interface driver hub
[    1.243068] [    T329] usbcore: registered new device driver usb
[    1.248946] [    T302] r8169 0000:05:00.0 eth0: RTL8168h/8111h, d8:bb:c1:ab:dd:5e, XID 541, IRQ 52
[    1.248949] [    T302] r8169 0000:05:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
[    1.260857] [    T289] hid-generic 0020:1022:0001.0001: hidraw0: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.261173] [    T179] hid-generic 0020:1022:0001.0004: hidraw1: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.271061] [    T289] hid-generic 0020:1022:0001.0002: hidraw2: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.276147] [    T179] hid-generic 0020:1022:0001.0005: hidraw3: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.283574] [    T289] hid-generic 0020:1022:0001.0003: hidraw4: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.283950] [    T289] hid-generic 0020:1022:0001.0006: hidraw5: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.297214] [     T12] nvme nvme0: 16/0/0 default/read/poll queues
[    1.299753] [    T152] nvme nvme1: 15/0/0 default/read/poll queues
[    1.312617] [    T158]  nvme1n1: p1
[    1.319287] [    T149]  nvme0n1: p1 p2 p3 p4
[    1.408297] [    T147] input: PNP0C50:0e 06CB:7E7E Mouse as /devices/platform/AMDI0010:03/i2c-0/i2c-PNP0C50:0e/0018:06CB:7E7E.0007/input/input5
[    1.408429] [    T147] input: PNP0C50:0e 06CB:7E7E Touchpad as /devices/platform/AMDI0010:03/i2c-0/i2c-PNP0C50:0e/0018:06CB:7E7E.0007/input/input6
[    1.408577] [    T147] hid-generic 0018:06CB:7E7E.0007: input,hidraw6: I2C HID v1.00 Mouse [PNP0C50:0e 06CB:7E7E] on i2c-PNP0C50:0e
[    1.422627] [    T343] r8169 0000:05:00.0 enp5s0: renamed from eth0
[    1.428450] [    T311] hid-sensor-hub 0020:1022:0001.0001: hidraw0: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.430085] [    T311] hid-sensor-hub 0020:1022:0001.0002: hidraw2: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.431808] [    T311] hid-sensor-hub 0020:1022:0001.0003: hidraw4: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.435136] [    T311] hid-sensor-hub 0020:1022:0001.0004: hidraw1: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.438826] [    T311] hid-sensor-hub 0020:1022:0001.0005: hidraw3: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.444541] [    T311] hid-sensor-hub 0020:1022:0001.0006: hidraw5: SENSOR HUB HID v0.00 Device [hid-amdsfh 1022:0001] on pcie_mp2_amd
[    1.468089] [    T329] xhci_hcd 0000:08:00.3: xHCI Host Controller
[    1.468097] [    T329] xhci_hcd 0000:08:00.3: new USB bus registered, assigned bus number 1
[    1.468178] [    T329] xhci_hcd 0000:08:00.3: hcc params 0x0268ffe5 hci version 0x110 quirks 0x0000020000000010
[    1.475772] [    T329] xhci_hcd 0000:08:00.3: xHCI Host Controller
[    1.475924] [    T329] xhci_hcd 0000:08:00.3: new USB bus registered, assigned bus number 2
[    1.475927] [    T329] xhci_hcd 0000:08:00.3: Host supports USB 3.1 Enhanced SuperSpeed
[    1.477026] [    T329] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.17
[    1.477029] [    T329] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.477031] [    T329] usb usb1: Product: xHCI Host Controller
[    1.477033] [    T329] usb usb1: Manufacturer: Linux 6.17.0-rc5-next-20250912-master-00001-g68697fae2855 xhci-hcd
[    1.477034] [    T329] usb usb1: SerialNumber: 0000:08:00.3
[    1.478148] [    T296] input: PNP0C50:0e 06CB:7E7E Mouse as /devices/platform/AMDI0010:03/i2c-0/i2c-PNP0C50:0e/0018:06CB:7E7E.0007/input/input8
[    1.481104] [    T296] input: PNP0C50:0e 06CB:7E7E Touchpad as /devices/platform/AMDI0010:03/i2c-0/i2c-PNP0C50:0e/0018:06CB:7E7E.0007/input/input9
[    1.501773] [    T329] hub 1-0:1.0: USB hub found
[    1.502626] [    T329] hub 1-0:1.0: 4 ports detected
[    1.506318] [    T296] hid-multitouch 0018:06CB:7E7E.0007: input,hidraw6: I2C HID v1.00 Mouse [PNP0C50:0e 06CB:7E7E] on i2c-PNP0C50:0e
[    1.529476] [    T329] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[    1.529780] [    T329] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 6.17
[    1.529805] [    T329] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.529812] [    T329] usb usb2: Product: xHCI Host Controller
[    1.529813] [    T329] usb usb2: Manufacturer: Linux 6.17.0-rc5-next-20250912-master-00001-g68697fae2855 xhci-hcd
[    1.529822] [    T329] usb usb2: SerialNumber: 0000:08:00.3
[    1.534474] [    T329] hub 2-0:1.0: USB hub found
[    1.535120] [    T329] hub 2-0:1.0: 2 ports detected
[    1.542890] [    T329] xhci_hcd 0000:08:00.4: xHCI Host Controller
[    1.542957] [    T329] xhci_hcd 0000:08:00.4: new USB bus registered, assigned bus number 3
[    1.543560] [    T329] xhci_hcd 0000:08:00.4: hcc params 0x0268ffe5 hci version 0x110 quirks 0x0000020000000010
[    1.558191] [    T329] xhci_hcd 0000:08:00.4: xHCI Host Controller
[    1.558212] [    T329] xhci_hcd 0000:08:00.4: new USB bus registered, assigned bus number 4
[    1.558301] [    T329] xhci_hcd 0000:08:00.4: Host supports USB 3.1 Enhanced SuperSpeed
[    1.560237] [    T329] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 6.17
[    1.560249] [    T329] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.560253] [    T329] usb usb3: Product: xHCI Host Controller
[    1.560254] [    T329] usb usb3: Manufacturer: Linux 6.17.0-rc5-next-20250912-master-00001-g68697fae2855 xhci-hcd
[    1.560260] [    T329] usb usb3: SerialNumber: 0000:08:00.4
[    1.562083] [    T329] hub 3-0:1.0: USB hub found
[    1.564193] [    T329] hub 3-0:1.0: 4 ports detected
[    1.575128] [    T329] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[    1.575722] [    T329] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 6.17
[    1.575751] [    T329] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    1.575779] [    T329] usb usb4: Product: xHCI Host Controller
[    1.575794] [    T329] usb usb4: Manufacturer: Linux 6.17.0-rc5-next-20250912-master-00001-g68697fae2855 xhci-hcd
[    1.575802] [    T329] usb usb4: SerialNumber: 0000:08:00.4
[    1.579360] [    T329] hub 4-0:1.0: USB hub found
[    1.579452] [    T329] hub 4-0:1.0: 2 ports detected
[    1.766235] [    T386] usb 1-2: new low-speed USB device number 2 using xhci_hcd
[    1.814232] [    T111] usb 3-3: new high-speed USB device number 2 using xhci_hcd
[    1.899096] [    T386] usb 1-2: New USB device found, idVendor=1bcf, idProduct=08a0, bcdDevice= 1.04
[    1.899099] [    T386] usb 1-2: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[    1.929596] [    T334] input: HID 1bcf:08a0 Mouse as /devices/pci0000:00/0000:00:08.1/0000:08:00.3/usb1/1-2/1-2:1.0/0003:1BCF:08A0.0008/input/input11
[    1.929735] [    T334] input: HID 1bcf:08a0 Keyboard as /devices/pci0000:00/0000:00:08.1/0000:08:00.3/usb1/1-2/1-2:1.0/0003:1BCF:08A0.0008/input/input12
[    1.944656] [    T111] usb 3-3: New USB device found, idVendor=0e8d, idProduct=0608, bcdDevice= 1.00
[    1.944658] [    T111] usb 3-3: New USB device strings: Mfr=5, Product=6, SerialNumber=7
[    1.944660] [    T111] usb 3-3: Product: Wireless_Device
[    1.944661] [    T111] usb 3-3: Manufacturer: MediaTek Inc.
[    1.944662] [    T111] usb 3-3: SerialNumber: 000000000
[    2.006748] [    T334] input: HID 1bcf:08a0 as /devices/pci0000:00/0000:00:08.1/0000:08:00.3/usb1/1-2/1-2:1.0/0003:1BCF:08A0.0008/input/input13
[    2.006979] [    T334] hid-generic 0003:1BCF:08A0.0008: input,hiddev0,hidraw7: USB HID v1.10 Mouse [HID 1bcf:08a0] on usb-0000:08:00.3-2/input0
[    2.007023] [    T334] usbcore: registered new interface driver usbhid
[    2.007024] [    T334] usbhid: USB HID core driver
[    2.030359] [    T386] usb 1-4: new high-speed USB device number 3 using xhci_hcd
[    2.042510] [    T315] [drm] amdgpu kernel modesetting enabled.
[    2.042525] [    T315] amdgpu: vga_switcheroo: detected switching method \_SB_.PCI0.GP17.VGA_.ATPX handle
[    2.042945] [    T315] amdgpu: ATPX version 1, functions 0x00000001
[    2.042996] [    T315] amdgpu: ATPX Hybrid Graphics
[    2.062609] [    T315] amdgpu: Virtual CRAT table created for CPU
[    2.062789] [    T315] amdgpu: Topology: Add CPU node
[    2.064523] [    T315] amdgpu 0000:03:00.0: enabling device (0000 -> 0002)
[    2.065384] [    T315] amdgpu 0000:03:00.0: amdgpu: initializing kernel modesetting (DIMGREY_CAVEFISH 0x1002:0x73FF 0x1462:0x1313 0xC3).
[    2.066113] [    T315] amdgpu 0000:03:00.0: amdgpu: register mmio base: 0xFCA00000
[    2.066120] [    T315] amdgpu 0000:03:00.0: amdgpu: register mmio size: 1048576
[    2.075400] [    T111] usb 3-4: new full-speed USB device number 3 using xhci_hcd
[    2.120382] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 0 <common_v1_0_0> (nv_common)
[    2.120384] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 1 <gmc_v10_0_0> (gmc_v10_0)
[    2.120386] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 2 <ih_v5_0_0> (navi10_ih)
[    2.120388] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 3 <psp_v11_0_0> (psp)
[    2.120389] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 4 <smu_v11_0_0> (smu)
[    2.120391] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 5 <dce_v1_0_0> (dm)
[    2.120392] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 6 <gfx_v10_0_0> (gfx_v10_0)
[    2.120394] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 7 <sdma_v5_2_0> (sdma_v5_2)
[    2.120395] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 8 <vcn_v3_0_0> (vcn_v3_0)
[    2.120397] [    T315] amdgpu 0000:03:00.0: amdgpu: detected ip block number 9 <jpeg_v3_0_0> (jpeg_v3_0)
[    2.120406] [    T315] amdgpu 0000:03:00.0: amdgpu: ACPI VFCT table present but broken (too short #2),skipping
[    2.174252] [    T386] usb 1-4: New USB device found, idVendor=30c9, idProduct=0042, bcdDevice= 0.03
[    2.174257] [    T386] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    2.174259] [    T386] usb 1-4: Product: Integrated Camera
[    2.174261] [    T386] usb 1-4: Manufacturer: S1F0009330LB620L420004LP
[    2.174262] [    T386] usb 1-4: SerialNumber: SunplusIT Inc
[    2.187162] [    T315] amdgpu 0000:03:00.0: amdgpu: Fetched VBIOS from ROM BAR
[    2.187164] [    T315] amdgpu: ATOM BIOS: SWBRT77181.001
[    2.216943] [    T315] amdgpu 0000:03:00.0: amdgpu: Trusted Memory Zone (TMZ) feature disabled as experimental (default)
[    2.217235] [    T315] amdgpu 0000:03:00.0: amdgpu: GPU posting now...
[    2.219263] [    T315] amdgpu 0000:03:00.0: amdgpu: vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit
[    2.219288] [    T315] amdgpu 0000:03:00.0: amdgpu: VRAM: 8176M 0x0000008000000000 - 0x00000081FEFFFFFF (8176M used)
[    2.219291] [    T315] amdgpu 0000:03:00.0: amdgpu: GART: 512M 0x0000000000000000 - 0x000000001FFFFFFF
[    2.219469] [    T315] [drm] Detected VRAM RAM=8176M, BAR=8192M
[    2.219471] [    T315] [drm] RAM width 128bits GDDR6
[    2.222628] [    T315] amdgpu 0000:03:00.0: amdgpu: amdgpu: 8176M of VRAM memory ready
[    2.222635] [    T315] amdgpu 0000:03:00.0: amdgpu: amdgpu: 5391M of GTT memory ready.
[    2.222847] [    T315] [drm] GART: num cpu pages 131072, num gpu pages 131072
[    2.227067] [    T315] [drm] PCIE GART of 512M enabled (table at 0x00000081FEB00000).
[    2.236858] [    T111] usb 3-4: New USB device found, idVendor=1462, idProduct=1563, bcdDevice= 2.00
[    2.236889] [    T111] usb 3-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    2.236890] [    T111] usb 3-4: Product: MysticLight MS-1563 v0001
[    2.236891] [    T111] usb 3-4: Manufacturer: MSI
[    2.236903] [    T111] usb 3-4: SerialNumber: 2064386A5430
[    2.266315] [    T111] hid-generic 0003:1462:1563.0009: hiddev1,hidraw8: USB HID v1.11 Device [MSI MysticLight MS-1563 v0001] on usb-0000:08:00.4-4/input0
[    4.614165] [    T315] amdgpu 0000:03:00.0: amdgpu: STB initialized to 2048 entries
[    4.614259] [    T315] amdgpu 0000:03:00.0: amdgpu: [drm] Loading DMUB firmware via PSP: version=0x02020020
[    4.614658] [    T315] [drm] use_doorbell being set to: [true]
[    4.614673] [    T315] [drm] use_doorbell being set to: [true]
[    4.614691] [    T315] amdgpu 0000:03:00.0: amdgpu: [VCN instance 0] Found VCN firmware Version ENC: 1.33 DEC: 4 VEP: 0 Revision: 6
[    4.808720] [    T315] amdgpu 0000:03:00.0: amdgpu: reserve 0xa00000 from 0x81fd000000 for PSP TMR
[    4.892778] [    T315] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available
[    4.912660] [    T315] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: optional securedisplay ta ucode is not available
[    4.912679] [    T315] amdgpu 0000:03:00.0: amdgpu: smu driver if version = 0x0000000f, smu fw if version = 0x00000013, smu fw program = 0, version =
0x003b3100 (59.49.0)
[    4.912682] [    T315] amdgpu 0000:03:00.0: amdgpu: SMU driver if version not matched
[    4.912710] [    T315] amdgpu 0000:03:00.0: amdgpu: use vbios provided pptable
[    4.963260] [    T315] amdgpu 0000:03:00.0: amdgpu: SMU is initialized successfully!
[    4.963650] [    T315] amdgpu 0000:03:00.0: amdgpu: [drm] Display Core v3.2.349 initialized on DCN 3.0.2
[    4.963652] [    T315] amdgpu 0000:03:00.0: amdgpu: [drm] DP-HDMI FRL PCON supported
[    4.964985] [    T315] amdgpu 0000:03:00.0: amdgpu: [drm] DMUB hardware initialized: version=0x02020020
[    4.997052] [    T315] amdgpu 0000:03:00.0: amdgpu: kiq ring mec 2 pipe 1 q 0
[    5.006667] [    T315] kfd kfd: amdgpu: Allocated 3969056 bytes on gart
[    5.006678] [    T315] kfd kfd: amdgpu: Total number of KFD nodes to be created: 1
[    5.007075] [    T315] amdgpu: Virtual CRAT table created for GPU
[    5.008096] [    T315] amdgpu: Topology: Add dGPU node [0x73ff:0x1002]
[    5.008098] [    T315] kfd kfd: amdgpu: added device 1002:73ff
[    5.008382] [    T315] amdgpu 0000:03:00.0: amdgpu: SE 2, SH per SE 2, CU per SH 8, active_cu_number 28
[    5.008507] [    T315] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
[    5.008523] [    T315] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
[    5.008541] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 4 on hub 0
[    5.008542] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 5 on hub 0
[    5.008543] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 6 on hub 0
[    5.008565] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 7 on hub 0
[    5.008567] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 8 on hub 0
[    5.008568] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 9 on hub 0
[    5.008574] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 10 on hub 0
[    5.008580] [    T315] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 11 on hub 0
[    5.008581] [    T315] amdgpu 0000:03:00.0: amdgpu: ring kiq_0.2.1.0 uses VM inv eng 12 on hub 0
[    5.008589] [    T315] amdgpu 0000:03:00.0: amdgpu: ring sdma0 uses VM inv eng 13 on hub 0
[    5.008602] [    T315] amdgpu 0000:03:00.0: amdgpu: ring sdma1 uses VM inv eng 14 on hub 0
[    5.008604] [    T315] amdgpu 0000:03:00.0: amdgpu: ring vcn_dec_0 uses VM inv eng 0 on hub 8
[    5.008605] [    T315] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.0 uses VM inv eng 1 on hub 8
[    5.008609] [    T315] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.1 uses VM inv eng 4 on hub 8
[    5.008614] [    T315] amdgpu 0000:03:00.0: amdgpu: ring jpeg_dec uses VM inv eng 5 on hub 8
[    5.017256] [    T315] amdgpu 0000:03:00.0: amdgpu: Using BOCO for runtime pm
[    5.043259] [    T315] [drm] Initialized amdgpu 3.64.0 for 0000:03:00.0 on minor 0
[    5.055075] [    T315] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[    5.055748] [    T315] [drm] pre_validate_dsc:1667 MST_DSC dsc precompute is not needed
[    5.060255] [    T315] amdgpu 0000:08:00.0: enabling device (0006 -> 0007)
[    5.061213] [    T315] amdgpu 0000:08:00.0: amdgpu: initializing kernel modesetting (RENOIR 0x1002:0x1638 0x1462:0x1313 0xC5).
[    5.061913] [    T315] amdgpu 0000:08:00.0: amdgpu: register mmio base: 0xFC900000
[    5.061927] [    T315] amdgpu 0000:08:00.0: amdgpu: register mmio size: 524288
[    5.117954] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 0 <common_v2_0_0> (soc15_common)
[    5.118091] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 1 <gmc_v9_0_0> (gmc_v9_0)
[    5.118116] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 2 <ih_v4_0_0> (vega10_ih)
[    5.118118] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 3 <psp_v12_0_0> (psp)
[    5.118124] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 4 <smu_v12_0_0> (smu)
[    5.118151] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 5 <dce_v1_0_0> (dm)
[    5.118152] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 6 <gfx_v9_0_0> (gfx_v9_0)
[    5.118159] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 7 <sdma_v4_0_0> (sdma_v4_0)
[    5.118161] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 8 <vcn_v2_0_0> (vcn_v2_0)
[    5.118174] [    T315] amdgpu 0000:08:00.0: amdgpu: detected ip block number 9 <jpeg_v2_0_0> (jpeg_v2_0)
[    5.118763] [    T315] amdgpu 0000:08:00.0: amdgpu: Fetched VBIOS from VFCT
[    5.118764] [    T315] amdgpu: ATOM BIOS: 113-CEZANNE-018
[    5.237770] [    T315] Console: switching to colour dummy device 80x25
[    5.237803] [    T315] amdgpu 0000:08:00.0: vgaarb: deactivate vga console
[    5.237804] [    T315] amdgpu 0000:08:00.0: amdgpu: Trusted Memory Zone (TMZ) feature enabled
[    5.237806] [    T315] amdgpu 0000:08:00.0: amdgpu: MODE2 reset
[    5.240670] [    T315] amdgpu 0000:08:00.0: amdgpu: vm size is 262144 GB, 4 levels, block size is 9-bit, fragment size is 9-bit
[    5.240676] [    T315] amdgpu 0000:08:00.0: amdgpu: VRAM: 512M 0x000000F400000000 - 0x000000F41FFFFFFF (512M used)
[    5.240678] [    T315] amdgpu 0000:08:00.0: amdgpu: GART: 1024M 0x0000000000000000 - 0x000000003FFFFFFF
[    5.240683] [    T315] [drm] Detected VRAM RAM=512M, BAR=512M
[    5.240684] [    T315] [drm] RAM width 128bits DDR4
[    5.240772] [    T315] amdgpu 0000:08:00.0: amdgpu: amdgpu: 512M of VRAM memory ready
[    5.240774] [    T315] amdgpu 0000:08:00.0: amdgpu: amdgpu: 5391M of GTT memory ready.
[    5.240786] [    T315] [drm] GART: num cpu pages 262144, num gpu pages 262144
[    5.240870] [    T315] [drm] PCIE GART of 1024M enabled.
[    5.240872] [    T315] [drm] PTB located at 0x000000F41FC00000
[    5.241175] [    T315] amdgpu 0000:08:00.0: amdgpu: [drm] Loading DMUB firmware via PSP: version=0x0101002B
[    5.241627] [    T315] amdgpu 0000:08:00.0: amdgpu: [VCN instance 0] Found VCN firmware Version ENC: 1.24 DEC: 8 VEP: 0 Revision: 3
[    5.241959] [    T315] amdgpu 0000:08:00.0: amdgpu: reserve 0x400000 from 0xf41f800000 for PSP TMR
[    5.329353] [    T315] amdgpu 0000:08:00.0: amdgpu: RAS: optional ras ta ucode is not available
[    5.338230] [    T315] amdgpu 0000:08:00.0: amdgpu: RAP: optional rap ta ucode is not available
[    5.338232] [    T315] amdgpu 0000:08:00.0: amdgpu: SECUREDISPLAY: optional securedisplay ta ucode is not available
[    5.338798] [    T315] amdgpu 0000:08:00.0: amdgpu: SMU is initialized successfully!
[    5.340053] [    T315] amdgpu 0000:08:00.0: amdgpu: [drm] Display Core v3.2.349 initialized on DCN 2.1
[    5.340056] [    T315] amdgpu 0000:08:00.0: amdgpu: [drm] DP-HDMI FRL PCON supported
[    5.340599] [    T315] amdgpu 0000:08:00.0: amdgpu: [drm] DMUB hardware initialized: version=0x0101002B
[    5.466995] [    T315] amdgpu 0000:08:00.0: amdgpu: kiq ring mec 2 pipe 1 q 0
[    5.473779] [    T315] kfd kfd: amdgpu: Allocated 3969056 bytes on gart
[    5.473791] [    T315] kfd kfd: amdgpu: Total number of KFD nodes to be created: 1
[    5.473915] [    T315] amdgpu: Virtual CRAT table created for GPU
[    5.475056] [    T315] amdgpu: Topology: Add dGPU node [0x1638:0x1002]
[    5.475058] [    T315] kfd kfd: amdgpu: added device 1002:1638
[    5.475129] [    T315] amdgpu 0000:08:00.0: amdgpu: SE 1, SH per SE 1, CU per SH 8, active_cu_number 8
[    5.475132] [    T315] amdgpu 0000:08:00.0: amdgpu: ring gfx uses VM inv eng 0 on hub 0
[    5.475134] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 1 on hub 0
[    5.475135] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 4 on hub 0
[    5.475136] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 5 on hub 0
[    5.475137] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 6 on hub 0
[    5.475138] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 7 on hub 0
[    5.475139] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 8 on hub 0
[    5.475140] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 9 on hub 0
[    5.475140] [    T315] amdgpu 0000:08:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 10 on hub 0
[    5.475141] [    T315] amdgpu 0000:08:00.0: amdgpu: ring kiq_0.2.1.0 uses VM inv eng 11 on hub 0
[    5.475143] [    T315] amdgpu 0000:08:00.0: amdgpu: ring sdma0 uses VM inv eng 0 on hub 8
[    5.475143] [    T315] amdgpu 0000:08:00.0: amdgpu: ring vcn_dec uses VM inv eng 1 on hub 8
[    5.475144] [    T315] amdgpu 0000:08:00.0: amdgpu: ring vcn_enc0 uses VM inv eng 4 on hub 8
[    5.475146] [    T315] amdgpu 0000:08:00.0: amdgpu: ring vcn_enc1 uses VM inv eng 5 on hub 8
[    5.475146] [    T315] amdgpu 0000:08:00.0: amdgpu: ring jpeg_dec uses VM inv eng 6 on hub 8
[    5.476200] [    T315] amdgpu 0000:08:00.0: amdgpu: Runtime PM not available
[    5.476456] [    T315] amdgpu 0000:08:00.0: amdgpu: [drm] Using custom brightness curve
[    5.476553] [    T315] [drm] Initialized amdgpu 3.64.0 for 0000:08:00.0 on minor 1
[    5.482019] [    T315] fbcon: amdgpudrmfb (fb0) is primary device
[    5.494669] [    T315] Console: switching to colour frame buffer device 240x67
[    5.502947] [    T315] amdgpu 0000:08:00.0: [drm] fb0: amdgpudrmfb frame buffer device
[    5.622743] [    T467] PM: Image not found (code -22)
[    5.680971] [    T480] EXT4-fs (nvme0n1p2): mounted filesystem 73e0f015-c115-4eb2-92cb-dbf7da2b6112 ro with ordered data mode. Quota mode: disabled.
[    5.766966] [      T1] systemd[1]: Inserted module 'autofs4'
[    5.792460] [      T1] systemd[1]: systemd 257.8-1~deb13u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +IPE +SMACK +SECCOMP +GCRYPT -GNUTLS
+OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBCRYPTSETUP_PLUGINS +LIBFDISK +PCRE2 +PWQUALITY +P11KIT +QRENCODE +TPM2
+BZIP2 +LZ4 +XZ +ZLIB +ZSTD +BPF_FRAMEWORK +BTF -XKBCOMMON -UTMP +SYSVINIT +LIBARCHIVE)
[    5.792466] [      T1] systemd[1]: Detected architecture x86-64.
[    5.794889] [      T1] systemd[1]: Hostname set to <lisa>.
[    5.863423] [      T1] systemd[1]: bpf-restrict-fs: BPF LSM hook not enabled in the kernel, BPF LSM not supported.
[    5.977484] [      T1] systemd[1]: Queued start job for default target graphical.target.
[    5.981500] [      T1] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
[    5.981918] [      T1] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
[    5.982322] [      T1] systemd[1]: Created slice system-systemd\x2dfsck.slice - Slice /system/systemd-fsck.
[    5.983408] [      T1] systemd[1]: Created slice user.slice - User and Session Slice.
[    5.983503] [      T1] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
[    5.983904] [      T1] systemd[1]: Set up automount proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point.
[    5.984068] [      T1] systemd[1]: Expecting device dev-disk-by\x2duuid-11b4f8f5\x2d4dc8\x2d43e2\x2da1e9\x2d6693a8a172b6.device - /dev/disk/by-uuid/11b4f8f5-
4dc8-43e2-a1e9-6693a8a172b6...
[    5.984356] [      T1] systemd[1]: Expecting device dev-disk-by\x2duuid-33A0\x2d776C.device - /dev/disk/by-uuid/33A0-776C...
[    5.986069] [      T1] systemd[1]: Expecting device dev-disk-by\x2duuid-85e13cd1\x2d3c57\x2d4343\x2da1f5\x2d6209e530b640.device - /dev/disk/by-uuid/85e13cd1-
3c57-4343-a1f5-6209e530b640...
[    5.986100] [      T1] systemd[1]: Expecting device dev-disk-by\x2duuid-d21e6ad6\x2dbc46\x2d4b61\x2dbc20\x2de4d2f4bf719a.device - /dev/disk/by-uuid/d21e6ad6-
bc46-4b61-bc20-e4d2f4bf719a...
[    5.986507] [      T1] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
[    5.987698] [      T1] systemd[1]: Reached target nss-user-lookup.target - User and Group Name Lookups.
[    5.988062] [      T1] systemd[1]: Reached target remote-fs.target - Remote File Systems.
[    5.988410] [      T1] systemd[1]: Reached target slices.target - Slice Units.
[    5.989615] [      T1] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
[    5.990029] [      T1] systemd[1]: Listening on dm-event.socket - Device-mapper event daemon FIFOs.
[    5.990460] [      T1] systemd[1]: Listening on lvm2-lvmpolld.socket - LVM2 poll daemon socket.
[    5.991428] [      T1] systemd[1]: Listening on syslog.socket - Syslog Socket.
[    5.992280] [      T1] systemd[1]: Listening on systemd-creds.socket - Credential Encryption/Decryption.
[    5.993375] [      T1] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
[    5.993735] [      T1] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
[    5.994122] [      T1] systemd[1]: Listening on systemd-journald.socket - Journal Sockets.
[    5.994413] [      T1] systemd[1]: systemd-pcrextend.socket - TPM PCR Measurements was skipped because of an unmet condition check
(ConditionSecurity=measured-uki).
[    5.994430] [      T1] systemd[1]: systemd-pcrlock.socket - Make TPM PCR Policy was skipped because of an unmet condition check (ConditionSecurity=measured-
uki).
[    5.994521] [      T1] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
[    5.996735] [      T1] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
[    5.998134] [      T1] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
[    5.999023] [      T1] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
[    5.999873] [      T1] systemd[1]: Mounting run-lock.mount - Legacy Locks Directory /run/lock...
[    6.000992] [      T1] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
[    6.001273] [      T1] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check
(ConditionPathExists=/sys/kernel/tracing).
[    6.002097] [      T1] systemd[1]: Starting blk-availability.service - Availability of block devices...
[    6.004047] [      T1] systemd[1]: Starting keyboard-setup.service - Set the console keyboard layout...
[    6.005773] [      T1] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
[    6.006779] [      T1] systemd[1]: Starting lvm2-monitor.service - Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[    6.008085] [      T1] systemd[1]: Starting [email protected] - Load Kernel Module configfs...
[    6.009062] [      T1] systemd[1]: Starting [email protected] - Load Kernel Module drm...
[    6.010815] [      T1] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
[    6.012034] [      T1] systemd[1]: Starting [email protected] - Load Kernel Module fuse...
[    6.013659] [      T1] systemd[1]: Starting modprobe@nvme_fabrics.service - Load Kernel Module nvme_fabrics...
[    6.014306] [      T1] systemd[1]: systemd-fsck-root.service - File System Check on Root Device was skipped because of an unmet condition check
(ConditionPathExists=!/run/initramfs/fsck-root).
[    6.014356] [      T1] systemd[1]: systemd-hibernate-clear.service - Clear Stale Hibernate Storage Info was skipped because of an unmet condition check
(ConditionPathExists=/sys/firmware/efi/efivars/HibernateLocation-8cf2644b-4b0b-428f-9387-6d876050dc67).
[    6.016154] [      T1] systemd[1]: Starting systemd-journald.service - Journal Service...
[    6.016582] [    T537] pstore: Using crash dump compression: deflate
[    6.018098] [    T537] pstore: Registered efi_pstore as persistent store backend
[    6.018575] [      T1] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
[    6.019728] [      T1] systemd[1]: systemd-pcrmachine.service - TPM PCR Machine ID Measurement was skipped because of an unmet condition check
(ConditionSecurity=measured-uki).
[    6.020740] [      T1] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
[    6.021422] [      T1] systemd[1]: systemd-tpm2-setup-early.service - Early TPM SRK Setup was skipped because of an unmet condition check
(ConditionSecurity=measured-uki).
[    6.022210] [      T1] systemd[1]: Starting systemd-udev-load-credentials.service - Load udev Rules from Credentials...
[    6.024359] [      T1] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
[    6.027441] [    T538] fuse: init (API version 7.45)
[    6.027597] [      T1] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
[    6.027875] [      T1] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
[    6.028393] [      T1] systemd[1]: Mounted run-lock.mount - Legacy Locks Directory /run/lock.
[    6.030598] [      T1] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
[    6.031114] [      T1] systemd[1]: Finished blk-availability.service - Availability of block devices.
[    6.031654] [      T1] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
[    6.033431] [      T1] systemd[1]: [email protected]: Deactivated successfully.
[    6.033683] [      T1] systemd[1]: Finished [email protected] - Load Kernel Module configfs.
[    6.034038] [      T1] systemd[1]: [email protected]: Deactivated successfully.
[    6.034272] [      T1] systemd[1]: Finished [email protected] - Load Kernel Module drm.
[    6.037055] [      T1] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
[    6.037349] [      T1] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
[    6.038121] [    T557] EXT4-fs (nvme0n1p2): re-mounted 73e0f015-c115-4eb2-92cb-dbf7da2b6112 r/w.
[    6.039628] [      T1] systemd[1]: [email protected]: Deactivated successfully.
[    6.039841] [      T1] systemd[1]: Finished [email protected] - Load Kernel Module fuse.
[    6.040152] [      T1] systemd[1]: modprobe@nvme_fabrics.service: Deactivated successfully.
[    6.040383] [      T1] systemd[1]: Finished modprobe@nvme_fabrics.service - Load Kernel Module nvme_fabrics.
[    6.042556] [      T1] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
[    6.044168] [      T1] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
[    6.046218] [      T1] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
[    6.046729] [      T1] systemd[1]: systemd-hwdb-update.service - Rebuild Hardware Database was skipped because of an unmet condition check
(ConditionNeedsUpdate=/etc).
[    6.046777] [      T1] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check
(ConditionDirectoryNotEmpty=/sys/fs/pstore).
[    6.047626] [      T1] systemd[1]: Starting systemd-random-seed.service - Load/Save OS Random Seed...
[    6.050118] [      T1] systemd[1]: Starting systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully...
[    6.051636] [      T1] systemd[1]: systemd-tpm2-setup.service - TPM SRK Setup was skipped because of an unmet condition check (ConditionSecurity=measured-
uki).
[    6.057748] [    T545] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[    6.060339] [      T1] systemd[1]: Finished systemd-udev-load-credentials.service - Load udev Rules from Credentials.
[    6.060701] [    T545] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[    6.060816] [    T545] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
[    6.061474] [      T1] systemd[1]: Finished keyboard-setup.service - Set the console keyboard layout.
[    6.062138] [    T381] cfg80211: loaded regulatory.db is malformed or signature is missing/invalid
[    6.062210] [    T542] systemd-journald[542]: Collecting audit messages is disabled.
[    6.064528] [      T1] systemd[1]: Finished lvm2-monitor.service - Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling.
[    6.064891] [      T1] systemd[1]: Mounted sys-fs-fuse-connections.mount - FUSE Control File System.
[    6.065346] [      T1] systemd[1]: Mounted sys-kernel-config.mount - Kernel Configuration File System.
[    6.066734] [      T1] systemd[1]: Finished systemd-random-seed.service - Load/Save OS Random Seed.
[    6.090318] [      T1] systemd[1]: Finished systemd-tmpfiles-setup-dev-early.service - Create Static Device Nodes in /dev gracefully.
[    6.090974] [      T1] systemd[1]: systemd-sysusers.service - Create System Users was skipped because no trigger condition checks were met.
[    6.092102] [      T1] systemd[1]: Starting systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev...
[    6.109968] [    T545] mt7921e 0000:04:00.0: enabling device (0000 -> 0002)
[    6.114989] [    T545] mt7921e 0000:04:00.0: ASIC revision: 79610010
[    6.136330] [      T1] systemd[1]: Finished systemd-tmpfiles-setup-dev.service - Create Static Device Nodes in /dev.
[    6.137641] [      T1] systemd[1]: Starting systemd-udevd.service - Rule-based Manager for Device Events and Files...
[    6.154852] [      T1] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
[    6.156104] [      T1] systemd[1]: Starting ifupdown-pre.service - Helper to synchronize boot up for ifupdown...
[    6.161143] [      T1] systemd[1]: Started systemd-journald.service - Journal Service.
[    6.170016] [    T542] systemd-journald[542]: Received client request to flush runtime journal.
[    6.188977] [    T178] mt7921e 0000:04:00.0: HW/SW Version: 0x8a108a10, Build Time: 20241106151007a

[    6.199439] [    T178] mt7921e 0000:04:00.0: WM Firmware Version: ____010000, Build Time: 20241106151045
[    6.291194] [    T661] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:33/PNP0C09:00/PNP0C0D:00/input/input14
[    6.291357] [    T661] ACPI: button: Lid Switch [LID0]
[    6.291507] [    T661] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input15
[    6.291721] [    T661] ACPI: button: Power Button [PWRB]
[    6.291935] [    T661] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input16
[    6.292088] [    T661] ACPI: button: Sleep Button [SLPB]
[    6.296119] [    T620] ACPI: AC: AC Adapter [ADP1] (on-line)
[    6.310578] [    T630] ccp 0000:08:00.2: enabling device (0000 -> 0002)
[    6.312008] [    T630] ccp 0000:08:00.2: tee enabled
[    6.312161] [    T630] ccp 0000:08:00.2: psp enabled
[    6.338397] [    T663] mc: Linux media interface: v0.10
[    6.402161] [    T152] ACPI: battery: Slot [BAT1] (battery present)
[    6.404865] [    T635] input: MSI WMI hotkeys as /devices/virtual/input/input17
[    6.407257] [    T668] snd_rn_pci_acp3x 0000:08:00.5: enabling device (0000 -> 0002)
[    6.416116] [    T663] videodev: Linux video capture interface: v2.00
[    6.430586] [    T663] usb 1-4: Found UVC 1.00 device Integrated Camera (30c9:0042)
[    6.436327] [    T764] Adding 75497468k swap on /dev/nvme0n1p3.  Priority:-2 extents:1 across:75497468k SS
[    6.440783] [    T666] Bluetooth: Core ver 2.22
[    6.440807] [    T666] NET: Registered PF_BLUETOOTH protocol family
[    6.440808] [    T666] Bluetooth: HCI device and connection manager initialized
[    6.440812] [    T666] Bluetooth: HCI socket layer initialized
[    6.440815] [    T666] Bluetooth: L2CAP socket layer initialized
[    6.440820] [    T666] Bluetooth: SCO socket layer initialized
[    6.443530] [    T655] snd_hda_intel 0000:03:00.1: enabling device (0000 -> 0002)
[    6.443629] [    T655] snd_hda_intel 0000:03:00.1: Handle vga_switcheroo audio client
[    6.443632] [    T655] snd_hda_intel 0000:03:00.1: Force to non-snoop mode
[    6.444187] [    T655] snd_hda_intel 0000:08:00.1: enabling device (0000 -> 0002)
[    6.444275] [    T655] snd_hda_intel 0000:08:00.1: Handle vga_switcheroo audio client
[    6.444340] [    T655] snd_hda_intel 0000:08:00.6: enabling device (0000 -> 0002)
[    6.454768] [    T663] usbcore: registered new interface driver uvcvideo
[    6.455378] [    T633] snd_hda_intel 0000:08:00.1: bound 0000:08:00.0 (ops amdgpu_dm_audio_component_bind_ops [amdgpu])
[    6.457066] [    T633] snd_hda_intel 0000:03:00.1: bound 0000:03:00.0 (ops amdgpu_dm_audio_component_bind_ops [amdgpu])
[    6.457546] [    T666] usbcore: registered new interface driver btusb
[    6.459478] [    T210] Bluetooth: hci0: HW/SW Version: 0x008a008a, Build Time: 20241106151414
[    6.463469] [    T177] input: HD-Audio Generic HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:08.1/0000:08:00.1/sound/card1/input18
[    6.463706] [    T383] input: HDA ATI HDMI HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.1/sound/card0/input22
[    6.464560] [    T177] input: HD-Audio Generic HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:08.1/0000:08:00.1/sound/card1/input19
[    6.465038] [    T383] input: HDA ATI HDMI HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.1/sound/card0/input23
[    6.465198] [    T177] input: HD-Audio Generic HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:08.1/0000:08:00.1/sound/card1/input20
[    6.466244] [    T383] input: HDA ATI HDMI HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.1/sound/card0/input24
[    6.466472] [    T177] input: HD-Audio Generic HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:08.1/0000:08:00.1/sound/card1/input21
[    6.467483] [    T383] input: HDA ATI HDMI HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.1/sound/card0/input25
[    6.469273] [    T383] input: HDA ATI HDMI HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:01.1/0000:01:00.0/0000:02:00.0/0000:03:00.1/sound/card0/input26
[    6.470919] [    T800] snd_hda_codec_generic hdaudioC2D0: autoconfig for Generic: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
[    6.470923] [    T800] snd_hda_codec_generic hdaudioC2D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[    6.470925] [    T800] snd_hda_codec_generic hdaudioC2D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
[    6.470926] [    T800] snd_hda_codec_generic hdaudioC2D0:    mono: mono_out=0x0
[    6.470927] [    T800] snd_hda_codec_generic hdaudioC2D0:    inputs:
[    6.470928] [    T800] snd_hda_codec_generic hdaudioC2D0:      Mic=0x19
[    6.481055] [    T127] input: HD-Audio Generic Mic as /devices/pci0000:00/0000:00:08.1/0000:08:00.6/sound/card2/input27
[    6.481165] [    T127] input: HD-Audio Generic Headphone as /devices/pci0000:00/0000:00:08.1/0000:08:00.6/sound/card2/input28
[    6.607442] [    T210] Bluetooth: hci0: Device setup in 146646 usecs
[    6.607446] [    T210] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
[    6.845384] [    T237] psmouse serio1: Failed to deactivate mouse on isa0060/serio1: -71
[    6.944984] [    T237] psmouse serio1: Failed to enable mouse on isa0060/serio1
[    7.054952] [    T829] EXT4-fs (nvme1n1p1): mounted filesystem 85e13cd1-3c57-4343-a1f5-6209e530b640 r/w with ordered data mode. Quota mode: disabled.
[    7.059878] [    T828] EXT4-fs (nvme0n1p4): mounted filesystem d21e6ad6-bc46-4b61-bc20-e4d2f4bf719a r/w with ordered data mode. Quota mode: disabled.
[    7.086665] [    T165] audit: type=1400 audit(1758146036.749:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="brave" pid=865
comm="apparmor_parser"
[    7.086707] [    T165] audit: type=1400 audit(1758146036.749:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="buildah" pid=866
comm="apparmor_parser"
[    7.086745] [    T165] audit: type=1400 audit(1758146036.749:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="busybox" pid=867
comm="apparmor_parser"
[    7.086786] [    T165] audit: type=1400 audit(1758146036.749:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="ch-checkns" pid=869
comm="apparmor_parser"
[    7.086842] [    T165] audit: type=1400 audit(1758146036.749:6): apparmor="STATUS" operation="profile_load" profile="unconfined"
name=4D6F6E676F444220436F6D70617373 pid=861 comm="apparmor_parser"
[    7.086897] [    T165] audit: type=1400 audit(1758146036.749:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="chrome" pid=871
comm="apparmor_parser"
[    7.086938] [    T165] audit: type=1400 audit(1758146036.749:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="QtWebEngineProcess"
pid=862 comm="apparmor_parser"
[    7.086980] [    T165] audit: type=1400 audit(1758146036.749:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="cam" pid=868
comm="apparmor_parser"
[    7.087028] [    T165] audit: type=1400 audit(1758146036.749:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="vscode" pid=873
comm="apparmor_parser"
[    7.087062] [    T165] audit: type=1400 audit(1758146036.749:11): apparmor="STATUS" operation="profile_load" profile="unconfined" name="1password" pid=859
comm="apparmor_parser"
[    7.204764] [   T1019] nvme nvme0: using unchecked data buffer
[    7.205268] [   T1010] Generic FE-GE Realtek PHY r8169-0-500:00: attached PHY driver (mii_bus:phy_addr=r8169-0-500:00, irq=MAC)
[    7.278265] [   T1067] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    7.278267] [   T1067] Bluetooth: BNEP filters: protocol multicast
[    7.278271] [   T1067] Bluetooth: BNEP socket layer initialized
[    7.279795] [    T983] Bluetooth: MGMT ver 1.23
[    7.287734] [   T1074] Bluetooth: RFCOMM TTY layer initialized
[    7.287750] [   T1074] Bluetooth: RFCOMM socket layer initialized
[    7.287755] [   T1074] Bluetooth: RFCOMM ver 1.11
[    7.370479] [    T179] r8169 0000:05:00.0 enp5s0: Link is Down
[    7.753003] [   T1027] block nvme0n1: No UUID available providing old NGUID
[    7.812138] [    T646] mt7921e 0000:04:00.0 wlp4s0: renamed from wlan0
[    8.074129] [    T237] input: PS/2 Generic Mouse as /devices/platform/i8042/serio1/input/input4
[    8.140376] [    T237] psmouse serio1: Failed to enable mouse on isa0060/serio1
[   10.680426] [   T1049] wlp4s0: authenticate with 54:67:51:3d:a2:e0 (local address=c8:94:02:c1:bd:69)
[   10.783698] [    T179] r8169 0000:05:00.0 enp5s0: Link is Up - 1Gbps/Full - flow control rx/tx
[   10.796476] [   T1049] wlp4s0: send auth to 54:67:51:3d:a2:e0 (try 1/3)
[   10.798676] [    T156] wlp4s0: authenticated
[   10.799243] [    T156] wlp4s0: associate with 54:67:51:3d:a2:e0 (try 1/3)
[   10.819060] [    T151] wlp4s0: RX AssocResp from 54:67:51:3d:a2:e0 (capab=0x1411 status=0 aid=3)
[   10.823740] [    T151] wlp4s0: associated
[   10.871862] [    T152] wlp4s0: Limiting TX power to 20 (20 - 0) dBm as advertised by 54:67:51:3d:a2:e0
[   59.052378] [   T1049] wlp4s0: disconnect from AP 54:67:51:3d:a2:e0 for new auth to 54:67:51:3d:a2:d2
[   59.114735] [   T1049] wlp4s0: authenticate with 54:67:51:3d:a2:d2 (local address=c8:94:02:c1:bd:69)
[   59.629161] [   T1049] wlp4s0: send auth to 54:67:51:3d:a2:d2 (try 1/3)
[   59.650331] [    T156] wlp4s0: authenticated
[   59.651250] [    T156] wlp4s0: associate with 54:67:51:3d:a2:d2 (try 1/3)
[   59.704809] [    T156] wlp4s0: RX ReassocResp from 54:67:51:3d:a2:d2 (capab=0x511 status=0 aid=1)
[   59.710990] [    T156] wlp4s0: associated
[   60.729784] [    T155] wlp4s0: deauthenticated from 54:67:51:3d:a2:d2 (Reason: 15=4WAY_HANDSHAKE_TIMEOUT)
[   61.075661] [   T1049] wlp4s0: authenticate with 54:67:51:3d:a2:e0 (local address=c8:94:02:c1:bd:69)
[   61.083577] [   T1049] wlp4s0: send auth to 54:67:51:3d:a2:e0 (try 1/3)
[   61.085839] [    T156] wlp4s0: authenticated
[   61.086241] [    T156] wlp4s0: associate with 54:67:51:3d:a2:e0 (try 1/3)
[   61.101700] [    T156] wlp4s0: RX AssocResp from 54:67:51:3d:a2:e0 (capab=0x1411 status=17 aid=1)
[   61.101704] [    T156] wlp4s0: 54:67:51:3d:a2:e0 denied association (code=17)
[   64.202924] [   T1049] wlp4s0: authenticate with 54:67:51:3d:a2:d2 (local address=c8:94:02:c1:bd:69)
[   64.212253] [   T1049] wlp4s0: send auth to 54:67:51:3d:a2:d2 (try 1/3)
[   64.213428] [    T156] wlp4s0: authenticated
[   64.214236] [    T156] wlp4s0: associate with 54:67:51:3d:a2:d2 (try 1/3)
[   64.267707] [    T151] wlp4s0: RX AssocResp from 54:67:51:3d:a2:d2 (capab=0x511 status=0 aid=1)
[   64.273642] [    T151] wlp4s0: associated
[   82.233572] [    T599] [drm] PCIE GART of 512M enabled (table at 0x00000081FEB00000).
[   82.233594] [    T599] amdgpu 0000:03:00.0: amdgpu: PSP is resuming...
[   82.234311] [    T155] pci_bus 0000:03: Allocating resources
[   82.416209] [    T599] amdgpu 0000:03:00.0: amdgpu: reserve 0xa00000 from 0x81fd000000 for PSP TMR
[   82.500645] [    T599] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available
[   82.516092] [    T599] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: optional securedisplay ta ucode is not available
[   82.516095] [    T599] amdgpu 0000:03:00.0: amdgpu: SMU is resuming...
[   82.516098] [    T599] amdgpu 0000:03:00.0: amdgpu: smu driver if version = 0x0000000f, smu fw if version = 0x00000013, smu fw program = 0, version =
0x003b3100 (59.49.0)
[   82.516101] [    T599] amdgpu 0000:03:00.0: amdgpu: SMU driver if version not matched
[   82.566923] [    T599] amdgpu 0000:03:00.0: amdgpu: Setting new power limit is not supported!
[   82.566925] [    T599] amdgpu 0000:03:00.0: amdgpu: SMU is resumed successfully!
[   82.568800] [    T599] amdgpu 0000:03:00.0: amdgpu: kiq ring mec 2 pipe 1 q 0
[   82.576142] [    T599] amdgpu 0000:03:00.0: amdgpu: [drm] DMUB hardware initialized: version=0x02020020
[   82.594748] [    T599] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[   82.594760] [    T599] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
[   82.594762] [    T599] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
[   82.594763] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 4 on hub 0
[   82.594764] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 5 on hub 0
[   82.594766] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 6 on hub 0
[   82.594767] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 7 on hub 0
[   82.594768] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 8 on hub 0
[   82.594769] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 9 on hub 0
[   82.594770] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 10 on hub 0
[   82.594772] [    T599] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 11 on hub 0
[   82.594773] [    T599] amdgpu 0000:03:00.0: amdgpu: ring kiq_0.2.1.0 uses VM inv eng 12 on hub 0
[   82.594774] [    T599] amdgpu 0000:03:00.0: amdgpu: ring sdma0 uses VM inv eng 13 on hub 0
[   82.594775] [    T599] amdgpu 0000:03:00.0: amdgpu: ring sdma1 uses VM inv eng 14 on hub 0
[   82.594777] [    T599] amdgpu 0000:03:00.0: amdgpu: ring vcn_dec_0 uses VM inv eng 0 on hub 8
[   82.594778] [    T599] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.0 uses VM inv eng 1 on hub 8
[   82.594779] [    T599] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.1 uses VM inv eng 4 on hub 8
[   82.594780] [    T599] amdgpu 0000:03:00.0: amdgpu: ring jpeg_dec uses VM inv eng 5 on hub 8
[   82.598707] [    T599] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[  107.025809] [    T237] [drm] PCIE GART of 512M enabled (table at 0x00000081FEB00000).
[  107.025831] [    T237] amdgpu 0000:03:00.0: amdgpu: PSP is resuming...
[  107.026394] [    T155] pci_bus 0000:03: Allocating resources
[  107.208424] [    T237] amdgpu 0000:03:00.0: amdgpu: reserve 0xa00000 from 0x81fd000000 for PSP TMR
[  107.291597] [    T237] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available
[  107.308100] [    T237] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: optional securedisplay ta ucode is not available
[  107.308102] [    T237] amdgpu 0000:03:00.0: amdgpu: SMU is resuming...
[  107.308106] [    T237] amdgpu 0000:03:00.0: amdgpu: smu driver if version = 0x0000000f, smu fw if version = 0x00000013, smu fw program = 0, version =
0x003b3100 (59.49.0)
[  107.308108] [    T237] amdgpu 0000:03:00.0: amdgpu: SMU driver if version not matched
[  107.358958] [    T237] amdgpu 0000:03:00.0: amdgpu: Setting new power limit is not supported!
[  107.358960] [    T237] amdgpu 0000:03:00.0: amdgpu: SMU is resumed successfully!
[  107.360825] [    T237] amdgpu 0000:03:00.0: amdgpu: kiq ring mec 2 pipe 1 q 0
[  107.367905] [    T237] amdgpu 0000:03:00.0: amdgpu: [drm] DMUB hardware initialized: version=0x02020020
[  107.387000] [    T237] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[  107.387013] [    T237] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
[  107.387015] [    T237] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
[  107.387016] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 4 on hub 0
[  107.387017] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 5 on hub 0
[  107.387018] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 6 on hub 0
[  107.387019] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 7 on hub 0
[  107.387020] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 8 on hub 0
[  107.387021] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 9 on hub 0
[  107.387022] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 10 on hub 0
[  107.387023] [    T237] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 11 on hub 0
[  107.387023] [    T237] amdgpu 0000:03:00.0: amdgpu: ring kiq_0.2.1.0 uses VM inv eng 12 on hub 0
[  107.387024] [    T237] amdgpu 0000:03:00.0: amdgpu: ring sdma0 uses VM inv eng 13 on hub 0
[  107.387025] [    T237] amdgpu 0000:03:00.0: amdgpu: ring sdma1 uses VM inv eng 14 on hub 0
[  107.387026] [    T237] amdgpu 0000:03:00.0: amdgpu: ring vcn_dec_0 uses VM inv eng 0 on hub 8
[  107.387027] [    T237] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.0 uses VM inv eng 1 on hub 8
[  107.387028] [    T237] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.1 uses VM inv eng 4 on hub 8
[  107.387029] [    T237] amdgpu 0000:03:00.0: amdgpu: ring jpeg_dec uses VM inv eng 5 on hub 8
[  107.391209] [    T237] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[  118.065778] [    T111] [drm] PCIE GART of 512M enabled (table at 0x00000081FEB00000).
[  118.065799] [    T111] amdgpu 0000:03:00.0: amdgpu: PSP is resuming...
[  118.066363] [     T12] pci_bus 0000:03: Allocating resources
[  118.248414] [    T111] amdgpu 0000:03:00.0: amdgpu: reserve 0xa00000 from 0x81fd000000 for PSP TMR
[  118.332777] [    T111] amdgpu 0000:03:00.0: amdgpu: RAS: optional ras ta ucode is not available
[  118.349295] [    T111] amdgpu 0000:03:00.0: amdgpu: SECUREDISPLAY: optional securedisplay ta ucode is not available
[  118.349298] [    T111] amdgpu 0000:03:00.0: amdgpu: SMU is resuming...
[  118.349301] [    T111] amdgpu 0000:03:00.0: amdgpu: smu driver if version = 0x0000000f, smu fw if version = 0x00000013, smu fw program = 0, version =
0x003b3100 (59.49.0)
[  118.349303] [    T111] amdgpu 0000:03:00.0: amdgpu: SMU driver if version not matched
[  118.400645] [    T111] amdgpu 0000:03:00.0: amdgpu: Setting new power limit is not supported!
[  118.400646] [    T111] amdgpu 0000:03:00.0: amdgpu: SMU is resumed successfully!
[  118.402579] [    T111] amdgpu 0000:03:00.0: amdgpu: kiq ring mec 2 pipe 1 q 0
[  118.409820] [    T111] amdgpu 0000:03:00.0: amdgpu: [drm] DMUB hardware initialized: version=0x02020020
[  118.428909] [    T111] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes
[  118.428922] [    T111] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.0.0 uses VM inv eng 0 on hub 0
[  118.428923] [    T111] amdgpu 0000:03:00.0: amdgpu: ring gfx_0.1.0 uses VM inv eng 1 on hub 0
[  118.428924] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.0 uses VM inv eng 4 on hub 0
[  118.428925] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.0 uses VM inv eng 5 on hub 0
[  118.428926] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.0 uses VM inv eng 6 on hub 0
[  118.428927] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.0 uses VM inv eng 7 on hub 0
[  118.428928] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.0.1 uses VM inv eng 8 on hub 0
[  118.428929] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.1.1 uses VM inv eng 9 on hub 0
[  118.428930] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.2.1 uses VM inv eng 10 on hub 0
[  118.428931] [    T111] amdgpu 0000:03:00.0: amdgpu: ring comp_1.3.1 uses VM inv eng 11 on hub 0
[  118.428932] [    T111] amdgpu 0000:03:00.0: amdgpu: ring kiq_0.2.1.0 uses VM inv eng 12 on hub 0
[  118.428933] [    T111] amdgpu 0000:03:00.0: amdgpu: ring sdma0 uses VM inv eng 13 on hub 0
[  118.428934] [    T111] amdgpu 0000:03:00.0: amdgpu: ring sdma1 uses VM inv eng 14 on hub 0
[  118.428935] [    T111] amdgpu 0000:03:00.0: amdgpu: ring vcn_dec_0 uses VM inv eng 0 on hub 8
[  118.428936] [    T111] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.0 uses VM inv eng 1 on hub 8
[  118.428937] [    T111] amdgpu 0000:03:00.0: amdgpu: ring vcn_enc_0.1 uses VM inv eng 4 on hub 8
[  118.428938] [    T111] amdgpu 0000:03:00.0: amdgpu: ring jpeg_dec uses VM inv eng 5 on hub 8
[  118.433136] [    T111] amdgpu 0000:03:00.0: [drm] Cannot find any crtc or sizes

Bert Karwatzki

On 9/17/25 22:26, Yazen Ghannam wrote:
<snip>

According to AMD APM 9.3.3.4:

"If the error being logged is a deferred error, then the error will be logged to MCA_DESTAT."

So this means that when Valid is set in DESTAT then the error MUST BE deferred. I.e I think it's in valid to have valid && !deferred in DESTAT, no ?

Additionally nowhere in the APM is ti mentioned what's the default value of MCA_CONFIG.LogDeferredEn so as it stands you are now working with the assumption that it's 1 and DESTAT is always a redundant copy of STATUS.

Btw looking at the output that Bert has provided it seems that indeed MCA_CONFIG.LogDeferredEn is 0 by default:

"
LogDeferredEn—Bit 34. Enable logging of deferred errors in MCA_STATUS. 0=Log deferred errors only in MCA_DESTAT and MCA_DEADDR. 1=Log deferred errors in MCA_STATUS and MCA_ADDR in addition to MCA_DESTAT and MCA_DEADDR. This bit does not affect logging of deferred errors in MCA_SYND or MCA_MISCx. "

I think the polling code is slightly broken now for AMD. The order of operation per poll cycle should be:

1. Check MCA_STATUS -> report if there is anything, clear it the bank
2. (In the same cycle) -> Check DEFERRED and report if there is anything, clear the deferred.

Yes, correct. That is why this issue is perplexing.

The value is determined by the platform. The Linux code is structured so the data is gathered from any possible source. That's why there are a few checks to determine which register to look at.

Banks 9 to 14 seem to have bogus values. And this seems to be the cause of our mishandling here.

You can see the difference compared to the other banks. Banks 7 and 8 are good comparisons as they are of the same "type" (L3 cache).

It is unlikely to have two independent errors in MCA_STATUS and MCA_DESTAT due to how errors can be overwritten by more severe errors. By default, our reference platform implementation has MCA_CONFIG[LogDeferredInMcaStat] enabled. So a deferred error in MCA_STATUS will only be overwritten by an uncorrectable (#MC) error. In this case, MCA_STATUS will be cleared by the #MC handler. And so MCA_DESTAT acts as a backup.

But you're right there is a gap here that we can try to fill if a platform ever changes this config bit.

For the current issue, it does seem that the registers contain junk values. And we are only now seeing this with the recent rework.

Bert, can you please provide two more register dumps from the script?

Our hardware team is interested to see if the values remain consistent or change between reads.

Thanks,
Yazen