gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

for_each_of_imap_item is an iterator designed to help a driver to parse an interrupt-map property.

Indeed some drivers need to know details about the interrupt mapping described in the device-tree in order to set internal registers accordingly.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Tested-by Wolfram Sang <[email protected]>

---
 drivers/of/irq.c       | 70 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/of_irq.h | 41 ++++++++++++++++++++++++-
 2 files changed, 110 insertions(+), 1 deletion(-)

Recently for_each_of_imap_item iterator has been introduce to help drivers in parsing the interrupt-map property.

Add a test case for this iterator.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

---
 .../of/unittest-data/tests-interrupts.dtsi    |   9 ++
 drivers/of/unittest.c                         | 116 ++++++++++++++++++
 2 files changed, 125 insertions(+)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Reviewed-by Wolfram Sang <[email protected]>

---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

drivers/soc/renesas/rzn1_irqmux.c new file +14 -0

@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <[email protected]>
+ */
+
+#include <linux/bitops.h>
+#include <linux/build_bug.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>

drivers/soc/renesas/rzn1_irqmux.c new file +19 -0

+
+static int rzn1_irqmux_parent_args_to_line_index(struct device *dev,
+                                                const struct of_phandle_args *parent_args,
+                                                const u32 output_lines[],
+                                                unsigned int output_lines_count)
+{
+       unsigned int i;
+
+       /*
+        * The parent interrupt should be one of the GIC controller.
+        * Three arguments must be provided.
+        *  - args[0]: GIC_SPI
+        *  - args[1]: The GIC interrupt number
+        *  - args[2]: The interrupt flags
+        *
+        * We retrieve the line index based on the GIC interrupt number
+        * provided and rzn1_irqmux_output_line[] mapping array.
+        */
+

drivers/soc/renesas/rzn1_irqmux.c new file +13 -0

+       int index;
+       int ret;
+       u32 tmp;
+
+       /* We support only #interrupt-cells = <1> and #address-cells = <0> */
+       ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+       if (ret)
+               return ret;
+       if (tmp != 1)
+               return -EINVAL;
+
+       ret = of_property_read_u32(np, "#address-cells", &tmp);
+       if (ret)

drivers/soc/renesas/rzn1_irqmux.c new file +16 -0

+
+       for_each_of_imap_item(&imap_parser, &imap_item) {
+               index = rzn1_irqmux_parent_args_to_line_index(dev,
+                                                             &imap_item.parent_args,
+                                                             rzn1_irqmux_output_lines,
+                                                             ARRAY_SIZE(rzn1_irqmux_output_lines));
+               if (index < 0) {
+                       of_node_put(imap_item.parent_args.np);
+                       return index;
+               }
+
+               if (test_and_set_bit(index, &index_done)) {
+                       of_node_put(imap_item.parent_args.np);
+                       dev_err(dev, "Mux output line already defined\n");
+                       return -EINVAL;
+               }

Hi Hervé,

Quoted 8 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

Thanks for your patch!

drivers/soc/renesas/Makefile obj-$(CONFIG_SYS_R9A09G057) += r9a09g057-sys.o · line 17

Quoted 7 lines

drivers/soc/renesas/Makefile +1 -0

@@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057)   += r9a09g057-sys.o
 # Family
 obj-$(CONFIG_PWC_RZV2M)                += pwc-rzv2m.o
 obj-$(CONFIG_RST_RCAR)         += rcar-rst.o
+obj-$(CONFIG_RZN1_IRQMUX)              += rzn1_irqmux.o  

One TAB too much.

Quoted 18 lines

drivers/soc/renesas/rzn1_irqmux.c new file +14 -0

@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <[email protected]>
+ */
+
+#include <linux/bitops.h>
+#include <linux/build_bug.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>

drivers/soc/renesas/rzn1_irqmux.c line 24

Quoted 10 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+#include <linux/platform_device.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/*
+ * The array index is the output line index, the value at the index is the
+ * GIC SPI interrupt number the output line is connected to.
+ */
+static const u32 rzn1_irqmux_output_lines[] = {
+       103, 104, 105, 106, 107, 108, 109, 110
+};  

I did read the discussion with Wolfram, but the flexibility (and overhead) provided by this array sounds a bit overkill to me.

What about just defining:

    #define RZN1_IRQMUX_SPI_BASE    103
    #define RZN1_IRQMUX_NUM_IRQS    8

?

If/when a new SoC with a similar setup ever arrives, you can probably just replace the constants above by variables inside SoC-specific match data. And if the new mapping would be non-contiguous, you can still revive this array ;-)

More about this below...

Quoted 19 lines

drivers/soc/renesas/rzn1_irqmux.c new file +19 -0

+
+static int rzn1_irqmux_parent_args_to_line_index(struct device *dev,
+                                                const struct of_phandle_args *parent_args,
+                                                const u32 output_lines[],
+                                                unsigned int output_lines_count)
+{
+       unsigned int i;
+
+       /*
+        * The parent interrupt should be one of the GIC controller.
+        * Three arguments must be provided.
+        *  - args[0]: GIC_SPI
+        *  - args[1]: The GIC interrupt number
+        *  - args[2]: The interrupt flags
+        *
+        * We retrieve the line index based on the GIC interrupt number
+        * provided and rzn1_irqmux_output_line[] mapping array.
+        */
+

drivers/soc/renesas/rzn1_irqmux.c line 53

Quoted 10 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+       if (parent_args->args_count != 3 ||
+           parent_args->args[0] != GIC_SPI) {
+               dev_err(dev, "Invalid interrupt-map item\n");
+               return -EINVAL;
+       }
+
+       for (i = 0; i < output_lines_count; i++) {
+               if (parent_args->args[1] == output_lines[i])
+                       return i;
+       }  

... then this loop can be replaced by two simple comparisons.

drivers/soc/renesas/rzn1_irqmux.c line 63

Quoted 10 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+
+       dev_err(dev, "Invalid GIC interrupt %u\n", parent_args->args[1]);
+       return -EINVAL;
+}
+
+static int rzn1_irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)
+{
+       struct of_imap_parser imap_parser;
+       struct of_imap_item imap_item;
+       unsigned long index_done = 0;  

Perhaps "DECLARE_BITMAP(index_done, RZN1_IRQMUX_NUM_IRQS)", so the BITS_PER_LONG limit can be lifted, without any cost?

Quoted 14 lines

drivers/soc/renesas/rzn1_irqmux.c new file +13 -0

+       int index;
+       int ret;
+       u32 tmp;
+
+       /* We support only #interrupt-cells = <1> and #address-cells = <0> */
+       ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+       if (ret)
+               return ret;
+       if (tmp != 1)
+               return -EINVAL;
+
+       ret = of_property_read_u32(np, "#address-cells", &tmp);
+       if (ret)

drivers/soc/renesas/rzn1_irqmux.c line 86

Quoted 10 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+               return ret;
+       if (tmp != 0)
+               return -EINVAL;
+
+       ret = of_imap_parser_init(&imap_parser, np, &imap_item);
+       if (ret)
+               return ret;
+
+       /* 8 output lines are available */
+       BUILD_BUG_ON(ARRAY_SIZE(rzn1_irqmux_output_lines) != 8);  

... then this check can be removed, too.

drivers/soc/renesas/rzn1_irqmux.c line 92

Quoted 6 lines

drivers/soc/renesas/rzn1_irqmux.c new file +6 -0

+
+       /*
+        * index_done is an unsigned long integer. Be sure that no buffer
+        * overflow can occur.
+        */
+       BUILD_BUG_ON(ARRAY_SIZE(rzn1_irqmux_output_lines) > BITS_PER_LONG);  

Currently this is less strict than the check above, so a bit useless?

Quoted 27 lines

drivers/soc/renesas/rzn1_irqmux.c new file +26 -0

+
+       for_each_of_imap_item(&imap_parser, &imap_item) {
+               index = rzn1_irqmux_parent_args_to_line_index(dev,
+                                                             &imap_item.parent_args,
+                                                             rzn1_irqmux_output_lines,
+                                                             ARRAY_SIZE(rzn1_irqmux_output_lines));
+               if (index < 0) {
+                       of_node_put(imap_item.parent_args.np);
+                       return index;
+               }
+
+               if (test_and_set_bit(index, &index_done)) {
+                       of_node_put(imap_item.parent_args.np);
+                       dev_err(dev, "Mux output line already defined\n");
+                       return -EINVAL;
+               }
+
+               /*
+                * The child #address-cells is 0 (already checked). The first
+                * value in imap item is the src hwirq.
+                */
+               writel(imap_item.child_imap[0], regs + index);
+       }
+
+       return 0;
+}  

Quoted 47 lines · On Tue, 21 Oct 2025 15:05:35 +0200 Geert Uytterhoeven <[email protected]>…

Quoted 26 lines · Herve Codina (Schneider Electric)

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by Herve Codina (Schneider Electric) <[email protected]>

drivers/soc/renesas/rzn1_irqmux.c new file +14 -0

@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <[email protected]>
+ */
+
+#include <linux/bitops.h>
+#include <linux/build_bug.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>

drivers/soc/renesas/rzn1_irqmux.c line 24

Quoted 10 lines

drivers/soc/renesas/rzn1_irqmux.c new file +10 -0

+#include <linux/platform_device.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/*
+ * The array index is the output line index, the value at the index is the
+ * GIC SPI interrupt number the output line is connected to.
+ */
+static const u32 rzn1_irqmux_output_lines[] = {
+       103, 104, 105, 106, 107, 108, 109, 110
+};

I did read the discussion with Wolfram, but the flexibility (and overhead) provided by this array sounds a bit overkill to me.

What about just defining:

    #define RZN1_IRQMUX_SPI_BASE    103
    #define RZN1_IRQMUX_NUM_IRQS    8

Quoted 6 lines

?

If/when a new SoC with a similar setup ever arrives, you can probably just replace the constants above by variables inside SoC-specific match data. And if the new mapping would be non-contiguous, you can still revive this array ;-)

I have in mind a use case that can lead to a non-contiguous mapping.

The RZ/N1 SoC embeds a Cortex-M3 CPU. This CPU can use GPIOs and some of them for interrupt purpose. In that case, those GPIOs have to be routed to the interrupt line expected by the Cortex-M3.

And so, we have some interrupts reserved for CPUs running Linux and some others for the Cortex-M3.

Among those reserved interrupts may some are not used.

for instance:
Interrupt 103, 102: Reserved and used by Linux
Interrupt 103: Reserved for Linux but not used -> Hole in the mapping Interrupt 104: Reserved and used my Cortex-M3 (need to be routed by Linux)

I don't know if this use case is relevant but I think we should be too restrictive on the mapping and so accept holes.

With that in mind, I let you confirm that you still prefer to have a mapping without any holes. A future patch to support that is always possible.

Quoted 10 lines

I have in mind a use case that can lead to a non-contiguous mapping.

The RZ/N1 SoC embeds a Cortex-M3 CPU. This CPU can use GPIOs and some of them for interrupt purpose. In that case, those GPIOs have to be routed to the interrupt line expected by the Cortex-M3.

And so, we have some interrupts reserved for CPUs running Linux and some others for the Cortex-M3.

Quoted 6 lines

Among those reserved interrupts may some are not used.

for instance:
Interrupt 103, 102: Reserved and used by Linux
Interrupt 103: Reserved for Linux but not used -> Hole in the mapping Interrupt 104: Reserved and used my Cortex-M3 (need to be routed by Linux)

102 does not seem to be correct?

Quoted 6 lines

I don't know if this use case is relevant but I think we should be too restrictive on the mapping and so accept holes.

With that in mind, I let you confirm that you still prefer to have a mapping without any holes. A future patch to support that is always possible.

While that would indeed be a non-discontiguous mapping, I do not see how it is related to rzn1_irqmux_output_lines[] in the driver. That array would still contain the same contiguous values 103..110, right?

Sorry, I haven't been following the development of this driver that closely (RZ/N1 is completely different from e.g. R-Car, and I never had access to an RZ/N1 platform), so perhaps I am missing something. Why does the user have to specify an interrupt-map in DT? Can't the driver create the mapping dynamically, based actual usage of the GPIOs? I.e. the first 8 GPIOs that ask for interrupt functionality receive it, and are mapped to an available GIC interrupt?
I believe this is how rzg2l-irqc works, mapping up to 32 GPIO interrupts to 32 GIC (TINT) interrupts.

Quoted 16 lines · On Thu, 23 Oct 2025 13:30:53 +0200 Geert Uytterhoeven <[email protected]>…

Quoted 15 lines

I have in mind a use case that can lead to a non-contiguous mapping.

The RZ/N1 SoC embeds a Cortex-M3 CPU. This CPU can use GPIOs and some of them for interrupt purpose. In that case, those GPIOs have to be routed to the interrupt line expected by the Cortex-M3.

And so, we have some interrupts reserved for CPUs running Linux and some others for the Cortex-M3.

Among those reserved interrupts may some are not used.

for instance:
Interrupt 103, 102: Reserved and used by Linux
Interrupt 103: Reserved for Linux but not used -> Hole in the mapping Interrupt 104: Reserved and used my Cortex-M3 (need to be routed by Linux)

Quoted 1 line

102 does not seem to be correct?

My bad, my example was wrong.
Interrupt 103, 104: Reserved and used by Linux
Interrupt 105: Reserved for Linux but not used -> Hole in the mapping Interrupt 106: Reserved and used my Cortex-M3 (need to be routed by Linux)

Quoted 9 lines

Quoted 5 lines

I don't know if this use case is relevant but I think we should be too restrictive on the mapping and so accept holes.

With that in mind, I let you confirm that you still prefer to have a mapping without any holes. A future patch to support that is always possible.

While that would indeed be a non-discontiguous mapping, I do not see how it is related to rzn1_irqmux_output_lines[] in the driver. That array would still contain the same contiguous values 103..110, right?

The array rzn1_irqmux_output_lines is still contiguous yes but the mapping defined in irq-map property no.

Looking back again at your proposal, indeed I can remove the following loop:

        for (i = 0; i < output_lines_count; i++) {
               if (parent_args->args[1] == output_lines[i])
                       return i;
        }

With just

        if (parent_args->args[1] >= RZN1_IRQMUX_SPI_BASE &&
            parent_args->args[1] < RZN1_IRQMUX_SPI_BASE + RZN1_IRQMUX_NUM_IRQS) {
                return parent_args->args[1] - RZN1_IRQMUX_SPI_BASE;

        dev_err(dev, "Invalid GIC interrupt %u\n", parent_args->args[1]);
        return -EINVAL;

Quoted 9 lines

Sorry, I haven't been following the development of this driver that closely (RZ/N1 is completely different from e.g. R-Car, and I never had access to an RZ/N1 platform), so perhaps I am missing something. Why does the user have to specify an interrupt-map in DT? Can't the driver create the mapping dynamically, based actual usage of the GPIOs? I.e. the first 8 GPIOs that ask for interrupt functionality receive it, and are mapped to an available GIC interrupt?
I believe this is how rzg2l-irqc works, mapping up to 32 GPIO interrupts to 32 GIC (TINT) interrupts.

I think the main difference with rzg2l-irqc is that the RZ/N1 irq mux is clearly not an interrupt controller.

It is just a mux with 96 inputs (GPIO lines coming from several GPIO controller) and 8 outputs (connected to the GIC).

It is represented as an interrupt nexus node and has an interrupt-map property. to describe the routing.

The interrupt-map property cannot be dynamically created.

Also, the routing is necessary even if the related GPIO is not used by Linux. This GPIO can be used as a GPIO input interrupt line by the Cortex M3.

If the irq mux driver performs the routing only on Linux GPIO usage, it will not route GPIOs depending on Cortex M3 internal usage.

The first patches in this series are related to a new helper introduced to parse an interrupt-map property.
- patch 1: Introduce the helper (for_each_of_imap_item)
- patch 2: Add a unittest for the new helper
- patch 3 and 4: convert existing drivers to use this new helper

Patch 5 adds support for GPIO (device-tree description)

The last patches (6, 7 and 8) of the series are related to GPIO interrupts and GPIO IRQ multiplexer.

In the RZ/N1 SoCs, GPIO interrupts are wired to a GPIO IRQ multiplexer.

This multiplexer does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines.

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

Quoted 3 lines

This series adds support for GPIO and GPIO IRQ mux available in the RZ/N1 SoCs.

I definitely want to review and test this series. But I can do this on Friday earliest, more likely next Monday.