net: dsa: lantiq_gswip: Add support for MaxLinear GSW1xx switch family
Subsystems (5)
v5 cover net: dsa: lantiq_gswip: Add support for MaxLinear GSW1xx switch family
This patch series extends the existing lantiq_gswip DSA driver to support the MaxLinear GSW1xx family of dedicated Ethernet switch ICs. These switches are based on the same IP as the Lantiq/Intel GSWIP found in VR9 and xRX MIPS router SoCs, but are connected via MDIO instead of memory-mapped I/O.
The series includes several improvements and refactoring to prepare for the new hardware support.
The GSW1xx family includes several variants:
- GSW120: 4 ports, 2 PHYs, RGMII & SGMII/2500Base-X
- GSW125: 4 ports, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
- GSW140: 6 ports, 4 PHYs, RGMII & SGMII/2500Base-X
- GSW141: 6 ports, 4 PHYs, RGMII & SGMII
- GSW145: 6 ports, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
Key features implemented:
- MDIO-based register access using regmap
- Support for SGMII/1000Base-X/2500Base-X SerDes interfaces
- Configurable RGMII delays via device tree properties
- Configurable RMII clock direction
- Energy Efficient Ethernet (EEE) support
- enabling/disabling learning
Daniel Golle (12):
net: dsa: lantiq_gswip: split into common and MMIO parts
net: dsa: lantiq_gswip: support enable/disable learning
net: dsa: lantiq_gswip: support Energy Efficient Ethernet
net: dsa: lantiq_gswip: set link parameters also for CPU port
net: dsa: lantiq_gswip: define and use
GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID
dt-bindings: net: dsa: lantiq,gswip: add support for MII delay
properties
net: dsa: lantiq_gswip: allow adjusting MII delays
dt-bindings: net: dsa: lantiq,gswip: add MaxLinear RMII refclk output
property
net: dsa: lantiq_gswip: add vendor property to setup MII refclk output
dt-bindings: net: dsa: lantiq,gswip: add support for MaxLinear GSW1xx
switches
net: dsa: add tagging driver for MaxLinear GSW1xx switch family
net: dsa: add driver for MaxLinear GSW1xx switch family
.../bindings/net/dsa/lantiq,gswip.yaml | 300 ++- MAINTAINERS | 3 +- drivers/net/dsa/lantiq/Kconfig | 18 +- drivers/net/dsa/lantiq/Makefile | 2 + drivers/net/dsa/lantiq/lantiq_gswip.c | 1617 +-------------- drivers/net/dsa/lantiq/lantiq_gswip.h | 20 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 1737 +++++++++++++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.c | 733 +++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.h | 126 ++ drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h | 154 ++ include/net/dsa.h | 2 + include/uapi/linux/if_ether.h | 1 + net/dsa/Kconfig | 8 + net/dsa/Makefile | 1 + net/dsa/tag_mxl-gsw1xx.c | 116 ++ 15 files changed, 3170 insertions(+), 1668 deletions(-) create mode 100644 drivers/net/dsa/lantiq/lantiq_gswip_common.c create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.c create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.h create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h create mode 100644 net/dsa/tag_mxl-gsw1xx.c
Signature · 1 line
2.51.2
PATCH v5 1/12 net: dsa: lantiq_gswip: split into common and MMIO parts
Move all parts specific for the MMIO/SoC driver into a module of its own to prepare for supporting MDIO-connected switch ICs.
Modify gswip_probe() functions by splitting it into a common function gswip_probe_common() which covers allocating, initializing and registering the DSA switch, while keeping transport-specific regmap initialization as well as PHY firmware loading in the new MMIO/SoC-specific gswip_probe() function.
--- drivers/net/dsa/lantiq/Kconfig | 6 +- drivers/net/dsa/lantiq/Makefile | 1 + drivers/net/dsa/lantiq/lantiq_gswip.c | 1617 +---------------- drivers/net/dsa/lantiq/lantiq_gswip.h | 4 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 1622 ++++++++++++++++++ 5 files changed, 1658 insertions(+), 1592 deletions(-) create mode 100644 drivers/net/dsa/lantiq/lantiq_gswip_common.c
drivers/net/dsa/lantiq/Kconfig +5 -1
@@ -1,8 +1,12 @@ +config NET_DSA_LANTIQ_COMMON + tristate + select REGMAP + config NET_DSA_LANTIQ_GSWIP tristate "Lantiq / Intel GSWIP" depends on HAS_IOMEM select NET_DSA_TAG_GSWIP - select REGMAP + select NET_DSA_LANTIQ_COMMON help This enables support for the Lantiq / Intel GSWIP 2.1 found in the xrx200 / VR9 SoC.
drivers/net/dsa/lantiq/Makefile +1 -0
@@ -1 +1,2 @@ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o +obj-$(CONFIG_NET_DSA_LANTIQ_COMMON) += lantiq_gswip_common.o
drivers/net/dsa/lantiq/lantiq_gswip.c +26 -1591
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drivers/net/dsa/lantiq/lantiq_gswip.h +4 -0
@@ -278,4 +278,8 @@ struct gswip_priv { u16 version; }; +void gswip_disable_switch (struct gswip_priv *priv); + +int gswip_probe_common (struct gswip_priv *priv,u32 version); +#endif /* __LANTIQ_GSWIP_H */
drivers/net/dsa/lantiq/lantiq_gswip_common.c new file +1622 -0
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2.51.2
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PATCH v5 2/12 net: dsa: lantiq_gswip: support enable/disable learning
In reply to Daniel GolleSwitch API 2.2 or later supports enabling or disabling learning on each port. Implement support for BR_LEARNING bridge flag and announce support for BR_LEARNING on GSWIP 2.2 or later.
---
v2: initialize supported flags with 0
drivers/net/dsa/lantiq/lantiq_gswip.h | 3 ++ drivers/net/dsa/lantiq/lantiq_gswip_common.c | 43 ++++++++++++++++++++ 2 files changed, 46 insertions(+)
drivers/net/dsa/lantiq/lantiq_gswip.h +3 -0
@@ -157,6 +157,9 @@#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) +/* Ethernet Switch PCE Port Control Register 3 */ +#define GSWIP_PCE_PCTRL_3p (p) (0x483 + ((p) * 0xA)) +#define GSWIP_PCE_PCTRL_3_LNDIS BIT(15)/* Learning Disable */ #define GSWIP_PCE_VCTRL (p) (0x485 + ((p) * 0xA))#define GSWIP_PCE_VCTRL_UVR BIT(0)/* Unknown VLAN Rule */ #define GSWIP_PCE_VCTRL_VINR GENMASK(2, 1)/* VLAN Ingress Tag Rule */
drivers/net/dsa/lantiq/lantiq_gswip_common.c +43 -0
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Signature · 1 line
2.51.2
PATCH v5 3/12 net: dsa: lantiq_gswip: support Energy Efficient Ethernet
In reply to Daniel GolleIntroduce support for Energy Efficient Ethernet (EEE) on hardware version 2.2 or later.
--- drivers/net/dsa/lantiq/lantiq_gswip.h | 7 +++ drivers/net/dsa/lantiq/lantiq_gswip_common.c | 47 ++++++++++++++++++++ 2 files changed, 54 insertions(+)
drivers/net/dsa/lantiq/lantiq_gswip.h +7 -0
@@ -2,6 +2,7 @@#ifndef __LANTIQ_GSWIP_H#define __LANTIQ_GSWIP_H +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/mutex.h> #include <linux/phylink.h>
@@ -193,6 +194,12 @@#define GSWIP_MAC_CTRL_2p (p) (0x905 + ((p) * 0xC))#define GSWIP_MAC_CTRL_2_LCHKL BIT(2)/* Frame Length Check Long Enable */ #define GSWIP_MAC_CTRL_2_MLEN BIT(3)/* Maximum Untagged Frame Lnegth */ +#define GSWIP_MAC_CTRL_4p (p) (0x907 + ((p) * 0xC)) +#define GSWIP_MAC_CTRL_4_LPIEN BIT(7)/* LPI Mode Enable */ +#define GSWIP_MAC_CTRL_4_GWAIT_MASK GENMASK(14, 8)/* LPI Wait Time 1G */ +#define GSWIP_MAC_CTRL_4_GWAIT (t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_GWAIT_MASK) +#define GSWIP_MAC_CTRL_4_WAIT_MASK GENMASK(6, 0)/* LPI Wait Time 100M */ +#define GSWIP_MAC_CTRL_4_WAIT (t) u16_encode_bits((t), GSWIP_MAC_CTRL_4_WAIT_MASK)/* Ethernet Switch Fetch DMA Port Control Register */ #define GSWIP_FDMA_PCTRLp (p) (0xA80 + ((p) * 0x6))
drivers/net/dsa/lantiq/lantiq_gswip_common.c +47 -0
65 lines not on this page · raw message
Signature · 1 line
2.51.2
PATCH v5 4/12 net: dsa: lantiq_gswip: set link parameters also for CPU port
In reply to Daniel GolleOn standalone switch ICs the link parameters of the CPU port need to be setup just like user ports. The destinction in the driver to not carry out link parameter setup for the CPU port does make sense for in-SoC switches on which the CPU port is internally connected to the SoC's Ethernet MAC.
Set link parameters also for the CPU port unless it is an internal interface. Note that the internal TP PHYs anyway cannot be used as CPU ports, hence it doesn't matter that they are now also covered by that condition.
---
v4: improve commit message
drivers/net/dsa/lantiq/lantiq_gswip_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/net/dsa/lantiq/lantiq_gswip_common.c +1 -1
@@ -1459,7 +1459,7 @@ static void gswip_phylink_mac_link_up(struct phylink_config *config,struct gswip_priv *priv = dp->ds->priv;int port = dp->index; -if (!dsa_port_is_cpu (dp)) { +if (!dsa_port_is_cpu (dp) || interface !=PHY_INTERFACE_MODE_INTERNAL ) {gswip_port_set_link (priv, port, true);gswip_port_set_speed (priv, port, speed, interface);gswip_port_set_duplex (priv, port, duplex);
Signature · 1 line
2.51.2
PATCH v5 5/12 net: dsa: lantiq_gswip: define and use GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID
In reply to Daniel GolleWhen adding FDB entries to the MAC bridge table on GSWIP 2.2 or later it is needed to set an (undocumented) bit to mark the entry as valid. If this bit isn't set for entries in the MAC bridge table, then those entries won't be considered as valid MAC addresses.
---
v4: keep previous behavior for GSWIP 2.1 and earlier
drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-)
drivers/net/dsa/lantiq/lantiq_gswip.h +1 -0
@@ -224,6 +224,7 @@#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0)/* Filtering identifier */ #define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4)/* Port on learned entries */ #define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0)/* Static, non-aging entry */ +#define GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID BIT(1)/* Valid bit */ #define XRX200_GPHY_FW_ALIGN (16 * 1024)
drivers/net/dsa/lantiq/lantiq_gswip_common.c +6 -1
@@ -1149,7 +1149,12 @@ static int gswip_port_fdb(struct dsa_switch *ds, int port, mac_bridge.key[2 ] = addr[1 ] | (addr[0 ] <<8 ); mac_bridge.key[3 ] =FIELD_PREP (GSWIP_TABLE_MAC_BRIDGE_KEY3_FID , fid); mac_bridge.val[0 ] = add ?BIT (port) :0 ;/* port map */ - mac_bridge.val[1 ] =GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC ; +if (GSWIP_VERSION_GE (priv,GSWIP_VERSION_2_2_ETC )) + mac_bridge.val[1 ] = add ? (GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC | +GSWIP_TABLE_MAC_BRIDGE_VAL1_VALID ) :0 ; +else + mac_bridge.val[1 ] =GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC ; + mac_bridge.valid = add; err =gswip_pce_table_entry_write (priv, &mac_bridge);
Signature · 1 line
2.51.2
PATCH v5 6/12 dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
In reply to Daniel GolleAdd support for standard tx-internal-delay-ps and rx-internal-delay-ps properties on port nodes to allow fine-tuning of RGMII clock delays.
The GSWIP switch hardware supports delay values in 500 picosecond increments from 0 to 3500 picoseconds, with a post-reset default of 2000 picoseconds for both TX and RX delays. The driver currently sets the delay to 0 in case the PHY is setup to carry out the delay by the corresponding interface modes ("rgmii-id", "rgmii-rxid", "rgmii-txid").
This corresponds to the driver changes that allow adjusting MII delays using Device Tree properties instead of relying solely on the PHY interface mode.
---
v4:
* remove misleading defaults
v3:
* redefine ports node so properties are defined actually apply
* RGMII port with 2ps delay is 'rgmii-id' mode
.../bindings/net/dsa/lantiq,gswip.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +28 -3
@@ -6,8 +6,31 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Lantiq GSWIP Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports +$ref: dsa.yaml# + +patternProperties: + "^(ethernet-)?ports$": + type: object + patternProperties: + "^(ethernet-)?port@[0-6]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false + + properties: + tx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII TX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + rx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII RX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. maintainers: - Hauke Mehrtens <[email protected]>
@@ -113,8 +136,10 @@ examples: port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; }; port@1 {
Signature · 1 line
2.51.2
Rob Herring
maintainerRe: [PATCH net-next v5 06/12] dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
Quoted 30 lines · Daniel Golle
Add support for standard tx-internal-delay-ps and rx-internal-delay-ps properties on port nodes to allow fine-tuning of RGMII clock delays.
The GSWIP switch hardware supports delay values in 500 picosecond increments from 0 to 3500 picoseconds, with a post-reset default of 2000 picoseconds for both TX and RX delays. The driver currently sets the delay to 0 in case the PHY is setup to carry out the delay by the corresponding interface modes ("rgmii-id", "rgmii-rxid", "rgmii-txid").
This corresponds to the driver changes that allow adjusting MII delays using Device Tree properties instead of relying solely on the PHY interface mode.
Signed-off-by Daniel Golle <[email protected]>---
v4:
* remove misleading defaultsv3:
* redefine ports node so properties are defined actually apply
* RGMII port with 2ps delay is 'rgmii-id' mode.../bindings/net/dsa/lantiq,gswip.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-0
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml $schema: http://devicetree.org/meta-schemas/core.yaml# · line 10
Quoted 5 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-2@@ -6,8 +6,31 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Lantiq GSWIP Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-ports
I think you can keep this as you aren't adding custom properties.
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml $schema: http://devicetree.org/meta-schemas/core.yaml#
Quoted 10 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +9
-0+$ref: dsa.yaml# + +patternProperties: + "^(ethernet-)?ports$": + type: object + patternProperties: + "^(ethernet-)?port@[0-6]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false
And drop these lines. You may need 'additionalProperties: true' if the tools warn.
Quoted 33 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +16
-0+ + properties: + tx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII TX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. + rx-internal-delay-ps: + enum: [0, 500, 1000, 1500, 2000, 2500, 3000, 3500] + description: + RGMII RX Clock Delay defined in pico seconds. + The delay lines adjust the MII clock vs. data timing. + If this property is not present the delay is determined by + the interface mode. maintainers:- Hauke Mehrtens <[email protected]>
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +3
-1@@ -113,8 +136,10 @@ examples: port@0 { reg = <0>; label = "lan3"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; }; port@1 {Signature · 1 line
2.51.2
Rob Herring
maintainerRe: [PATCH net-next v5 06/12] dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
Quoted 32 lines · Rob Herring
Quoted 31 lines · Daniel Golle
Add support for standard tx-internal-delay-ps and rx-internal-delay-ps properties on port nodes to allow fine-tuning of RGMII clock delays.
The GSWIP switch hardware supports delay values in 500 picosecond increments from 0 to 3500 picoseconds, with a post-reset default of 2000 picoseconds for both TX and RX delays. The driver currently sets the delay to 0 in case the PHY is setup to carry out the delay by the corresponding interface modes ("rgmii-id", "rgmii-rxid", "rgmii-txid").
This corresponds to the driver changes that allow adjusting MII delays using Device Tree properties instead of relying solely on the PHY interface mode.
Signed-off-by Daniel Golle <[email protected]>---
v4:
* remove misleading defaultsv3:
* redefine ports node so properties are defined actually apply
* RGMII port with 2ps delay is 'rgmii-id' mode.../bindings/net/dsa/lantiq,gswip.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-0@@ -6,8 +6,31 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
Quoted 6 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml $schema: http://devicetree.org/meta-schemas/core.yaml# · line 10
Quoted 4 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-2title: Lantiq GSWIP Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-portsI think you can keep this as you aren't adding custom properties.
Nevermind, I see the next patch now...
Re: [PATCH net-next v5 06/12] dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
Quoted 33 lines · Rob Herring
Quoted 32 lines · Rob Herring
Quoted 31 lines · Daniel Golle
Add support for standard tx-internal-delay-ps and rx-internal-delay-ps properties on port nodes to allow fine-tuning of RGMII clock delays.
The GSWIP switch hardware supports delay values in 500 picosecond increments from 0 to 3500 picoseconds, with a post-reset default of 2000 picoseconds for both TX and RX delays. The driver currently sets the delay to 0 in case the PHY is setup to carry out the delay by the corresponding interface modes ("rgmii-id", "rgmii-rxid", "rgmii-txid").
This corresponds to the driver changes that allow adjusting MII delays using Device Tree properties instead of relying solely on the PHY interface mode.
Signed-off-by Daniel Golle <[email protected]>---
v4:
* remove misleading defaultsv3:
* redefine ports node so properties are defined actually apply
* RGMII port with 2ps delay is 'rgmii-id' mode.../bindings/net/dsa/lantiq,gswip.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-0@@ -6,8 +6,31 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
Quoted 8 lines
Quoted 6 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml $schema: http://devicetree.org/meta-schemas/core.yaml# · line 10
Quoted 4 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-2title: Lantiq GSWIP Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-portsI think you can keep this as you aren't adding custom properties.
Nevermind, I see the next patch now...
I suppose you mean [08/12] ("dt-bindings: net: dsa: lantiq,gswip: add MaxLinear RMII refclk output property"), right?
The intention to divert from dsa.yaml#/$defs/ethernet-ports already in this patch was to enforce the possible values of {rx,tx}-internal-delay-ps.
Anyway, so you are saying I can keep the change in this patch? Or should I just drop the constraints on the possible values of the delays and only divert from dsa.yaml#/$defs/ethernet-ports once I'm actually adding maxlinear,rmii-refclk-out?
Rob Herring
maintainerRe: [PATCH net-next v5 06/12] dt-bindings: net: dsa: lantiq,gswip: add support for MII delay properties
Quoted 46 lines · Daniel Golle
Quoted 33 lines · Rob Herring
Quoted 32 lines · Rob Herring
Quoted 31 lines · Daniel Golle
Add support for standard tx-internal-delay-ps and rx-internal-delay-ps properties on port nodes to allow fine-tuning of RGMII clock delays.
The GSWIP switch hardware supports delay values in 500 picosecond increments from 0 to 3500 picoseconds, with a post-reset default of 2000 picoseconds for both TX and RX delays. The driver currently sets the delay to 0 in case the PHY is setup to carry out the delay by the corresponding interface modes ("rgmii-id", "rgmii-rxid", "rgmii-txid").
This corresponds to the driver changes that allow adjusting MII delays using Device Tree properties instead of relying solely on the PHY interface mode.
Signed-off-by Daniel Golle <[email protected]>---
v4:
* remove misleading defaultsv3:
* redefine ports node so properties are defined actually apply
* RGMII port with 2ps delay is 'rgmii-id' mode.../bindings/net/dsa/lantiq,gswip.yaml | 31 +++++++++++++++++-- 1 file changed, 28 insertions(+), 3 deletions(-)Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-0@@ -6,8 +6,31 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#Quoted 8 lines
Quoted 6 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml $schema: http://devicetree.org/meta-schemas/core.yaml# · line 10
Quoted 4 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-2title: Lantiq GSWIP Ethernet switches -allOf: - - $ref: dsa.yaml#/$defs/ethernet-portsI think you can keep this as you aren't adding custom properties.
Nevermind, I see the next patch now...
I suppose you mean [08/12] ("dt-bindings: net: dsa: lantiq,gswip: add MaxLinear RMII refclk output property"), right?
Quoted 8 lines
The intention to divert from dsa.yaml#/$defs/ethernet-ports already in this patch was to enforce the possible values of {rx,tx}-internal-delay-ps.
Anyway, so you are saying I can keep the change in this patch? Or should I just drop the constraints on the possible values of the delays and only divert from dsa.yaml#/$defs/ethernet-ports once I'm actually adding maxlinear,rmii-refclk-out?
You can keep it as-is, but strictly speaking, some of what's here is only needed for [08/12]. Perhaps reverse the order of the patches. Then it would be most of the changes here with the maxlinear,rmii-refclk-out added, and then the 2nd patch is constraints on {rx,tx}-internal-delay-ps.
Rob
PATCH v5 7/12 net: dsa: lantiq_gswip: allow adjusting MII delays
In reply to Daniel GolleCurrently the MII clk vs. data delay is configured based on the PHY interface mode.
In addition to that add support for setting up MII delays using the standard Device Tree properties 'tx-internal-delay-ps' and 'rx-internal-delay-ps', using the values determined by the PHY interface mode as default to maintain backward compatibility with legacy device trees.
---
v4: rework to use legacy codepath as fallback
drivers/net/dsa/lantiq/lantiq_gswip.h | 4 + drivers/net/dsa/lantiq/lantiq_gswip_common.c | 94 ++++++++++++-------- 2 files changed, 60 insertions(+), 38 deletions(-)
drivers/net/dsa/lantiq/lantiq_gswip.h +4 -0
@@ -82,6 +82,10 @@#define GSWIP_MII_PCDU5 0x05#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) +#define GSWIP_MII_PCDU_TXDLY (x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_TXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY (x) u16_encode_bits(((x) / 500), GSWIP_MII_PCDU_RXDLY_MASK) +#define GSWIP_MII_PCDU_RXDLY_DEFAULT 2000/* picoseconds */ +#define GSWIP_MII_PCDU_TXDLY_DEFAULT 2000/* picoseconds */ /* GSWIP Core Registers */ #define GSWIP_SWRES 0x000
drivers/net/dsa/lantiq/lantiq_gswip_common.c +56 -38
112 lines not on this page · raw message
Signature · 1 line
2.51.2
PATCH v5 8/12 dt-bindings: net: dsa: lantiq,gswip: add MaxLinear RMII refclk output property
In reply to Daniel GolleAdd support for the maxlinear,rmii-refclk-out boolean property on port nodes to configure the RMII reference clock to be an output rather than an input.
This property is only applicable for ports in RMII mode and allows the switch to provide the reference clock for RMII-connected PHYs instead of requiring an external clock source.
This corresponds to the driver changes that read this Device Tree property to configure the RMII clock direction.
--- Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml | 5 +++++ 1 file changed, 5 insertions(+)
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +5 -0
@@ -31,6 +31,11 @@ patternProperties: The delay lines adjust the MII clock vs. data timing. If this property is not present the delay is determined by the interface mode. + maxlinear,rmii-refclk-out: + type: boolean + description: + Configure the RMII reference clock to be a clock output + rather than an input. Only applicable for RMII mode. maintainers: - Hauke Mehrtens <[email protected]>
Signature · 1 line
2.51.2
PATCH v5 9/12 net: dsa: lantiq_gswip: add vendor property to setup MII refclk output
In reply to Daniel GolleRead boolean Device Tree property "maxlinear,rmii-refclk-out" and switch the RMII reference clock to be a clock output rather than an input if it is set.
---
v4: set GSWIP_MII_CFG_RMII_CLK bit in RMII case inside the switch
statement instead of a (wrong) if-clause just below
drivers/net/dsa/lantiq/lantiq_gswip_common.c | 2 ++ 1 file changed, 2 insertions(+)
drivers/net/dsa/lantiq/lantiq_gswip_common.c +2 -0
@@ -1433,6 +1433,8 @@ static void gswip_phylink_mac_config(struct phylink_config *config,break ;case PHY_INTERFACE_MODE_RMII : miicfg |=GSWIP_MII_CFG_MODE_RMIIM ; +if (of_property_read_bool (dp->dn,"maxlinear,rmii-refclk-out" )) + miicfg |=GSWIP_MII_CFG_RMII_CLK ;break ;case PHY_INTERFACE_MODE_RGMII :case PHY_INTERFACE_MODE_RGMII_ID :
Signature · 1 line
2.51.2
PATCH v5 10/12 dt-bindings: net: dsa: lantiq,gswip: add support for MaxLinear GSW1xx switches
In reply to Daniel GolleExtend the Lantiq GSWIP device tree binding to also cover MaxLinear GSW1xx switches which are based on the same hardware IP but connected via MDIO instead of being memory-mapped.
Add compatible strings for MaxLinear GSW120, GSW125, GSW140, GSW141, and GSW145 switches and adjust the schema to handle the different connection methods with conditional properties.
Add MaxLinear GSW125 example showing MDIO-connected configuration.
---
v5:
* drop maxlinear,rx-inverted from example
v4:
* drop maxlinear,rx-inverted and maxlinear,tx-inverted properties for now in favor of upcoming generic properties
v3:
* add maxlinear,rx-inverted and maxlinear,tx-inverted properties
v2:
* remove git conflict left-overs which somehow creeped in
* indent example with 4 spaces instead of tabs
.../bindings/net/dsa/lantiq,gswip.yaml | 266 +++++++++++++----- 1 file changed, 193 insertions(+), 73 deletions(-)
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +193 -73
@@ -4,7 +4,12 @@ $id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lantiq GSWIP Ethernet switches +title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches + +description: + Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP. + Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O, + while MaxLinear switches are standalone ICs connected via MDIO. $ref: dsa.yaml#
@@ -37,6 +42,100 @@ patternProperties: Configure the RMII reference clock to be a clock output rather than an input. Only applicable for RMII mode. +allOf: + - if: + properties: + compatible: + contains: + enum: + - lantiq,xrx200-gswip + - lantiq,xrx300-gswip + - lantiq,xrx330-gswip + then: + properties: + reg: + minItems: 3 + maxItems: 3 + description: Memory-mapped register regions (switch, mdio, mii) + reg-names: + items: + - const: switch + - const: mdio + - const: mii + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + + properties: + compatible: + const: lantiq,xrx200-mdio + + required: + - compatible + gphy-fw: + type: object + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + compatible: + items: + - enum: + - lantiq,xrx200-gphy-fw + - lantiq,xrx300-gphy-fw + - lantiq,xrx330-gphy-fw + - const: lantiq,gphy-fw + + lantiq,rcu: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the RCU syscon + + patternProperties: + "^gphy@[0-9a-f]{1,2}$": + type: object + + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 255 + description: + Offset of the GPHY firmware register in the RCU register + range + + resets: + items: + - description: GPHY reset line + + reset-names: + items: + - const: gphy + + required: + - reg + + required: + - compatible + - lantiq,rcu + + additionalProperties: false + required: + - reg-names + else: + properties: + reg: + maxItems: 1 + description: MDIO bus address + reg-names: false + gphy-fw: false + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + maintainers: - Hauke Mehrtens <[email protected]>
@@ -46,78 +145,11 @@ properties: - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip - - reg: - minItems: 3 - maxItems: 3 - - reg-names: - items: - - const: switch - - const: mdio - - const: mii - - mdio: - $ref: /schemas/net/mdio.yaml# - unevaluatedProperties: false - - properties: - compatible: - const: lantiq,xrx200-mdio - - required: - - compatible - - gphy-fw: - type: object - properties: - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - compatible: - items: - - enum: - - lantiq,xrx200-gphy-fw - - lantiq,xrx300-gphy-fw - - lantiq,xrx330-gphy-fw - - const: lantiq,gphy-fw - - lantiq,rcu: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the RCU syscon - - patternProperties: - "^gphy@[0-9a-f]{1,2}$": - type: object - - additionalProperties: false - - properties: - reg: - minimum: 0 - maximum: 255 - description: - Offset of the GPHY firmware register in the RCU register range - - resets: - items: - - description: GPHY reset line - - reset-names: - items: - - const: gphy - - required: - - reg - - required: - - compatible - - lantiq,rcu - - additionalProperties: false + - maxlinear,gsw120 + - maxlinear,gsw125 + - maxlinear,gsw140 + - maxlinear,gsw141 + - maxlinear,gsw145 required: - compatible
@@ -132,6 +164,7 @@ examples: reg = <0xe108000 0x3100>, /* switch */ <0xe10b100 0xd8>, /* mdio */ <0xe10b1d8 0x130>; /* mii */ + reg-names = "switch", "mdio", "mii"; dsa,member = <0 0>; ports {
@@ -230,3 +263,90 @@ examples: }; }; }; + + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@1f { + compatible = "maxlinear,gsw125"; + reg = <0x1f>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan0"; + phy-handle = <&switchphy0>; + phy-mode = "internal"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + phy-handle = <&switchphy1>; + phy-mode = "internal"; + }; + + port@4 { + reg = <4>; + label = "wan"; + phy-mode = "1000base-x"; + managed = "in-band-status"; + }; + + port@5 { + reg = <5>; + phy-mode = "rgmii-id"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2000>; + ethernet = <ð0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switchphy0: switchphy@0 { + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + }; + }; + }; + + switchphy1: switchphy@1 { + reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + }; + }; + }; + }; + }; + };
Signature · 1 line
2.51.2
Rob Herring
maintainerRe: [PATCH net-next v5 10/12] dt-bindings: net: dsa: lantiq,gswip: add support for MaxLinear GSW1xx switches
Quoted 212 lines · Daniel Golle
Extend the Lantiq GSWIP device tree binding to also cover MaxLinear GSW1xx switches which are based on the same hardware IP but connected via MDIO instead of being memory-mapped.
Add compatible strings for MaxLinear GSW120, GSW125, GSW140, GSW141, and GSW145 switches and adjust the schema to handle the different connection methods with conditional properties.
Add MaxLinear GSW125 example showing MDIO-connected configuration.
Signed-off-by Daniel Golle <[email protected]>---
v5:
* drop maxlinear,rx-inverted from examplev4:
* drop maxlinear,rx-inverted and maxlinear,tx-inverted properties for now in favor of upcoming generic propertiesv3:
* add maxlinear,rx-inverted and maxlinear,tx-inverted propertiesv2:
* remove git conflict left-overs which somehow creeped in
* indent example with 4 spaces instead of tabs.../bindings/net/dsa/lantiq,gswip.yaml | 266 +++++++++++++----- 1 file changed, 193 insertions(+), 73 deletions(-)Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +100
-61@@ -4,7 +4,12 @@ $id: http://devicetree.org/schemas/net/dsa/lantiq,gswip.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Lantiq GSWIP Ethernet switches +title: Lantiq GSWIP and MaxLinear GSW1xx Ethernet switches + +description: + Lantiq GSWIP and MaxLinear GSW1xx switches share the same hardware IP. + Lantiq switches are embedded in SoCs and accessed via memory-mapped I/O, + while MaxLinear switches are standalone ICs connected via MDIO. $ref: dsa.yaml#@@ -37,6 +42,100 @@ patternProperties: Configure the RMII reference clock to be a clock output rather than an input. Only applicable for RMII mode. +allOf: + - if: + properties: + compatible: + contains: + enum: + - lantiq,xrx200-gswip + - lantiq,xrx300-gswip + - lantiq,xrx330-gswip + then: + properties: + reg: + minItems: 3 + maxItems: 3 + description: Memory-mapped register regions (switch, mdio, mii) + reg-names: + items: + - const: switch + - const: mdio + - const: mii + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + + properties: + compatible: + const: lantiq,xrx200-mdio + + required: + - compatible + gphy-fw: + type: object + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + compatible: + items: + - enum: + - lantiq,xrx200-gphy-fw + - lantiq,xrx300-gphy-fw + - lantiq,xrx330-gphy-fw + - const: lantiq,gphy-fw + + lantiq,rcu: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the RCU syscon + + patternProperties: + "^gphy@[0-9a-f]{1,2}$": + type: object + + additionalProperties: false + + properties: + reg: + minimum: 0 + maximum: 255 + description: + Offset of the GPHY firmware register in the RCU register + range + + resets: + items: + - description: GPHY reset line + + reset-names: + items: + - const: gphy + + required: + - reg + + required: + - compatible + - lantiq,rcu + + additionalProperties: false + required: + - reg-names + else: + properties: + reg: + maxItems: 1 + description: MDIO bus address + reg-names: false + gphy-fw: false + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + maintainers: - Hauke Mehrtens <[email protected]>@@ -46,78 +145,11 @@ properties: - lantiq,xrx200-gswip - lantiq,xrx300-gswip - lantiq,xrx330-gswip - - reg: - minItems: 3 - maxItems: 3 - - reg-names: - items: - - const: switch - - const: mdio - - const: mii - - mdio: - $ref: /schemas/net/mdio.yaml# - unevaluatedProperties: false - - properties: - compatible: - const: lantiq,xrx200-mdio - - required: - - compatible - - gphy-fw: - type: object - properties: - '#address-cells': - const: 1 - - '#size-cells': - const: 0 - - compatible: - items: - - enum: - - lantiq,xrx200-gphy-fw - - lantiq,xrx300-gphy-fw - - lantiq,xrx330-gphy-fw - - const: lantiq,gphy-fw - - lantiq,rcu: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to the RCU syscon - - patternProperties: - "^gphy@[0-9a-f]{1,2}$": - type: object - - additionalProperties: false - - properties: - reg: - minimum: 0 - maximum: 255 - description: - Offset of the GPHY firmware register in the RCU register range - - resets: - items: - - description: GPHY reset line -
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml properties: · line 118
Quoted 10 lines
Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml +0
-10- reset-names: - items: - - const: gphy - - required: - - reg - - required: - - compatible - - lantiq,rcu
All this should remain rather than being under an if/then schema. If you need something so different, then it should probably be a separate schema file. If there's some common parts, then a common schema shared between 2 or more specific bindings.
Rob
PATCH v5 11/12 net: dsa: add tagging driver for MaxLinear GSW1xx switch family
In reply to Daniel GolleAdd support for a new DSA tagging protocol driver for the MaxLinear GSW1xx switch family. The GSW1xx switches use a proprietary 8-byte special tag inserted between the source MAC address and the EtherType field to indicate the source and destination ports for frames traversing the CPU port.
Implement the tag handling logic to insert the special tag on transmit and parse it on receive.
---
v5:
* reduce length of overly long line
v4:
* use __be16 to access tag fields
* define ETH_P_MXLGSW in if_ether.h
* drop *_SHIFT macros, get rid of _MASK suffix, use FIELD helpers
* print tag using %8ph
since RFC:
* use dsa etype header macros instead of open coding them
* maintain alphabetic order in Kconfig and Makefile
MAINTAINERS | 3 +- include/net/dsa.h | 2 + include/uapi/linux/if_ether.h | 1 + net/dsa/Kconfig | 8 +++ net/dsa/Makefile | 1 + net/dsa/tag_mxl-gsw1xx.c | 116 ++++++++++++++++++++++++++++++++++ 6 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 net/dsa/tag_mxl-gsw1xx.c
MAINTAINERS +2 -1
@@ -14038,7 +14038,7 @@ F: tools/testing/selftests/landlock/ K: landlock K: LANDLOCK -LANTIQ / INTEL Ethernet drivers +LANTIQ / MAXLINEAR / INTEL Ethernet DSA drivers M: Hauke Mehrtens <[email protected]> L: [email protected] S: Maintained
@@ -14046,6 +14046,7 @@ F: Documentation/devicetree/bindings/net/dsa/lantiq,gswip.yaml F: drivers/net/dsa/lantiq/* F: drivers/net/ethernet/lantiq_xrx200.c F: net/dsa/tag_gswip.c +F: net/dsa/tag_mxl-gsw1xx.c LANTIQ MIPS ARCHITECTURE M: John Crispin <[email protected]>
include/net/dsa.h +2 -0
@@ -56,6 +56,7 @@ struct tc_action;#define DSA_TAG_PROTO_VSC73XX_8021Q_VALUE 28#define DSA_TAG_PROTO_BRCM_LEGACY_FCS_VALUE 29#define DSA_TAG_PROTO_YT921X_VALUE 30 +#define DSA_TAG_PROTO_MXL_GSW1XX_VALUE 31enum dsa_tag_protocol {DSA_TAG_PROTO_NONE =DSA_TAG_PROTO_NONE_VALUE ,
@@ -89,6 +90,7 @@ enum dsa_tag_protocol {DSA_TAG_PROTO_LAN937X =DSA_TAG_PROTO_LAN937X_VALUE ,DSA_TAG_PROTO_VSC73XX_8021Q =DSA_TAG_PROTO_VSC73XX_8021Q_VALUE ,DSA_TAG_PROTO_YT921X =DSA_TAG_PROTO_YT921X_VALUE , + DSA_TAG_PROTO_MXL_GSW1XX = DSA_TAG_PROTO_MXL_GSW1XX_VALUE, };struct dsa_switch ;
include/uapi/linux/if_ether.h +1 -0
@@ -92,6 +92,7 @@#define ETH_P_ETHERCAT 0x88A4/* EtherCAT */ #define ETH_P_8021AD 0x88A8/* 802.1ad Service VLAN */ #define ETH_P_802_EX1 0x88B5/* 802.1 Local Experimental 1. */ +#define ETH_P_MXLGSW 0x88C3/* MaxLinear GSW DSA [ NOT AN OFFICIALLY REGISTERED ID ] */ #define ETH_P_PREAUTH 0x88C7/* 802.11 Preauthentication */ #define ETH_P_TIPC 0x88CA/* TIPC */ #define ETH_P_LLDP 0x88CC/* Link Layer Discovery Protocol */
net/dsa/Kconfig +8 -0
@@ -104,6 +104,14 @@ config NET_DSA_TAG_MTK Say Y or M if you want to enable support for tagging frames for Mediatek switches. +config NET_DSA_TAG_MXL_GSW1XX + tristate "Tag driver for MaxLinear GSW1xx switches" + help + The GSW1xx family of switches supports an 8-byte special tag which + can be used on the CPU port of the switch. + Say Y or M if you want to enable support for tagging frames for + MaxLinear GSW1xx switches. + config NET_DSA_TAG_KSZ tristate "Tag driver for Microchip 8795/937x/9477/9893 families of switches" help
net/dsa/Makefile +1 -0
@@ -28,6 +28,7 @@ obj-$(CONFIG_NET_DSA_TAG_HELLCREEK) += tag_hellcreek.o obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o +obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o obj-$(CONFIG_NET_DSA_TAG_NONE) += tag_none.o obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
net/dsa/tag_mxl-gsw1xx.c new file +116 -0
116 lines not on this page · raw message
Signature · 1 line
2.51.2
PATCH v5 12/12 net: dsa: add driver for MaxLinear GSW1xx switch family
In reply to Daniel GolleAdd driver for the MaxLinear GSW1xx family of Ethernet switch ICs which are based on the same IP as the Lantiq/Intel GSWIP found in the Lantiq VR9 and Intel GRX MIPS router SoCs. The main difference is that instead of using memory-mapped I/O to communicate with the host CPU these ICs are connected via MDIO (or SPI, which isn't supported by this driver). Implement the regmap API to access the switch registers over MDIO to allow reusing lantiq_gswip_common for all core functionality.
The GSW1xx also comes with a SerDes port capable of 1000Base-X, SGMII and 2500Base-X, which can either be used to connect an external PHY or SFP cage, or as the CPU port. Support for the SerDes interface is implemented in this driver using the phylink_pcs interface.
---
v4:
* break out PCS reset into dedicated function
* drop hacky support for reverse-SGMII
* remove again the custom properties for TX and RX inverted SerDes PCS in favor of waiting for generic properties to land
v3:
* avoid disrupting link when calling .pcs_config()
* sort functions and phylink_pcs_ops instance in same order as struct definition
* always set bootstrap override bits and add explanatory comment
* move definitions to separate header file
* add custom properties for TX and RX inverted data on the SerDes interface
v2: remove left-overs of 4k VLAN support (will be added in future)
drivers/net/dsa/lantiq/Kconfig | 12 + drivers/net/dsa/lantiq/Makefile | 1 + drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 733 ++++++++++++++++++++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.h | 126 ++++ drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h | 154 +++++ 6 files changed, 1027 insertions(+) create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.c create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx.h create mode 100644 drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h
drivers/net/dsa/lantiq/Kconfig +12 -0
@@ -10,3 +10,15 @@ config NET_DSA_LANTIQ_GSWIP help This enables support for the Lantiq / Intel GSWIP 2.1 found in the xrx200 / VR9 SoC. + +config NET_DSA_MXL_GSW1XX + tristate "MaxLinear GSW1xx Ethernet switch support" + select NET_DSA_TAG_MXL_GSW1XX + select NET_DSA_LANTIQ_COMMON + help + This enables support for the MaxLinear GSW1xx family of 1GE switches + GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X + GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperature + GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X + GSW141 6 port, 4 PHYs, RGMII & SGMII + GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperature
drivers/net/dsa/lantiq/Makefile +1 -0
@@ -1,2 +1,3 @@ obj-$(CONFIG_NET_DSA_LANTIQ_GSWIP) += lantiq_gswip.o obj-$(CONFIG_NET_DSA_LANTIQ_COMMON) += lantiq_gswip_common.o +obj-$(CONFIG_NET_DSA_MXL_GSW1XX) += mxl-gsw1xx.o
drivers/net/dsa/lantiq/lantiq_gswip.h +1 -0
@@ -255,6 +255,7 @@ struct gswip_hw_info {unsigned int allowed_cpu_ports;unsigned int mii_ports;int mii_port_reg_offset; +bool supports_2500m;const struct gswip_pce_microcode (*pce_microcode)[];size_t pce_microcode_size;enum dsa_tag_protocol tag_protocol;
drivers/net/dsa/lantiq/mxl-gsw1xx.c new file +733 -0
733 lines not on this page · raw message
drivers/net/dsa/lantiq/mxl-gsw1xx.h new file +126 -0
126 lines not on this page · raw message
drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h new file +154 -0
154 lines not on this page · raw message
Signature · 1 line
2.51.2
Re: [PATCH net-next v5 12/12] net: dsa: add driver for MaxLinear GSW1xx switch family
Hi Daniel,
Quoted 38 lines · Daniel Golle
Add driver for the MaxLinear GSW1xx family of Ethernet switch ICs which are based on the same IP as the Lantiq/Intel GSWIP found in the Lantiq VR9 and Intel GRX MIPS router SoCs. The main difference is that instead of using memory-mapped I/O to communicate with the host CPU these ICs are connected via MDIO (or SPI, which isn't supported by this driver). Implement the regmap API to access the switch registers over MDIO to allow reusing
lantiq_gswip_commonfor all core functionality.The GSW1xx also comes with a SerDes port capable of 1000Base-X, SGMII and 2500Base-X, which can either be used to connect an external PHY or SFP cage, or as the CPU port. Support for the SerDes interface is implemented in this driver using the
phylink_pcsinterface.Signed-off-by Daniel Golle <[email protected]>---
v4:
* break out PCS reset into dedicated function
* drop hacky support for reverse-SGMII
* remove again the custom properties for TX and RX inverted SerDes PCS in favor of waiting for generic properties to landv3:
* avoid disrupting link when calling .pcs_config()
* sort functions andphylink_pcs_opsinstance in same order as struct definition
* always set bootstrap override bits and add explanatory comment
* move definitions to separate header file
* add custom properties for TX and RX inverted data on the SerDes interfacev2: remove left-overs of 4k VLAN support (will be added in future)
drivers/net/dsa/lantiq/Kconfig | 12 + drivers/net/dsa/lantiq/Makefile | 1 + drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + drivers/net/dsa/lantiq/mxl-gsw1xx.c | 733 ++++++++++++++++++++++++ drivers/net/dsa/lantiq/mxl-gsw1xx.h | 126 ++++
drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h| 154 +++++
Quoted 4 lines
6 files changed, 1027 insertions(+)create mode 100644
drivers/net/dsa/lantiq/mxl-gsw1xx.ccreate mode 100644drivers/net/dsa/lantiq/mxl-gsw1xx.hcreate mode 100644drivers/net/dsa/lantiq/mxl-gsw1xx_pce.h
thank you for the patch!
For some reason with both v4 and v5 I can reliably reproduce the following warning (ASSERT_RTNL()) at the very beginning of drivers/net/dsa/local_termination.sh selftest:
RTNL: assertion failed at git/net/core/dev.c (9480)
WARNING: CPU: 1 PID: 529 at git/net/core/dev.c:9480 __dev_set_promiscuity+0x174/0x188 CPU: 1 UID: 996 PID: 529 Comm: systemd-resolve Tainted: G O 6.18.0-rc2+gite9079300094d #1 PREEMPT pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __dev_set_promiscuity+0x174/0x188 lr : __dev_set_promiscuity+0x174/0x188 Call trace: __dev_set_promiscuity+0x174/0x188 (P) __dev_set_rx_mode+0xa0/0xb0 dev_mc_del+0x94/0xc0 igmp6_group_dropped+0x124/0x410 __ipv6_dev_mc_dec+0x108/0x168 __ipv6_sock_mc_drop+0x64/0x188 ipv6_sock_mc_drop+0x140/0x170 do_ipv6_setsockopt+0x1408/0x1828 ipv6_setsockopt+0x64/0xf8 udpv6_setsockopt+0x28/0x58 sock_common_setsockopt+0x24/0x38 do_sock_setsockopt+0x78/0x158 __sys_setsockopt+0x88/0x110 __arm64_sys_setsockopt+0x30/0x48 invoke_syscall+0x50/0x120 el0_svc_common.constprop.0+0xc8/0xf0 do_el0_svc+0x24/0x38 el0_svc+0x50/0x2b0 el0t_64_sync_handler+0xa0/0xe8 el0t_64_sync+0x198/0x1a0
(testing with GSW145)
I'm not sure though, if it's related to the gsw1xx code, am65-cpsw-nuss driver on my CPU port or if it's a fresh regression in net-next...
I can see the above splat if I apply the patchset onto bfe62db5422b1a5f25752bd0877a097d436d876d but not with older patchset on top of e90576829ce47a46838685153494bc12cd1bc333.
I'll try to bisect the underlying net-next...
Signature · 3 lines
Alexander Sverdlin Siemens AG www.siemens.com
Re: [PATCH net-next v5 12/12] net: dsa: add driver for MaxLinear GSW1xx switch family
Quoted 33 lines · Alexander
[...]
For some reason with both v4 and v5 I can reliably reproduce the following warning (ASSERT_RTNL()) at the very beginning ofdrivers/net/dsa/local_termination.shselftest:RTNL: assertion failed at
git/net/core/dev.c(9480)WARNING: CPU: 1 PID: 529 at git/net/core/dev.c:9480 __dev_set_promiscuity+0x174/0x188 CPU: 1 UID: 996 PID: 529 Comm: systemd-resolve Tainted: G O 6.18.0-rc2+gite9079300094d #1 PREEMPT pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __dev_set_promiscuity+0x174/0x188 lr : __dev_set_promiscuity+0x174/0x188 Call trace: __dev_set_promiscuity+0x174/0x188 (P) __dev_set_rx_mode+0xa0/0xb0 dev_mc_del+0x94/0xc0 igmp6_group_dropped+0x124/0x410 __ipv6_dev_mc_dec+0x108/0x168 __ipv6_sock_mc_drop+0x64/0x188 ipv6_sock_mc_drop+0x140/0x170 do_ipv6_setsockopt+0x1408/0x1828 ipv6_setsockopt+0x64/0xf8 udpv6_setsockopt+0x28/0x58 sock_common_setsockopt+0x24/0x38 do_sock_setsockopt+0x78/0x158 __sys_setsockopt+0x88/0x110 __arm64_sys_setsockopt+0x30/0x48 invoke_syscall+0x50/0x120 el0_svc_common.constprop.0+0xc8/0xf0 do_el0_svc+0x24/0x38 el0_svc+0x50/0x2b0 el0t_64_sync_handler+0xa0/0xe8 el0t_64_sync+0x198/0x1a0
Quoted 8 lines
(testing with GSW145)
I'm not sure though, if it's related to the gsw1xx code, am65-cpsw-nuss driver on my CPU port or if it's a fresh regression in net-next...I can see the above splat if I apply the patchset onto
bfe62db5422b1a5f25752bd0877a097d436d876dbut not with older patchset on top ofe90576829ce47a46838685153494bc12cd1bc333.I'll try to bisect the underlying net-next...
Did you try to rebase the patches necessary for the GSW145 on top of the last known-to-work net-next commit?
Also note that I've successfully tested local_termination.sh on top of ea7d0d60ebc9bddf3ad768557dfa1495bc032bf6, but using the modified RaspberryPi 4B provided by MaxLinear, so there obviously is a different Ethernet driver on the CPU port...
Re: [PATCH net-next v5 12/12] net: dsa: add driver for MaxLinear GSW1xx switch family
Hi Daniel,
Quoted 43 lines · Daniel Golle
Quoted 33 lines · Alexander
[...]
For some reason with both v4 and v5 I can reliably reproduce the following warning (ASSERT_RTNL()) at the very beginning ofdrivers/net/dsa/local_termination.shselftest:RTNL: assertion failed at
git/net/core/dev.c(9480)WARNING: CPU: 1 PID: 529 at git/net/core/dev.c:9480 __dev_set_promiscuity+0x174/0x188 CPU: 1 UID: 996 PID: 529 Comm: systemd-resolve Tainted: G O 6.18.0-rc2+gite9079300094d #1 PREEMPT pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __dev_set_promiscuity+0x174/0x188 lr : __dev_set_promiscuity+0x174/0x188 Call trace: __dev_set_promiscuity+0x174/0x188 (P) __dev_set_rx_mode+0xa0/0xb0 dev_mc_del+0x94/0xc0 igmp6_group_dropped+0x124/0x410 __ipv6_dev_mc_dec+0x108/0x168 __ipv6_sock_mc_drop+0x64/0x188 ipv6_sock_mc_drop+0x140/0x170 do_ipv6_setsockopt+0x1408/0x1828 ipv6_setsockopt+0x64/0xf8 udpv6_setsockopt+0x28/0x58 sock_common_setsockopt+0x24/0x38 do_sock_setsockopt+0x78/0x158 __sys_setsockopt+0x88/0x110 __arm64_sys_setsockopt+0x30/0x48 invoke_syscall+0x50/0x120 el0_svc_common.constprop.0+0xc8/0xf0 do_el0_svc+0x24/0x38 el0_svc+0x50/0x2b0 el0t_64_sync_handler+0xa0/0xe8 el0t_64_sync+0x198/0x1a0Quoted 8 lines
(testing with GSW145)
I'm not sure though, if it's related to the gsw1xx code, am65-cpsw-nuss driver on my CPU port or if it's a fresh regression in net-next...I can see the above splat if I apply the patchset onto
bfe62db5422b1a5f25752bd0877a097d436d876dbut not with older patchset on top ofe90576829ce47a46838685153494bc12cd1bc333.I'll try to bisect the underlying net-next...
Quoted 7 lines
Did you try to rebase the patches necessary for the GSW145 on top of the last known-to-work net-next commit?
Also note that I've successfully tested
local_termination.shon top ofea7d0d60ebc9bddf3ad768557dfa1495bc032bf6, but using the modified RaspberryPi 4B provided by MaxLinear, so there obviously is a different Ethernet driver on the CPU port...
I'll need to follow up on this... It turned out to be not that reliable reproducible, so my bisect led me to nowhere.
I don't think this is related to GSW145 code (even though it's being triggered by GSW145 port going down), only core code seems to be involved here... And I see quite some RTNL have been dropped in the net-next...
Signature · 3 lines
Alexander Sverdlin Siemens AG www.siemens.com