dt-bindings: firmware: Add Agilex5 SVC compatible string
Subsystems (2)
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PATCH 1/2 dt-bindings: firmware: Add Agilex5 SVC compatible string
Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by adding the new compatible string "intel,agilex5-svc" in the device tree bindings.
This is needed to differentiate Agilex5 from previous SoC generations, as Agilex5 uses a different mechanism for mapping reserved memory regions, which rely on IOMMU support.
--- .../devicetree/bindings/firmware/intel,stratix10-svc.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml +1 -0
@@ -34,6 +34,7 @@ properties: enum: - intel,stratix10-svc - intel,agilex-svc + - intel,agilex5-svc method: description: |
Signature · 1 line
2.43.7
Quoted 7 lines · Khairul Anuar Romli
Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by adding the new compatible string "intel,agilex5-svc" in the device tree bindings.
This is needed to differentiate Agilex5 from previous SoC generations, as Agilex5 uses a different mechanism for mapping reserved memory regions, which rely on IOMMU support.
There are no iommus here, so this feels inaccurate.
Best regards,
Krzysztof
Quoted 7 lines · Krzysztof Kozlowski
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Quoted 4 lines · Khairul Anuar Romli
Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by adding the new compatible string "intel,agilex5-svc" in the device tree bindings.
Quoted 8 lines
Quoted 3 lines
This is needed to differentiate Agilex5 from previous SoC generations, as Agilex5 uses a different mechanism for mapping reserved memory regions, which rely on IOMMU support.
There are no iommus here, so this feels inaccurate.
Best regards,
Krzysztof
I will remove this on the v2 revision as the iommu is part on future patch series.
Thanks
Khairul
Quoted 12 lines · Khairul Anuar
Quoted 11 lines · Krzysztof Kozlowski
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Quoted 7 lines · Khairul Anuar Romli
Enable support for the Agilex5 in Stratix10 SoC service layer (SVC) by adding the new compatible string "intel,agilex5-svc" in the device tree bindings.
This is needed to differentiate Agilex5 from previous SoC generations, as Agilex5 uses a different mechanism for mapping reserved memory regions, which rely on IOMMU support.
Quoted 8 lines
Quoted 4 lines
There are no iommus here, so this feels inaccurate.
Best regards,
KrzysztofI will remove this on the v2 revision as the iommu is part on future patch series.
No, instead please post complete bindings for this device. So all of the hardware properties. See writing bindings doc.
Best regards,
Krzysztof
PATCH 2/2 arm64: dts: intel: Add Agilex5 SVC node with memory region
In reply to a message not in the archiveIntroduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs. The node includes the compatible string "intel,agilex5-svc" and references a reserved memory region required for communication with the Secure Device Manager (SDM).
Agilex5 introduces a dependency on IOMMU-based translation for reserved memory, unlike prior Agilex platforms. This commit introduces the structural changes needed to support this feature once the IOMMU driver is upstreamed.
--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +9 -0
@@ -841,5 +841,14 @@ queue7 { }; }; }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>; + }; + }; }; };
Signature · 1 line
2.43.7
Re: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region
Quoted 20 lines · Khairul Anuar Romli
Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs. The node includes the compatible string "intel,agilex5-svc" and references a reserved memory region required for communication with the Secure Device Manager (SDM).
Agilex5 introduces a dependency on IOMMU-based translation for reserved memory, unlike prior Agilex platforms. This commit introduces the structural changes needed to support this feature once the IOMMU driver is upstreamed.
Signed-off-by Khairul Anuar Romli <[email protected]>--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi queue7 { · line 850
Quoted 10 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +7
-0@@ -841,5 +841,14 @@ queue7 { }; }; }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>;
You did not test your code.
Plus, where is the driver? Please read submitting patches in DT directory.
Best regards,
Krzysztof
Re: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region
Quoted 35 lines · Krzysztof Kozlowski
Quoted 20 lines · Khairul Anuar Romli
Introduce the Stratix10 SoC service layer (SVC) node for Agilex5 SoCs. The node includes the compatible string "intel,agilex5-svc" and references a reserved memory region required for communication with the Secure Device Manager (SDM).
Agilex5 introduces a dependency on IOMMU-based translation for reserved memory, unlike prior Agilex platforms. This commit introduces the structural changes needed to support this feature once the IOMMU driver is upstreamed.
Signed-off-by Khairul Anuar Romli <[email protected]>--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi queue7 { · line 850
Quoted 10 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +7
-0@@ -841,5 +841,14 @@ queue7 { }; }; }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>;You did not test your code.
Quoted 4 lines
Plus, where is the driver? Please read submitting patches in DT directory.
Best regards,
Krzysztof
I will add the driver implementation in the v2 as part of initial support enablement for this Agilex5.
Thanks
Best Regards,
Khairul
kernel test robot
build botRe: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region
In reply to Khairul Anuar Romlikernel test robot noticed the following build errors:
Hi Khairul,
kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v6.18-rc3 next-20251031] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Khairul-Anuar-Romli/arm64-dts-intel-Add-Agilex5-SVC-node-with-memory-region/20251028-183009 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/a3182556c07839dcd9227fa6a4a9d295507f3e8e.1761643239.git.khairul.anuar.romli%40altera.com patch subject: [PATCH 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region config: arm64-randconfig-002-20251101 (https://download.01.org/0day-ci/archive/20251101/[email protected]/config) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project cc271437553452ede002d871d32abc02084341a8) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251101/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
>> ERROR: Input tree has errors, aborting (use -f to force output)
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki