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clk: mediatek: mt7988-infracfg: fix USB port0 function for U2 only

PATCH In review Frank Wunderlich 2 participants 2 messages Nov 8, 2025

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PATCH 1/1 clk: mediatek: mt7988-infracfg: fix USB port0 function for U2 only

From: Sam Shih <[email protected]>

Fix the functionality of USB port0 U2 when U2 is enabled without U3. This change addresses the issue where port0 U3 is shared with PCIE2, ensuring that the port0 U2 function operates correctly without U3 support.

Additionally, add support to enable the U2 function instead of disabling the entire USB port0 in the configuration for the 4 PCIe case. This change ensures that U2 functionality is properly activated.

Fixes 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
---
 drivers/clk/mediatek/clk-mt7988-infracfg.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/clk/mediatek/clk-mt7988-infracfg.c +3 -2
index ef8267319d91..da4ad365e30f 100644
@@ -229,8 +229,9 @@ static const struct mtk_gate infra_clks[] = {
 			  CLK_IS_CRITICAL),
 	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
 			  9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10, CLK_IS_CRITICAL),
+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11,
+			  CLK_IS_CRITICAL),
 	GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
 	GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", "top_xtal", 13),
 	GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
Signature · 1 line
2.43.0
#1 lore raw
Quoted 22 lines · Frank Wunderlich

From: Sam Shih <[email protected]>

Fix the functionality of USB port0 U2 when U2 is enabled without U3. This change addresses the issue where port0 U3 is shared with PCIE2, ensuring that the port0 U2 function operates correctly without U3 support.

Additionally, add support to enable the U2 function instead of disabling the entire USB port0 in the configuration for the 4 PCIe case. This change ensures that U2 functionality is properly activated.

Fixes 4b4719437d85 ("clk: mediatek: add drivers for MT7988 SoC")
---
 drivers/clk/mediatek/clk-mt7988-infracfg.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
drivers/clk/mediatek/clk-mt7988-infracfg.c +0 -0
index ef8267319d91..da4ad365e30f 100644

drivers/clk/mediatek/clk-mt7988-infracfg.c static const struct mtk_gate infra_clks[] = { · line 234

Quoted 8 lines
drivers/clk/mediatek/clk-mt7988-infracfg.c +3 -2
@@ -229,8 +229,9 @@ static const struct mtk_gate infra_clks[] = {
 			  CLK_IS_CRITICAL),
 	GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", "usb_frmcnt_p1_sel",
 			  9, CLK_IS_CRITICAL),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
-	GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11),
+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10, CLK_IS_CRITICAL),
+	GATE_INFRA3_FLAGS(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", "usb_phy_sel", 11,
+			  CLK_IS_CRITICAL),

I don't agree that those two clocks are critical. There are boards using MT7988 which don't even come with USB at all.
Instead of marking the clock as criticl, the dependency of the USB host on them should be expressed properly.