x86/irq: Bugfix and cleanup for posted MSI interrupts

PATCH Applied Thomas Gleixner 3 participants 11 messages Nov 25, 2025 – Dec 18, 2025

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Stable branch x86 IOMMU Intel IOMMU (VT-d)

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Thomas Gleixner

author

2025-11-25 21:50 UTC #0 lore raw

v2 cover x86/irq: Bugfix and cleanup for posted MSI interrupts

A small update to V1 which can be found here:

https://lore.kernel.org/lkml/[email protected]

Luigi reported that the retrigger mechanism for posted MSI interrupts is broken. That happens because retrigger sends an IPI to the actual allocated vector, which is handled correctly, but lacks an EOI. That leaves a stale APIC ISR bit around.

The following series addresses this and does some related cleanups in that area on top.

Changes vs. V1:

Use __this_cpu_*() - Luigi

Thanks,

tglx

---
 arch/x86/include/asm/irq_remapping.h |   12 ++++++-
 arch/x86/kernel/irq.c                |   54 +++++++++++++++++++++++------------
 drivers/iommu/intel/irq_remapping.c  |   12 +++----
 3 files changed, 52 insertions(+), 26 deletions(-)

Thomas Gleixner

author

2025-11-25 21:50 UTC #1 lore raw

PATCH v2 1/3 x86/msi: Make irq_retrigger() functional for posted MSI

From: Thomas Gleixner <[email protected]>

Luigi reported that retriggering a posted MSI interrupt does not work correctly.

The reason is that the retrigger happens at the vector domain by sending an IPI to the actual vector on the target CPU. That works correctly exactly once because the posted MSI interrupt chip does not issue an EOI as that's only required for the posted MSI notification vector itself.

As a consequence the vector becomes stale in the ISR, which not only affects this vector but also any lower priority vector in the affected APIC because the ISR bit is not cleared.

Luigi proposed to set the vector in the remap PIR bitmap and raise the posted MSI notification vector. That works, but that still does not cure a related problem:

If there is ever a stray interrupt on such a vector, then the related APIC ISR bit becomes stale due to the lack of EOI as described above. Unlikely to happen, but if it happens it's not debuggable at all.

So instead of playing games with the PIR, this can be actually solved for both cases by:

1) Keeping track of the posted interrupt vector handler state

2) Implementing a posted MSI specific irq_ack() callback which checks that state. If the posted vector handler is inactive it issues an EOI, otherwise it delegates that to the posted handler.

This is correct versus affinity changes and concurrent events on the posted vector as the actual handler invocation is serialized through the interrupt descriptor lock.

Fixes ed1e48ea4370 ("iommu/vt-d: Enable posted mode for device MSIs")

Reported-by Luigi Rizzo <[email protected]>

Signed-off-by Thomas Gleixner <[email protected]>

Tested-by Luigi Rizzo <[email protected]>

Cc [email protected]

Closes https://lore.kernel.org/lkml/[email protected] open here

---
V2: Use __this_cpu...() - Luigi

---
 arch/x86/include/asm/irq_remapping.h |    7 +++++++
 arch/x86/kernel/irq.c                |   23 +++++++++++++++++++++++
 drivers/iommu/intel/irq_remapping.c  |    8 ++++----
 3 files changed, 34 insertions(+), 4 deletions(-)

arch/x86/include/asm/irq_remapping.h +7 -0

@@ -87,4 +87,11 @@ static inline void panic_if_irq_remap(co
 }
 
 #endif /* CONFIG_IRQ_REMAP */
+
+#ifdef CONFIG_X86_POSTED_MSI
+void intel_ack_posted_msi_irq(struct irq_data *irqd);
+#else
+#define intel_ack_posted_msi_irq	NULL
+#endif
+
 #endif /* __X86_IRQ_REMAPPING_H */

arch/x86/kernel/irq.c +23 -0

@@ -396,6 +396,7 @@ DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm
 
 /* Posted Interrupt Descriptors for coalesced MSIs to be posted */
 DEFINE_PER_CPU_ALIGNED(struct pi_desc, posted_msi_pi_desc);
+static DEFINE_PER_CPU_CACHE_HOT(bool, posted_msi_handler_active);
 
 void intel_posted_msi_init(void)
 {

@@ -413,6 +414,25 @@ void intel_posted_msi_init(void)
 	this_cpu_write(posted_msi_pi_desc.ndst, destination);
 }
 
+void intel_ack_posted_msi_irq(struct irq_data *irqd)
+{
+	irq_move_irq(irqd);
+
+	/*
+	 * Handle the rare case that irq_retrigger() raised the actual
+	 * assigned vector on the target CPU, which means that it was not
+	 * invoked via the posted MSI handler below. In that case APIC EOI
+	 * is required as otherwise the ISR entry becomes stale and lower
+	 * priority interrupts are never going to be delivered after that.
+	 *
+	 * If the posted handler invoked the device interrupt handler then
+	 * the EOI would be premature because it would acknowledge the
+	 * posted vector.
+	 */
+	if (unlikely(!__this_cpu_read(posted_msi_handler_active)))
+		apic_eoi();
+}
+
 static __always_inline bool handle_pending_pir(unsigned long *pir, struct pt_regs *regs)
 {
 	unsigned long pir_copy[NR_PIR_WORDS];

@@ -445,6 +465,8 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi
 
 	pid = this_cpu_ptr(&posted_msi_pi_desc);
 
+	/* Mark the handler active for intel_ack_posted_msi_irq() */
+	__this_cpu_write(posted_msi_handler_active, true);
 	inc_irq_stat(posted_msi_notification_count);
 	irq_enter();

@@ -473,6 +495,7 @@ DEFINE_IDTENTRY_SYSVEC(sysvec_posted_msi
 
 	apic_eoi();
 	irq_exit();
+	__this_cpu_write(posted_msi_handler_active, false);
 	set_irq_regs(old_regs);
 }
 #endif /* X86_POSTED_MSI */

drivers/iommu/intel/irq_remapping.c +4 -4

@@ -1303,17 +1303,17 @@ static struct irq_chip intel_ir_chip = {
  *	irq_enter();
  *		handle_edge_irq()
  *			irq_chip_ack_parent()
- *				irq_move_irq(); // No EOI
+ *				intel_ack_posted_msi_irq(); // No EOI
  *			handle_irq_event()
  *				driver_handler()
  *		handle_edge_irq()
  *			irq_chip_ack_parent()
- *				irq_move_irq(); // No EOI
+ *				intel_ack_posted_msi_irq(); // No EOI
  *			handle_irq_event()
  *				driver_handler()
  *		handle_edge_irq()
  *			irq_chip_ack_parent()
- *				irq_move_irq(); // No EOI
+ *				intel_ack_posted_msi_irq(); // No EOI
  *			handle_irq_event()
  *				driver_handler()
  *	apic_eoi()

@@ -1322,7 +1322,7 @@ static struct irq_chip intel_ir_chip = {
  */
 static struct irq_chip intel_ir_chip_post_msi = {
 	.name			= "INTEL-IR-POST",
-	.irq_ack		= irq_move_irq,
+	.irq_ack		= intel_ack_posted_msi_irq,
 	.irq_set_affinity	= intel_ir_set_affinity,
 	.irq_compose_msi_msg	= intel_ir_compose_msi_msg,
 	.irq_set_vcpu_affinity	= intel_ir_set_vcpu_affinity,

tip-bot2 for Thomas Gleixner

merge bot Applied

2025-12-17 17:48 UTC #2 lore raw

[tip: x86/urgent] x86/msi: Make irq_retrigger() functional for posted MSI

The following commit has been merged into the x86/urgent branch of tip:

Commit-ID:     0edc78b82bea85e1b2165d8e870a5c3535919695
Gitweb:        https://git.kernel.org/tip/0edc78b82bea85e1b2165d8e870a5c3535919695
Author:        Thomas Gleixner <[email protected]>
AuthorDate:    Tue, 25 Nov 2025 22:50:45 +01:00
Committer:     Thomas Gleixner <[email protected]>
CommitterDate: Wed, 17 Dec 2025 18:41:52 +01:00

x86/msi: Make irq_retrigger() functional for posted MSI