OpenRISC de0 nano single and multicore boards

PATCH Superseded Stafford Horne 2 participants 13 messages Dec 14, 2025 – Dec 16, 2025

Subsystems (4)

Device tree bindings GPIO irqchip drivers Openrisc architecture

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Stafford Horne

author maintainer

2025-12-14 18:02 UTC #0 lore raw

cover OpenRISC de0 nano single and multicore boards

The patches add support for OpenRISC systems running on the De0 Nano FPGA development board. We have two SoCs which are available here:

- https://github.com/olofk/de0_nano - Single core
- https://github.com/stffrdhrn/de0_nano-multicore - Multicore

As I work on tutorials to help other get started with OpenRISC I would like to have these defconfig and devicetree definitions in the upstream kernel to avoid losing them.

When I was working on resurrecting these old setup's I found a major bug in OpenRISC SMP which is fixed in this series as well.

Link https://openrisc.io/tutorials/

Stafford Horne (5):
dt-bindings: Add compatible string opencores,gpio to gpio-mmio
openrisc: dts: Add de0 nano config and devicetree
openrisc: Fix IPIs on simple multicore systems
openrisc: dts: Split simple smp dts to dts and dtsi
openrisc: dts: Add de0 nano multicore config and devicetree

 .../devicetree/bindings/gpio/gpio-mmio.yaml   |  1 +
 arch/openrisc/boot/dts/de0-nano-common.dtsi   | 41 +++++++++
 arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++
 arch/openrisc/boot/dts/de0-nano.dts           | 54 +++++++++++
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 12 +--
 arch/openrisc/configs/de0_nano_defconfig      | 79 ++++++++++++++++
 .../configs/de0_nano_multicore_defconfig      | 92 +++++++++++++++++++
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 arch/openrisc/include/asm/smp.h               |  3 +-
 arch/openrisc/kernel/smp.c                    | 22 ++++-
 drivers/irqchip/irq-ompic.c                   | 15 ++-
 drivers/irqchip/irq-or1k-pic.c                | 27 +++++-
 13 files changed, 384 insertions(+), 14 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi
 create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts
 create mode 100644 arch/openrisc/boot/dts/de0-nano.dts
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (89%)
 create mode 100644 arch/openrisc/configs/de0_nano_defconfig
 create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-14 18:02 UTC #1 lore raw

PATCH 1/5 dt-bindings: Add compatible string opencores,gpio to gpio-mmio

In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below.

Example:

        gpio0: gpio@91000000 {
                compatible = "opencores,gpio", "brcm,bcm6345-gpio";
                reg = <0x91000000 0x1>, <0x91000001 0x1>;
                reg-names = "dat", "dirout";
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";
        };

Link https://opencores.org/projects/gpio

Signed-off-by Stafford Horne <[email protected]>

---
 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +1 -0

index b4d55bf6a285..0490580df19e 100644
@@ -23,6 +23,7 @@ properties:
       - ni,169445-nand-gpio
       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
       - intel,ixp4xx-expansion-bus-mmio-gpio
+      - opencores,gpio
 
   big-endian: true

Signature · 1 line

2.51.0

Conor Dooley

2025-12-15 16:57 UTC #2 lore raw

Re: [PATCH 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio

Quoted 8 lines · Stafford Horne

In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below.
Example:
        gpio0: gpio@91000000 {
                compatible = "opencores,gpio", "brcm,bcm6345-gpio";

What you have done below does not permit this, it only permits opencores,gpio in isolation.
pw-bot: changes-requested

Quoted 28 lines

                reg = <0x91000000 0x1>, <0x91000001 0x1>;
                reg-names = "dat", "dirout";
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";
        };

Link https://opencores.org/projects/gpio

Signed-off-by Stafford Horne <[email protected]>

---
 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +1 -0

index b4d55bf6a285..0490580df19e 100644
@@ -23,6 +23,7 @@ properties:
       - ni,169445-nand-gpio
       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
       - intel,ixp4xx-expansion-bus-mmio-gpio
+      - opencores,gpio
 
   big-endian: true

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-15 18:40 UTC #3 lore raw

Re: [PATCH 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio

Quoted 5 lines · Conor Dooley

Quoted 4 lines · Stafford Horne
In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below.

Quoted 8 lines

Quoted 4 lines
Example:
        gpio0: gpio@91000000 {
                compatible = "opencores,gpio", "brcm,bcm6345-gpio";
What you have done below does not permit this, it only permits opencores,gpio in isolation.
pw-bot: changes-requested

Understood, I was not familar with the new schema. I was trying to follow what was seen in some other patches, now I see where I went wrong. I will fix this and use the schema validation tools to verify.

Thanks for pointing it out.

Quoted 28 lines

                reg = <0x91000000 0x1>, <0x91000001 0x1>;
                reg-names = "dat", "dirout";
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";
        };

Link https://opencores.org/projects/gpio

Signed-off-by Stafford Horne <[email protected]>

---
 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +1 -0

index b4d55bf6a285..0490580df19e 100644
@@ -23,6 +23,7 @@ properties:
       - ni,169445-nand-gpio
       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
       - intel,ixp4xx-expansion-bus-mmio-gpio
+      - opencores,gpio
 
   big-endian: true

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-15 19:34 UTC #4 lore raw

Re: [PATCH 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio

Quoted 15 lines · Stafford Horne

Quoted 5 lines · Conor Dooley
Quoted 4 lines · Stafford Horne
In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below.
Quoted 8 lines
Quoted 4 lines
Example:
        gpio0: gpio@91000000 {
                compatible = "opencores,gpio", "brcm,bcm6345-gpio";
What you have done below does not permit this, it only permits opencores,gpio in isolation.
pw-bot: changes-requested

Quoted 5 lines

Understood, I was not familar with the new schema. I was trying to follow what was seen in some other patches, now I see where I went wrong. I will fix this and use the schema validation tools to verify.
Thanks for pointing it out.

I think the below is correct. But, would this be ok to put in one patch?

I do:
- Convert compatible from simple enum to oneOf.
- Add items: for the openrisc,gpio compatiblity string.

properties:
compatible:
- enum:

-      - brcm,bcm6345-gpio
-      - ni,169445-nand-gpio
-      - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
-      - intel,ixp4xx-expansion-bus-mmio-gpio
+    oneOf:
+      - const: brcm,bcm6345-gpio
+      - const: ni,169445-nand-gpio
+      - const: wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
+      - const: intel,ixp4xx-expansion-bus-mmio-gpio
+      - items:

+ - enum:
+ - opencores,gpio
+ - const: brcm,bcm6345-gpio

Thanks,

-Stafford

Quoted 30 lines

Quoted 28 lines

                reg = <0x91000000 0x1>, <0x91000001 0x1>;
                reg-names = "dat", "dirout";
                gpio-controller;
                #gpio-cells = <2>;
                status = "okay";
        };

Link https://opencores.org/projects/gpio

Signed-off-by Stafford Horne <[email protected]>

---
 Documentation/devicetree/bindings/gpio/gpio-mmio.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +1 -0

index b4d55bf6a285..0490580df19e 100644
@@ -23,6 +23,7 @@ properties:
       - ni,169445-nand-gpio
       - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
       - intel,ixp4xx-expansion-bus-mmio-gpio
+      - opencores,gpio
 
   big-endian: true

Signature · 1 line

2.51.0

Conor Dooley

2025-12-16 00:05 UTC #5 lore raw

Re: [PATCH 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio

Quoted 31 lines · Stafford Horne

Quoted 15 lines · Stafford Horne
Quoted 5 lines · Conor Dooley
Quoted 4 lines · Stafford Horne
In FPGA Development boards with GPIOs we use the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow as below.
Quoted 8 lines
Quoted 4 lines
Example:
        gpio0: gpio@91000000 {
                compatible = "opencores,gpio", "brcm,bcm6345-gpio";
What you have done below does not permit this, it only permits opencores,gpio in isolation.
pw-bot: changes-requested
Quoted 5 lines
Understood, I was not familar with the new schema. I was trying to follow what was seen in some other patches, now I see where I went wrong. I will fix this and use the schema validation tools to verify.
Thanks for pointing it out.
I think the below is correct. But, would this be ok to put in one patch?
I do:
- Convert compatible from simple enum to oneOf.
- Add items: for the openrisc,gpio compatiblity string.
properties:
compatible:
(quoted diff) +0 -1
-    enum:

Review

Quoted 10 lines

(quoted diff) +5 -4

-      - brcm,bcm6345-gpio
-      - ni,169445-nand-gpio
-      - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
-      - intel,ixp4xx-expansion-bus-mmio-gpio
+    oneOf:
 
+      - const: brcm,bcm6345-gpio
+      - const: ni,169445-nand-gpio
+      - const: wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
+      - const: intel,ixp4xx-expansion-bus-mmio-gpio

This is fine, but keep the enum instead of making these into a bunch of const entries. IOW, just put a - in front of the existing enum: and reindent it to be correct under the oneOf.

Quoted 4 lines

(quoted diff) +4 -0

+      - items:
+          - enum:
+              - opencores,gpio
+          - const: brcm,bcm6345-gpio

Stafford Horne

author maintainer

2025-12-14 18:02 UTC #6 lore raw

PATCH 2/5 openrisc: dts: Add de0 nano config and devicetree

In reply to Stafford Horne

The de0 nano from Terasic is an FPGA board that we use in the OpenRISC community to test OpenRISC configurations. Add a base configuration for the board that runs an OpenRISC CPU at 50Mhz with 32MB ram, UART for console and some GPIOs for LEDs and switches.

There is an older version of this floating around that defines all of the hardware on the board including SPI's, flash devices, sram, ADCs etc. Eventually it would be good to get the full version upstream but for now I think a minimal board is good to start with.

Link https://openrisc.io/tutorials/de0_nano/

Link https://github.com/olofk/de0_nano

Signed-off-by Stafford Horne <[email protected]>

---
 arch/openrisc/boot/dts/de0-nano-common.dtsi | 41 +++++++++++
 arch/openrisc/boot/dts/de0-nano.dts         | 54 ++++++++++++++
 arch/openrisc/configs/de0_nano_defconfig    | 79 +++++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi
 create mode 100644 arch/openrisc/boot/dts/de0-nano.dts
 create mode 100644 arch/openrisc/configs/de0_nano_defconfig

arch/openrisc/boot/dts/de0-nano-common.dtsi new file +41 -0

new file mode 100644
index 000000000000..421c366d120e
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x02000000>;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		status = "okay";
+		led-heartbeat {
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_HEARTBEAT;
+			linux,default-trigger = "heartbeat";
+			label = "heartbeat";
+		};
+	};
+
+	gpio0: gpio@91000000 {
+		compatible = "opencores,gpio", "brcm,bcm6345-gpio";
+		reg = <0x91000000 0x1>, <0x91000001 0x1>;
+		reg-names = "dat", "dirout";
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "okay";
+	};
+
+	gpio1: gpio@92000000 {
+		compatible = "opencores,gpio", "brcm,bcm6345-gpio";
+		reg = <0x92000000 0x1>, <0x92000001 0x1>;
+		reg-names = "dat", "dirout";
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+};

arch/openrisc/boot/dts/de0-nano.dts new file +54 -0

54 lines not on this page · raw message

arch/openrisc/configs/de0_nano_defconfig new file +79 -0

79 lines not on this page · raw message

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-14 18:02 UTC #7 lore raw

PATCH 3/5 openrisc: Fix IPIs on simple multicore systems

In reply to Stafford Horne

Commit c05671846451 ("openrisc: sleep instead of spin on secondary wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never achieved on FPGA development boards. This is because the above patch has a step to unmask IPIs on non-boot cpu's but on hardware without power management, IPIs remain masked.

This meant that IPI's were never actually working on the simple SMP systems we run on development boards. The systems booted but stability was very suspect.

Add the ability to unmask IPI's on the non-boot cores. This is done by making the OMPIC IRQs proper percpu IRQs. We can then use the enabled_percpu_irq() to unmask IRQ on the non-boot cpus.

Update the or1k PIC driver to use a flow handler that can switch between percpu and the configured level or edge flow handlers at runtime. This mechanism is inspired by that done in the J-Core AIC driver.

Signed-off-by Stafford Horne <[email protected]>

---
 arch/openrisc/include/asm/smp.h |  3 ++-
 arch/openrisc/kernel/smp.c      | 22 +++++++++++++++++++++-
 drivers/irqchip/irq-ompic.c     | 15 +++++++++++----
 drivers/irqchip/irq-or1k-pic.c  | 27 ++++++++++++++++++++++++++-
 4 files changed, 60 insertions(+), 7 deletions(-)

arch/openrisc/include/asm/smp.h +2 -1

index e21d2f12b5b6..007296f160ef 100644
@@ -20,7 +20,8 @@ extern void smp_init_cpus(void);
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
-extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
+extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int),
+			       unsigned int irq);
 extern void handle_IPI(unsigned int ipi_msg);
 
 #endif /* __ASM_OPENRISC_SMP_H */

arch/openrisc/kernel/smp.c +21 -1

index 86da4bc5ee0b..040ca201b692 100644
@@ -13,6 +13,7 @@
 
 #include <linux/smp.h>
 #include <linux/cpu.h>
+#include <linux/interrupt.h>
 #include <linux/sched.h>
 #include <linux/sched/mm.h>
 #include <linux/irq.h>

@@ -25,6 +26,7 @@
 
 asmlinkage __init void secondary_start_kernel(void);
 
+static unsigned int ipi_irq __ro_after_init;
 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
 
 unsigned long secondary_release = -1;

@@ -39,6 +41,14 @@ enum ipi_msg_type {
 
 static DEFINE_SPINLOCK(boot_lock);
 
+static void or1k_ipi_enable(void)
+{
+	if (WARN_ON_ONCE(!ipi_irq))
+		return;
+
+	enable_percpu_irq(ipi_irq, 0);
+}
+
 static void boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	/*

@@ -136,6 +146,7 @@ asmlinkage __init void secondary_start_kernel(void)
 	complete(&cpu_running);
 
 	synchronise_count_slave(cpu);
+	or1k_ipi_enable();
 	set_cpu_online(cpu, true);
 
 	local_irq_enable();

@@ -195,9 +206,18 @@ void smp_send_stop(void)
 	smp_call_function(stop_this_cpu, NULL, 0);
 }
 
-void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
+void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int),
+			       unsigned int irq)
 {
+	if (WARN_ON(ipi_irq))
+		return;
+
 	smp_cross_call = fn;
+
+	ipi_irq = irq;
+
+	/* Enabled IPIs for boot CPU immediately */
+	or1k_ipi_enable();
 }
 
 void arch_send_call_function_single_ipi(int cpu)

drivers/irqchip/irq-ompic.c +11 -4

index e66ef4373b1e..f0e0b435bb1d 100644
@@ -84,6 +84,8 @@ DEFINE_PER_CPU(unsigned long, ops);
 
 static void __iomem *ompic_base;
 
+static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev);
+
 static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
 {
 	return ioread32be(base + offset);

@@ -183,12 +185,17 @@ static int __init ompic_of_init(struct device_node *node,
 		goto out_unmap;
 	}
 
-	ret = request_irq(irq, ompic_ipi_handler, IRQF_PERCPU,
-				"ompic_ipi", NULL);
-	if (ret)
+	irq_set_percpu_devid(irq);
+	ret = request_percpu_irq(irq, ompic_ipi_handler, "ompic_ipi",
+				 &ipi_dummy_dev);
+
+	if (ret) {
+		pr_err("ompic: failed to request irq %d, error: %d",
+		       irq, ret);
 		goto out_irq_disp;
+	}
 
-	set_smp_cross_call(ompic_raise_softirq);
+	set_smp_cross_call(ompic_raise_softirq, irq);
 
 	return 0;

drivers/irqchip/irq-or1k-pic.c +26 -1

index 48126067c54b..73dc99c71d40 100644
@@ -118,11 +118,36 @@ static void or1k_pic_handle_irq(struct pt_regs *regs)
 		generic_handle_domain_irq(root_domain, irq);
 }
 
+/*
+ * The OR1K PIC is a cpu-local interrupt controller and does not distinguish or
+ * use distinct irq number ranges for per-cpu event interrupts (IPI). Since
+ * information to determine whether a particular irq number should be treated as
+ * per-cpu is not available at mapping time, we use a wrapper handler function
+ * which chooses the right handler at runtime based on whether IRQF_PERCPU was
+ * used when requesting the irq.  Borrowed from J-Core AIC.
+ */
+static void or1k_irq_flow_handler(struct irq_desc *desc)
+{
+#ifdef CONFIG_SMP
+	struct irq_data *data = irq_desc_get_irq_data(desc);
+	struct or1k_pic_dev *pic = data->domain->host_data;
+
+	if (irqd_is_per_cpu(data))
+		handle_percpu_devid_irq(desc);
+	else
+		pic->handle(desc);
+#endif
+}
+
 static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 {
 	struct or1k_pic_dev *pic = d->host_data;
 
-	irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
+	if (IS_ENABLED(CONFIG_SMP))
+		irq_set_chip_and_handler(irq, &pic->chip, or1k_irq_flow_handler);
+	else
+		irq_set_chip_and_handler(irq, &pic->chip, pic->handle);
+
 	irq_set_status_flags(irq, pic->flags);
 
 	return 0;

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-14 18:02 UTC #8 lore raw

PATCH 4/5 openrisc: dts: Split simple smp dts to dts and dtsi

In reply to Stafford Horne

Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files.

Signed-off-by Stafford Horne <[email protected]>

---
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++++++++++++++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 12 ++++-----
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 3 files changed, 32 insertions(+), 7 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (89%)

arch/openrisc/boot/dts/simple-smp.dts new file +25 -0

new file mode 100644
index 000000000000..174c2613c419
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "simple_smp.dtsi"
+
+/ {
+	model = "Simple SMP Board";
+};
+
+&cpu0 {
+	clock-frequency = <20000000>;
+};
+
+&cpu1 {
+	clock-frequency = <20000000>;
+};
+
+&serial0 {
+	clock-frequency = <20000000>;
+};
+
+&enet0 {
+	status = "okay";
+};

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +6 -6

similarity index 89%
rename from arch/openrisc/boot/dts/simple_smp.dts
rename to arch/openrisc/boot/dts/simple-smp.dtsi
index 71af0e117bfe..92770bb6fcf7 100644
@@ -1,4 +1,3 @@
-/dts-v1/;
 / {
 	compatible = "opencores,or1ksim";
 	#address-cells = <1>;

@@ -22,15 +21,15 @@ memory@0 {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <0>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <1>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
 	};

@@ -57,7 +56,7 @@ serial0: serial@90000000 {
 		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
 		reg = <0x90000000 0x100>;
 		interrupts = <2>;
-		clock-frequency = <20000000>;
+		clock-frequency = <0>;
 	};
 
 	enet0: ethoc@92000000 {

@@ -65,5 +64,6 @@ enet0: ethoc@92000000 {
 		reg = <0x92000000 0x800>;
 		interrupts = <4>;
 		big-endian;
+		status = "disabled";
 	};
 };

arch/openrisc/configs/simple_smp_defconfig +1 -1

index 6008e824d31c..db77c795225e 100644
@@ -20,7 +20,7 @@ CONFIG_SLUB=y
 CONFIG_SLUB_TINY=y
 CONFIG_MODULES=y
 # CONFIG_BLOCK is not set
-CONFIG_BUILTIN_DTB_NAME="simple_smp"
+CONFIG_BUILTIN_DTB_NAME="simple-smp"
 CONFIG_SMP=y
 CONFIG_HZ_100=y
 CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-15 07:30 UTC #9 lore raw

Re: [PATCH 4/5] openrisc: dts: Split simple smp dts to dts and dtsi

Quoted 20 lines · Stafford Horne

Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files.
Signed-off-by Stafford Horne <[email protected]>
---
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++++++++++++++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 12 ++++-----
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 3 files changed, 32 insertions(+), 7 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (89%)
arch/openrisc/boot/dts/simple-smp.dts new file +0 -0
new file mode 100644
index 000000000000..174c2613c419

arch/openrisc/boot/dts/simple-smp.dts line 5

Quoted 5 lines

arch/openrisc/boot/dts/simple-smp.dts new file +5 -0
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "simple_smp.dtsi"

This should be simple-smp.dtsi.

Quoted 84 lines

arch/openrisc/boot/dts/simple-smp.dts new file +20 -0

+
+/ {
+	model = "Simple SMP Board";
+};
+
+&cpu0 {
+	clock-frequency = <20000000>;
+};
+
+&cpu1 {
+	clock-frequency = <20000000>;
+};
+
+&serial0 {
+	clock-frequency = <20000000>;
+};
+
+&enet0 {
+	status = "okay";
+};

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +6 -6

similarity index 89%
rename from arch/openrisc/boot/dts/simple_smp.dts
rename to arch/openrisc/boot/dts/simple-smp.dtsi
index 71af0e117bfe..92770bb6fcf7 100644
@@ -1,4 +1,3 @@
-/dts-v1/;
 / {
 	compatible = "opencores,or1ksim";
 	#address-cells = <1>;

@@ -22,15 +21,15 @@ memory@0 {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <0>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <1>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
 	};

@@ -57,7 +56,7 @@ serial0: serial@90000000 {
 		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
 		reg = <0x90000000 0x100>;
 		interrupts = <2>;
-		clock-frequency = <20000000>;
+		clock-frequency = <0>;
 	};
 
 	enet0: ethoc@92000000 {

@@ -65,5 +64,6 @@ enet0: ethoc@92000000 {
 		reg = <0x92000000 0x800>;
 		interrupts = <4>;
 		big-endian;
+		status = "disabled";
 	};
 };

arch/openrisc/configs/simple_smp_defconfig +1 -1

index 6008e824d31c..db77c795225e 100644
@@ -20,7 +20,7 @@ CONFIG_SLUB=y
 CONFIG_SLUB_TINY=y
 CONFIG_MODULES=y
 # CONFIG_BLOCK is not set
-CONFIG_BUILTIN_DTB_NAME="simple_smp"
+CONFIG_BUILTIN_DTB_NAME="simple-smp"
 CONFIG_SMP=y
 CONFIG_HZ_100=y
 CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y

Signature · 1 line

2.51.0

Conor Dooley

2025-12-15 16:58 UTC #10 lore raw

Re: [PATCH 4/5] openrisc: dts: Split simple smp dts to dts and dtsi

In reply to Stafford Horne

Quoted 58 lines · Stafford Horne

Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files.
Signed-off-by Stafford Horne <[email protected]>
---
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++++++++++++++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 12 ++++-----
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 3 files changed, 32 insertions(+), 7 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (89%)
arch/openrisc/boot/dts/simple-smp.dts new file +25 -0
new file mode 100644
index 000000000000..174c2613c419
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "simple_smp.dtsi"
+
+/ {
+	model = "Simple SMP Board";
+};
+
+&cpu0 {
+	clock-frequency = <20000000>;
+};
+
+&cpu1 {
+	clock-frequency = <20000000>;
+};
+
+&serial0 {
+	clock-frequency = <20000000>;
+};
+
+&enet0 {
+	status = "okay";
+};
arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +0 -1
similarity index 89%
rename from arch/openrisc/boot/dts/simple_smp.dts
rename to arch/openrisc/boot/dts/simple-smp.dtsi
index 71af0e117bfe..92770bb6fcf7 100644
@@ -1,4 +1,3 @@
-/dts-v1/;
 / {
 	compatible = "opencores,or1ksim";
 	#address-cells = <1>;

arch/openrisc/boot/dts/simple-smp.dtsi memory@0 { · line 27

Quoted 9 lines

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +2 -2

@@ -22,15 +21,15 @@ memory@0 {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <0>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;

Delete these lines, don't set them to zero please.

Quoted 42 lines

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +4 -3

 		};
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <1>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
 	};

@@ -57,7 +56,7 @@ serial0: serial@90000000 {
 		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
 		reg = <0x90000000 0x100>;
 		interrupts = <2>;
-		clock-frequency = <20000000>;
+		clock-frequency = <0>;
 	};
 
 	enet0: ethoc@92000000 {

@@ -65,5 +64,6 @@ enet0: ethoc@92000000 {
 		reg = <0x92000000 0x800>;
 		interrupts = <4>;
 		big-endian;
+		status = "disabled";
 	};
 };

arch/openrisc/configs/simple_smp_defconfig +1 -1

index 6008e824d31c..db77c795225e 100644
@@ -20,7 +20,7 @@ CONFIG_SLUB=y
 CONFIG_SLUB_TINY=y
 CONFIG_MODULES=y
 # CONFIG_BLOCK is not set
-CONFIG_BUILTIN_DTB_NAME="simple_smp"
+CONFIG_BUILTIN_DTB_NAME="simple-smp"
 CONFIG_SMP=y
 CONFIG_HZ_100=y
 CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-15 18:19 UTC #11 lore raw

Re: [PATCH 4/5] openrisc: dts: Split simple smp dts to dts and dtsi

Quoted 62 lines · Conor Dooley

Quoted 61 lines · Stafford Horne

Signed-off-by Stafford Horne <[email protected]>

---
 arch/openrisc/boot/dts/simple-smp.dts         | 25 +++++++++++++++++++
 .../dts/{simple_smp.dts => simple-smp.dtsi}   | 12 ++++-----
 arch/openrisc/configs/simple_smp_defconfig    |  2 +-
 3 files changed, 32 insertions(+), 7 deletions(-)
 create mode 100644 arch/openrisc/boot/dts/simple-smp.dts
 rename arch/openrisc/boot/dts/{simple_smp.dts => simple-smp.dtsi} (89%)

arch/openrisc/boot/dts/simple-smp.dts new file +25 -0

new file mode 100644
index 000000000000..174c2613c419
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "simple_smp.dtsi"
+
+/ {
+	model = "Simple SMP Board";
+};
+
+&cpu0 {
+	clock-frequency = <20000000>;
+};
+
+&cpu1 {
+	clock-frequency = <20000000>;
+};
+
+&serial0 {
+	clock-frequency = <20000000>;
+};
+
+&enet0 {
+	status = "okay";
+};

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +0 -1

similarity index 89%
rename from arch/openrisc/boot/dts/simple_smp.dts
rename to arch/openrisc/boot/dts/simple-smp.dtsi
index 71af0e117bfe..92770bb6fcf7 100644
@@ -1,4 +1,3 @@
-/dts-v1/;
 / {
 	compatible = "opencores,or1ksim";
 	#address-cells = <1>;

@@ -22,15 +21,15 @@ memory@0 {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

Quoted 8 lines

arch/openrisc/boot/dts/simple-smp.dtsi memory@0 { · line 27
Quoted 6 lines
arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +2 -2
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <0>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
Delete these lines, don't set them to zero please.

OK, I wasn't sure what to put here so put 0, Just removing is much better.

-Stafford

Quoted 42 lines

arch/openrisc/boot/dts/simple-smp.dtsi renamed from arch/openrisc/boot/dts/simple_smp.dts +4 -3

 		};
-		cpu@1 {
+		cpu1: cpu@1 {
 			compatible = "opencores,or1200-rtlsvn481";
 			reg = <1>;
-			clock-frequency = <20000000>;
+			clock-frequency = <0>;
 		};
 	};

@@ -57,7 +56,7 @@ serial0: serial@90000000 {
 		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
 		reg = <0x90000000 0x100>;
 		interrupts = <2>;
-		clock-frequency = <20000000>;
+		clock-frequency = <0>;
 	};
 
 	enet0: ethoc@92000000 {

@@ -65,5 +64,6 @@ enet0: ethoc@92000000 {
 		reg = <0x92000000 0x800>;
 		interrupts = <4>;
 		big-endian;
+		status = "disabled";
 	};
 };

arch/openrisc/configs/simple_smp_defconfig +1 -1

index 6008e824d31c..db77c795225e 100644
@@ -20,7 +20,7 @@ CONFIG_SLUB=y
 CONFIG_SLUB_TINY=y
 CONFIG_MODULES=y
 # CONFIG_BLOCK is not set
-CONFIG_BUILTIN_DTB_NAME="simple_smp"
+CONFIG_BUILTIN_DTB_NAME="simple-smp"
 CONFIG_SMP=y
 CONFIG_HZ_100=y
 CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y

Signature · 1 line

2.51.0

Stafford Horne

author maintainer

2025-12-14 18:02 UTC #12 lore raw

PATCH 5/5 openrisc: dts: Add de0 nano multicore config and devicetree

In reply to Stafford Horne

Add a multicore configuration for the Terasic de0 nano FPGA development board. This SoC runs 2 OpenRISC CPUs at 50Mhz with 32MB ram, UART for console and GPIOs for LEDs.

This FPGA SoC is based on the simple-smp reference board and brings in devices from the de0 nano common DTSI file.

A default config is added that brings together the device tree and driver setup.

Link https://github.com/stffrdhrn/de0_nano-multicore

Signed-off-by Stafford Horne <[email protected]>

---
 arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++
 .../configs/de0_nano_multicore_defconfig      | 92 +++++++++++++++++++
 2 files changed, 117 insertions(+)
 create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts
 create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig

arch/openrisc/boot/dts/de0-nano-multicore.dts new file +25 -0

new file mode 100644
index 000000000000..b6cf286afaa4
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/dts-v1/;
+
+#include "simple-smp.dtsi"
+#include "de0-nano-common.dtsi"
+
+/ {
+	model = "Terasic DE0 Nano - Multicore";
+};
+
+&cpu0 {
+	clock-frequency = <50000000>;
+};
+
+&cpu1 {
+	clock-frequency = <50000000>;
+};
+
+&serial0 {
+	clock-frequency = <50000000>;
+};

arch/openrisc/configs/de0_nano_multicore_defconfig new file +92 -0

92 lines not on this page · raw message

Signature · 1 line

2.51.0