Add support for Cix Sky1 resets
Gary Yang
maintainerv8 cover Add support for Cix Sky1 resets
Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets
v8 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- remove "simple-mfd" strings
v7 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix build warning
v6 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style
v5 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-controller.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style
v4 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- add syscon
- refine reset driver
- fix dt-bindings style
v3 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- remove syscon
v2 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix dt-bindings style
- refine reset driver
Gary Yang (3):
dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
reset: add Sky1 soc reset support
arm64: dts: cix: add support for cix sky1 resets
.../soc/cix/cix,sky1-system-control.yaml | 42 ++ arch/arm64/boot/dts/cix/sky1.dtsi | 12 + drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 374 ++++++++++++++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cix/Kconfig | 11 + drivers/soc/cix/Makefile | 1 + drivers/soc/cix/sky1-system-control.c | 47 +++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 ++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++ 12 files changed, 703 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 drivers/reset/reset-sky1.c create mode 100644 drivers/soc/cix/Kconfig create mode 100644 drivers/soc/cix/Makefile create mode 100644 drivers/soc/cix/sky1-system-control.c create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
Signature · 1 line
2.49.0
Gary Yang
maintainerPATCH v8 1/3 dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller child is described as usb typeC uses it by phandle.
--- .../soc/cix/cix,sky1-system-control.yaml | 42 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +42 -0
@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system control register region + +maintainers: + - Gary Yang <[email protected]> + +description: + An wide assortment of registers of the system controller on Sky1 SoC, + including resets, usb, wakeup sources and so on. + +properties: + compatible: + items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + };
include/dt-bindings/reset/cix,sky1-rst-fch.h new file +42 -0
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include/dt-bindings/reset/cix,sky1-rst.h new file +164 -0
164 lines not on this page · raw message
Signature · 1 line
2.49.0
Philipp Zabel
maintainerRe: [PATCH v8 1/3] dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
Quoted 3 lines · Gary Yang
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. The system control contains resets, usb typeC and more.
What is "and more"? Does none of the remaining functionality besides resets require any bindings?
Quoted 2 lines
At this point, only the reset controller child
is described as usb typeC uses it by phandle.
What do you mean by "child"? There is no child node for the reset controller (which is correct).
Quoted 20 lines
Signed-off-by Gary Yang <[email protected]>--- .../soc/cix/cix,sky1-system-control.yaml | 42 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.hDocumentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +4
-0@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml#
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml line 14
Quoted 10 lines
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +10
-0+$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system control register region + +maintainers: + - Gary Yang <[email protected]> + +description: + An wide assortment of registers of the system controller on Sky1 SoC, + including resets, usb, wakeup sources and so on.
Will any of this (usb, wakeup, "so on") require further additions to the binding documentation?
regards
Philipp
Re: [PATCH v8 1/3] dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
In reply to Gary YangQuoted 6 lines · Gary Yang
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller child is described as usb typeC uses it by phandle.
Signed-off-by Gary Yang <[email protected]>
Subject is not correct now. There is no simple-mfd. There should not be even syscon, because it is Linux term. Just use the name of this device.
include/dt-bindings/reset/cix,sky1-rst-fch.h
Quoted 58 lines
--- .../soc/cix/cix,sky1-system-control.yaml | 42 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164 ++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.hDocumentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +42
-0@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system control register region + +maintainers: + - Gary Yang <[email protected]> + +description: + An wide assortment of registers of the system controller on Sky1 SoC, + including resets, usb, wakeup sources and so on. + +properties: + compatible: + items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + };include/dt-bindings/reset/cix,sky1-rst-fch.h +0
-0
Filename must match compatible.
I am pretty sure I gave such feedback to Cix before....
Best regards,
Krzysztof
Gary Yang
maintainer回复: [PATCH v8 1/3] dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
Hi Krzysztof:
Thanks for your comments
Quoted 8 lines
EXTERNAL EMAIL
Quoted 5 lines · Gary Yang
There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller child is described as usb typeC uses it by phandle.
Quoted 5 lines
Quoted 1 line
Signed-off-by Gary Yang <[email protected]>Subject is not correct now. There is no simple-mfd. There should not be even syscon, because it is Linux term. Just use the name of this device.
Yes, I agree. We will fix it next version.
Quoted 70 lines
Quoted 4 lines
--- .../soc/cix/cix,sky1-system-control.yaml | 42 +++++ include/dt-bindings/reset/cix,sky1-rst-fch.h | 42 +++++ include/dt-bindings/reset/cix,sky1-rst.h | 164++++++++++++++++++
include/dt-bindings/reset/cix,sky1-rst-fch.h
Quoted 62 lines
3 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h create mode 100644 include/dt-bindings/reset/cix,sky1-rst.hdiff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.ya ml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.ya ml
new file mode 100644
index 000000000000..5507deb54ebdDocumentation/devicetree/bindings/soc/cix/cix,sky1-system-contro new file +44
-0+++ l.yaml@@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 +--- +$id: +http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 SoC system control register region + +maintainers: + - Gary Yang <[email protected]> + +description: + An wide assortment of registers of the system controller on Sky1 +SoC, + including resets, usb, wakeup sources and so on. + +properties: + compatible: + items: + - enum: + - cix,sky1-system-control + - cix,sky1-s5-system-control + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + };include/dt-bindings/reset/cix,sky1-rst-fch.h +0
-0Filename must match compatible.
Quoted 2 lines
I am pretty sure I gave such feedback to Cix before....
Yes, You're right. I remember it. But please allow us to explain it.
This header file contains many macros for reset signals. We intend to use syscon as a common module. So it is not only reset controller, it can also be used by other modules in futher. If the file named by syscon, Maybe make confuse. All right?
If miss any information, please let us know. Thanks
Best Regards
Gary
Quoted 2 lines
Best regards,
Krzysztof
Re: 回复: [PATCH v8 1/3] dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
Quoted 12 lines · Gary Yang
Quoted 12 lines
include/dt-bindings/reset/cix,sky1-rst-fch.h
Quoted 9 lines
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +7
-0+examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + };include/dt-bindings/reset/cix,sky1-rst-fch.h +0
-0Filename must match compatible.
Quoted 7 lines
Quoted 2 lines
I am pretty sure I gave such feedback to Cix before....
Yes, You're right. I remember it. But please allow us to explain it.
This header file contains many macros for reset signals. We intend to use syscon as a common module. So it is not only reset controller, it can also be used by other modules in futher. If the file named by syscon, Maybe make confuse. All right?
Really? How?
Not able to find the header because it is randomly named would confuse more. You don't get exceptions from the rules. Multiple people before also asked for some special naming for whatever reasons. It's the last time I am asking you of it. Read the docs and follow it and we really do not care what internally you want, because you are contributing to GENERIC kernel so you must follow common and generic rules.
Best regards,
Krzysztof
Gary Yang
maintainer回复: 回复: [PATCH v8 1/3] dt-bindings: soc: cix: document the simple-mfd syscon on Sky1 SoC
Hi Krzysztof:
Thanks for your comments
Quoted 25 lines
EXTERNAL EMAIL
Quoted 12 lines · Gary Yang
Quoted 12 lines
include/dt-bindings/reset/cix,sky1-rst-fch.h
Quoted 9 lines
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +7
-0+examples: + - | + syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x16000000 0x1000>; + #reset-cells = <1>; + };include/dt-bindings/reset/cix,sky1-rst-fch.h +0
-0Filename must match compatible.
Quoted 5 lines
Quoted 2 lines
I am pretty sure I gave such feedback to Cix before....
Yes, You're right. I remember it. But please allow us to explain it. This header file contains many macros for reset signals. We intend to use
syscon as a common module.
Quoted 2 lines
So it is not only reset controller, it can also be used by other modules in futher. If the file named by syscon, Maybe make confuse. All
right?
Quoted 9 lines
Really? How?
Not able to find the header because it is randomly named would confuse more. You don't get exceptions from the rules. Multiple people before also asked for some special naming for whatever reasons. It's the last time I am asking you of it. Read the docs and follow it and we really do not care what internally you want, because you are contributing to GENERIC kernel so you must follow common and generic rules.
Sorry, we don't challenge this rule. We study arch/riscv/boot/dts/spacemit/k1.dtsi. In this file, syscon is used as clock controller and reset controller. The reset ID is defined in file named include/dt-bindings/clock/spacemit,k1-syscon.h. I see what you said. We will rename this file to cix,sky1-system-control.h. All right?
Best Regards
Gary
Quoted 3 lines
Best regards,
Krzysztof
Gary Yang
maintainerPATCH v8 2/3 reset: add Sky1 soc reset support
In reply to Gary YangAdd support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain.
--- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 374 ++++++++++++++++++++++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cix/Kconfig | 11 + drivers/soc/cix/Makefile | 1 + drivers/soc/cix/sky1-system-control.c | 47 ++++ 8 files changed, 443 insertions(+) create mode 100644 drivers/reset/reset-sky1.c create mode 100644 drivers/soc/cix/Kconfig create mode 100644 drivers/soc/cix/Makefile create mode 100644 drivers/soc/cix/sky1-system-control.c
drivers/reset/Kconfig +7 -0
@@ -291,6 +291,13 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs +config RESET_SKY1 + bool "Cix Sky1 reset controller" + depends on HAS_IOMEM + depends on ARCH_CIX || COMPILE_TEST + help + This enables the reset controller for Cix Sky1. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) default ARM && ARCH_INTEL_SOCFPGA
drivers/reset/Makefile +1 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o +obj-$(CONFIG_RESET_SKY1) += reset-sky1.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
drivers/reset/reset-sky1.c new file +374 -0
374 lines not on this page · raw message
drivers/soc/Kconfig +1 -0
@@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" source "drivers/soc/cirrus/Kconfig" +source "drivers/soc/cix/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/hisilicon/Kconfig"
drivers/soc/Makefile +1 -0
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ obj-$(CONFIG_ARCH_CANAAN) += canaan/ obj-$(CONFIG_EP93XX_SOC) += cirrus/ +obj-$(CONFIG_ARCH_CIX) += cix/ obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/
drivers/soc/cix/Kconfig new file +11 -0
@@ -0,0 +1,11 @@ +config CIX_SOC_SYSCONS + bool "Cix SoC syscon drivers" + default y + depends on ARCH_CIX + select MFD_CORE + help + The drivers add support for the syscons on Cix SoC. Without + the drivers core parts of the kernel such as resets will not + function correctly. + + If unsure, and on a Cix SoC, say y.
drivers/soc/cix/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_CIX_SOC_SYSCONS) += sky1-system-control.o
drivers/soc/cix/sky1-system-control.c new file +47 -0
47 lines not on this page · raw message
Signature · 1 line
2.49.0
Philipp Zabel
maintainerRe: [PATCH v8 2/3] reset: add Sky1 soc reset support
Quoted 10 lines · Gary Yang
Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain.Signed-off-by Gary Yang <[email protected]>--- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 374 ++++++++++++++++++++++++++
Quoted 5 lines
drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cix/Kconfig | 11 + drivers/soc/cix/Makefile | 1 + drivers/soc/cix/sky1-system-control.c | 47 ++++
soc: changes must be split from the reset: changes.
I'm not sure if soc is the right place for an MFD platform driver. Why is this an MFD driver with only a single function?
Quoted 11 lines
8 files changed, 443 insertions(+) create mode 100644 drivers/reset/reset-sky1.c create mode 100644 drivers/soc/cix/Kconfig create mode 100644 drivers/soc/cix/Makefile create mode 100644 drivers/soc/cix/sky1-system-control.cdrivers/reset/Kconfig +0
-0
drivers/reset/Kconfig config RESET_SIMPLE · line 296
Quoted 6 lines
drivers/reset/Kconfig +3
-0@@ -291,6 +291,13 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs +config RESET_SKY1 + bool "Cix Sky1 reset controller" + depends on HAS_IOMEM
Why the HAS_IOMEM dependency? This driver uses regmap.
Quoted 353 lines
drivers/reset/Kconfig +4
-0+ depends on ARCH_CIX || COMPILE_TEST + help + This enables the reset controller for Cix Sky1. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) default ARM && ARCH_INTEL_SOCFPGAdrivers/reset/Makefile +1
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o +obj-$(CONFIG_RESET_SKY1) += reset-sky1.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.odrivers/reset/reset-sky1.c new file +328
-0@@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* +* CIX System Reset Controller (SRC) driver +* +* Author: Jerry Zhu <[email protected]> +*/ + +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/reset/cix,sky1-rst.h> +#include <dt-bindings/reset/cix,sky1-rst-fch.h> + +#define SKY1_RESET_SLEEP_MIN_US 50 +#define SKY1_RESET_SLEEP_MAX_US 100 + +struct sky1_src_signal { +unsigned int offset; +unsigned int bit; +}; + +struct sky1_src_variant { +const struct sky1_src_signal *signals; +unsigned int signals_num; +}; + +struct sky1_src { +struct reset_controller_dev rcdev; +const struct sky1_src_signal *signals; +struct regmap *regmap; +}; + +enum { +CSU_PM_RESET =0x304 , +SENSORFUSION_RESET =0x308 , +SENSORFUSION_NOC_RESET =0x30c , +RESET_GROUP0_S0_DOMAIN_0 =0x400 , +RESET_GROUP0_S0_DOMAIN_1 =0x404 , +RESET_GROUP1_USB_PHYS =0x408 , +RESET_GROUP1_USB_CONTROLLERS =0x40c , +RESET_GROUP0_RCSU =0x800 , +RESET_GROUP1_RCSU =0x804 , +}; + +static const struct sky1_src_signal sky1_src_signals[] = { +/* reset group1 for s0 domain modules */ + [SKY1_CSU_PM_RESET_N ] = {CSU_PM_RESET ,BIT (0 ) }, + [SKY1_SENSORFUSION_RESET_N ] = {SENSORFUSION_RESET ,BIT (0 ) }, + [SKY1_SENSORFUSION_NOC_RESET_N ] = {SENSORFUSION_NOC_RESET ,BIT (0 ) }, + [SKY1_DDRC_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (0 ) }, + [SKY1_GIC_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (1 ) }, + [SKY1_CI700_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (2 ) }, + [SKY1_SYS_NI700_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (3 ) }, + [SKY1_MM_NI700_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (4 ) }, + [SKY1_PCIE_NI700_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (5 ) }, + [SKY1_GPU_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (6 ) }, + [SKY1_NPUTOP_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (7 ) }, + [SKY1_NPUCORE0_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (8 ) }, + [SKY1_NPUCORE1_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (9 ) }, + [SKY1_NPUCORE2_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (10 ) }, + [SKY1_VPU_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (11 ) }, + [SKY1_ISP_SRESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (12 ) }, + [SKY1_ISP_ARESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (13 ) }, + [SKY1_ISP_HRESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (14 ) }, + [SKY1_ISP_GDCRESET_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (15 ) }, + [SKY1_DPU_RESET0_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (16 ) }, + [SKY1_DPU_RESET1_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (17 ) }, + [SKY1_DPU_RESET2_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (18 ) }, + [SKY1_DPU_RESET3_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (19 ) }, + [SKY1_DPU_RESET4_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (20 ) }, + [SKY1_DP_RESET0_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (21 ) }, + [SKY1_DP_RESET1_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (22 ) }, + [SKY1_DP_RESET2_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (23 ) }, + [SKY1_DP_RESET3_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (24 ) }, + [SKY1_DP_RESET4_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (25 ) }, + [SKY1_DP_PHY_RST_N ] = {RESET_GROUP0_S0_DOMAIN_0 ,BIT (26 ) }, + +/* reset group1 for s0 domain modules */ + [SKY1_AUDIO_HIFI5_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (0 ) }, + [SKY1_AUDIO_HIFI5_NOC_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (1 ) }, + [SKY1_CSIDPHY_PRST0_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (2 ) }, + [SKY1_CSIDPHY_CMNRST0_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (3 ) }, + [SKY1_CSI0_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (4 ) }, + [SKY1_CSIDPHY_PRST1_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (5 ) }, + [SKY1_CSIDPHY_CMNRST1_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (6 ) }, + [SKY1_CSI1_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (7 ) }, + [SKY1_CSI2_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (8 ) }, + [SKY1_CSI3_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (9 ) }, + [SKY1_CSIBRDGE0_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (10 ) }, + [SKY1_CSIBRDGE1_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (11 ) }, + [SKY1_CSIBRDGE2_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (12 ) }, + [SKY1_CSIBRDGE3_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (13 ) }, + [SKY1_GMAC0_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (14 ) }, + [SKY1_GMAC1_RST_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (15 ) }, + [SKY1_PCIE0_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (16 ) }, + [SKY1_PCIE1_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (17 ) }, + [SKY1_PCIE2_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (18 ) }, + [SKY1_PCIE3_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (19 ) }, + [SKY1_PCIE4_RESET_N ] = {RESET_GROUP0_S0_DOMAIN_1 ,BIT (20 ) }, + +/* reset group1 for usb phys */ + [SKY1_USB_DP_PHY0_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (0 ) }, + [SKY1_USB_DP_PHY1_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (1 ) }, + [SKY1_USB_DP_PHY2_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (2 ) }, + [SKY1_USB_DP_PHY3_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (3 ) }, + [SKY1_USB_DP_PHY0_RST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (4 ) }, + [SKY1_USB_DP_PHY1_RST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (5 ) }, + [SKY1_USB_DP_PHY2_RST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (6 ) }, + [SKY1_USB_DP_PHY3_RST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (7 ) }, + [SKY1_USBPHY_SS_PST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (8 ) }, + [SKY1_USBPHY_SS_RST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (9 ) }, + [SKY1_USBPHY_HS0_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (10 ) }, + [SKY1_USBPHY_HS1_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (11 ) }, + [SKY1_USBPHY_HS2_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (12 ) }, + [SKY1_USBPHY_HS3_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (13 ) }, + [SKY1_USBPHY_HS4_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (14 ) }, + [SKY1_USBPHY_HS5_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (15 ) }, + [SKY1_USBPHY_HS6_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (16 ) }, + [SKY1_USBPHY_HS7_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (17 ) }, + [SKY1_USBPHY_HS8_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (18 ) }, + [SKY1_USBPHY_HS9_PRST_N ] = {RESET_GROUP1_USB_PHYS ,BIT (19 ) }, + +/* reset group1 for usb controllers */ + [SKY1_USBC_SS0_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (0 ) }, + [SKY1_USBC_SS1_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (1 ) }, + [SKY1_USBC_SS2_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (2 ) }, + [SKY1_USBC_SS3_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (3 ) }, + [SKY1_USBC_SS4_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (4 ) }, + [SKY1_USBC_SS5_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (5 ) }, + [SKY1_USBC_SS0_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (6 ) }, + [SKY1_USBC_SS1_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (7 ) }, + [SKY1_USBC_SS2_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (8 ) }, + [SKY1_USBC_SS3_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (9 ) }, + [SKY1_USBC_SS4_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (10 ) }, + [SKY1_USBC_SS5_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (11 ) }, + [SKY1_USBC_HS0_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (12 ) }, + [SKY1_USBC_HS1_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (13 ) }, + [SKY1_USBC_HS2_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (14 ) }, + [SKY1_USBC_HS3_PRST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (15 ) }, + [SKY1_USBC_HS0_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (16 ) }, + [SKY1_USBC_HS1_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (17 ) }, + [SKY1_USBC_HS2_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (18 ) }, + [SKY1_USBC_HS3_RST_N ] = {RESET_GROUP1_USB_CONTROLLERS ,BIT (19 ) }, + +/* reset group0 for rcsu */ + [SKY1_AUDIO_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (0 ) }, + [SKY1_CI700_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (1 ) }, + [SKY1_CSI_RCSU0_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (2 ) }, + [SKY1_CSI_RCSU1_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (3 ) }, + [SKY1_CSU_PM_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (4 ) }, + [SKY1_DDR_BROADCAST_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (5 ) }, + [SKY1_DDR_CTRL_RCSU_0_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (6 ) }, + [SKY1_DDR_CTRL_RCSU_1_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (7 ) }, + [SKY1_DDR_CTRL_RCSU_2_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (8 ) }, + [SKY1_DDR_CTRL_RCSU_3_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (9 ) }, + [SKY1_DDR_TZC400_RCSU_0_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (10 ) }, + [SKY1_DDR_TZC400_RCSU_1_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (11 ) }, + [SKY1_DDR_TZC400_RCSU_2_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (12 ) }, + [SKY1_DDR_TZC400_RCSU_3_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (13 ) }, + [SKY1_DP0_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (14 ) }, + [SKY1_DP1_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (15 ) }, + [SKY1_DP2_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (16 ) }, + [SKY1_DP3_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (17 ) }, + [SKY1_DP4_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (18 ) }, + [SKY1_DPU0_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (19 ) }, + [SKY1_DPU1_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (20 ) }, + [SKY1_DPU2_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (21 ) }, + [SKY1_DPU3_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (22 ) }, + [SKY1_DPU4_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (23 ) }, + [SKY1_DSU_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (24 ) }, + [SKY1_FCH_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (25 ) }, + [SKY1_GICD_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (26 ) }, + [SKY1_GMAC_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (27 ) }, + [SKY1_GPU_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (28 ) }, + [SKY1_ISP_RCSU0_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (29 ) }, + [SKY1_ISP_RCSU1_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (30 ) }, + [SKY1_NI700_MMHUB_RCSU_RESET_N ] = {RESET_GROUP0_RCSU ,BIT (31 ) }, + +/* reset group1 for rcsu */ + [SKY1_NPU_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (0 ) }, + [SKY1_NI700_PCIE_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (1 ) }, + [SKY1_PCIE_X421_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (2 ) }, + [SKY1_PCIE_X8_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (3 ) }, + [SKY1_SF_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (4 ) }, + [SKY1_RCSU_SMMU_MMHUB_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (5 ) }, + [SKY1_RCSU_SMMU_PCIEHUB_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (6 ) }, + [SKY1_RCSU_SYSHUB_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (7 ) }, + [SKY1_NI700_SMN_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (8 ) }, + [SKY1_NI700_SYSHUB_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (9 ) }, + [SKY1_RCSU_USB2_HOST0_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (10 ) }, + [SKY1_RCSU_USB2_HOST1_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (11 ) }, + [SKY1_RCSU_USB2_HOST2_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (12 ) }, + [SKY1_RCSU_USB2_HOST3_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (13 ) }, + [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (14 ) }, + [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (15 ) }, + [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (16 ) }, + [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (17 ) }, + [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (18 ) }, + [SKY1_VPU_RCSU_RESET_N ] = {RESET_GROUP1_RCSU ,BIT (19 ) }, +}; + +static const struct sky1_src_variant variant_sky1 = { + .signals = sky1_src_signals, + .signals_num =ARRAY_SIZE (sky1_src_signals), +}; + +enum { +FCH_SW_RST_FUNC =0x8 , +FCH_SW_RST_BUS =0xc , +FCH_SW_XSPI =0x10 , +}; + +static const struct sky1_src_signal sky1_src_fch_signals[] = { +/* resets for fch_sw_rst_func */ + [SW_I3C0_RST_FUNC_G_N ] = {FCH_SW_RST_FUNC ,BIT (0 ) }, + [SW_I3C0_RST_FUNC_I_N ] = {FCH_SW_RST_FUNC ,BIT (1 ) }, + [SW_I3C1_RST_FUNC_G_N ] = {FCH_SW_RST_FUNC ,BIT (2 ) }, + [SW_I3C1_RST_FUNC_I_N ] = {FCH_SW_RST_FUNC ,BIT (3 ) }, + [SW_UART0_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (4 ) }, + [SW_UART1_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (5 ) }, + [SW_UART2_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (6 ) }, + [SW_UART3_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (7 ) }, + [SW_TIMER_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (20 ) }, + +/* resets for fch_sw_rst_bus */ + [SW_I3C0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (0 ) }, + [SW_I3C1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (1 ) }, + [SW_DMA_RST_AXI_N ] = {FCH_SW_RST_BUS ,BIT (2 ) }, + [SW_UART0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (4 ) }, + [SW_UART1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (5 ) }, + [SW_UART2_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (6 ) }, + [SW_UART3_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (7 ) }, + [SW_SPI0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (8 ) }, + [SW_SPI1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (9 ) }, + [SW_I2C0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (12 ) }, + [SW_I2C1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (13 ) }, + [SW_I2C2_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (14 ) }, + [SW_I2C3_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (15 ) }, + [SW_I2C4_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (16 ) }, + [SW_I2C5_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (17 ) }, + [SW_I2C6_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (18 ) }, + [SW_I2C7_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (19 ) }, + [SW_GPIO_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (21 ) }, + +/* resets for fch_sw_xspi */ + [SW_XSPI_REG_RST_N ] = {FCH_SW_XSPI ,BIT (0 ) }, + [SW_XSPI_SYS_RST_N ] = {FCH_SW_XSPI ,BIT (1 ) }, +}; + +static const struct sky1_src_variant variant_sky1_fch = { + .signals = sky1_src_fch_signals, + .signals_num =ARRAY_SIZE (sky1_src_fch_signals), +}; + +static struct sky1_src *to_sky1_src (struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sky1_src, rcdev); +} + +static int sky1_reset_set (struct reset_controller_dev *rcdev, +unsigned long id,bool assert) +{ +struct sky1_src *sky1src =to_sky1_src (rcdev); +const struct sky1_src_signal *signal = &sky1src->signals[id]; +unsigned int value = assert ?0 : sky1src->signals[id].bit; + +return regmap_update_bits (sky1src->regmap, + signal->offset, signal->bit, value); +} + +static int sky1_reset_assert (struct reset_controller_dev *rcdev, +unsigned long id) +{ +sky1_reset_set (rcdev, id, true); +usleep_range (SKY1_RESET_SLEEP_MIN_US , +SKY1_RESET_SLEEP_MAX_US ); +return 0 ; +} + +static int sky1_reset_deassert (struct reset_controller_dev *rcdev, +unsigned long id) +{ +sky1_reset_set (rcdev, id, false); +usleep_range (SKY1_RESET_SLEEP_MIN_US , +SKY1_RESET_SLEEP_MAX_US ); +return 0 ; +} + +static int sky1_reset (struct reset_controller_dev *rcdev, +unsigned long id) +{ +sky1_reset_assert (rcdev, id); +sky1_reset_deassert (rcdev, id); +return 0 ; +} + +static int sky1_reset_status (struct reset_controller_dev *rcdev, +unsigned long id) +{ +unsigned int value =0 ; +struct sky1_src *sky1src =to_sky1_src (rcdev); +const struct sky1_src_signal *signal = &sky1src->signals[id]; + +regmap_read (sky1src->regmap, signal->offset, &value); +return !(value & signal->bit); +} + +static const struct reset_control_ops sky1_src_ops = { + .reset = sky1_reset, + .assert = sky1_reset_assert, + .deassert = sky1_reset_deassert, + .status = sky1_reset_status +}; + +static int sky1_reset_probe (struct platform_device *pdev) +{ +struct sky1_src *sky1src; +struct device *dev = &pdev->dev; +const struct platform_device_id *id; +const struct sky1_src_variant *variant; +
drivers/reset/reset-sky1.c line 338
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+ sky1src =devm_kzalloc (dev,sizeof (*sky1src),GFP_KERNEL ); +if (!sky1src) +return -ENOMEM ; + + id =platform_get_device_id (pdev); +if (!id) +return -ENODEV ; + variant = (struct sky1_src_variant *)id->driver_data; + + sky1src->regmap =device_node_to_regmap (dev->parent->of_node);
Can you use dev_get_regmap() here?
Quoted 13 lines
drivers/reset/reset-sky1.c new file +13
-0+if (IS_ERR (sky1src->regmap)) { +dev_err (dev,"Unable to get sky1-src regmap" ); +return PTR_ERR (sky1src->regmap); + } + + sky1src->signals = variant->signals; + sky1src->rcdev.owner =THIS_MODULE ; + sky1src->rcdev.nr_resets = variant->signals_num; + sky1src->rcdev.ops = &sky1_src_ops; + sky1src->rcdev.of_node = dev->parent->of_node; + sky1src->rcdev.dev = dev; + +return devm_reset_controller_register (dev, &sky1src->rcdev);
drivers/reset/reset-sky1.c line 361
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+} + +static struct platform_device_id reset_id_table[] = { + { .name ="cix,sky1-rst" , + .driver_data = (kernel_ulong_t)&variant_sky1 }, + { .name ="cix,sky1-rst-fch" , + .driver_data = (kernel_ulong_t)&variant_sky1_fch }, + {/* sentinel */ }, +}; +MODULE_DEVICE_TABLE (platform, reset_id_table);
I think the reset driver should be put on the auxiliary bus instead.
drivers/soc/Kconfig
Quoted 17 lines
drivers/reset/reset-sky1.c new file +13
-0+ +static struct platform_driver sky1_reset_driver = { + .probe = sky1_reset_probe, + .driver = { + .name ="cix,sky1-rst" , + }, + .id_table = reset_id_table, +}; +module_platform_driver(sky1_reset_driver) + +MODULE_AUTHOR("Jerry Zhu <[email protected]>"); +MODULE_DESCRIPTION ("Cix Sky1 reset driver" ); +MODULE_LICENSE ("GPL" );drivers/soc/Kconfig +0
-0
Everything that follows doesn't belong in reset:
Quoted 87 lines
drivers/soc/Kconfig +1
-0@@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" source "drivers/soc/cirrus/Kconfig" +source "drivers/soc/cix/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/hisilicon/Kconfig"drivers/soc/Makefile +1
-0@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ obj-$(CONFIG_ARCH_CANAAN) += canaan/ obj-$(CONFIG_EP93XX_SOC) += cirrus/ +obj-$(CONFIG_ARCH_CIX) += cix/ obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/drivers/soc/cix/Kconfig new file +11
-0@@ -0,0 +1,11 @@ +config CIX_SOC_SYSCONS + bool "Cix SoC syscon drivers" + default y + depends on ARCH_CIX + select MFD_CORE + help + The drivers add support for the syscons on Cix SoC. Without + the drivers core parts of the kernel such as resets will not + function correctly. + + If unsure, and on a Cix SoC, say y.drivers/soc/cix/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-$(CONFIG_CIX_SOC_SYSCONS) += sky1-system-control.odrivers/soc/cix/sky1-system-control.c new file +37
-0@@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/array_size.h> +#include <linux/of.h> +#include <linux/mfd/core.h> +#include <linux/mfd/syscon.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> + +static const struct mfd_cell sky1_system_control_devs[] = { +MFD_CELL_NAME ("cix,sky1-rst-fch" ), +}; + +static const struct mfd_cell sky1_s5_system_control_devs[] = { +MFD_CELL_NAME ("cix,sky1-rst" ), +}; + +static int sky1_system_control_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +const struct mfd_cell *cell = + (struct mfd_cell *)of_device_get_match_data (dev); + +return mfd_add_devices (dev,PLATFORM_DEVID_NONE , cell,1 ,NULL ,0 ,NULL ); +} + +static const struct of_device_id sky1_system_control_of_match[] = { + { .compatible ="cix,sky1-system-control" , + .data = sky1_system_control_devs}, + { .compatible ="cix,sky1-s5-system-control" , + .data = sky1_s5_system_control_devs}, + {}, +}; +MODULE_DEVICE_TABLE (of, sky1_system_control_of_match); + +static struct platform_driver sky1_system_control_driver = { + .driver = {
drivers/soc/cix/sky1-system-control.c line 47
Quoted 10 lines
drivers/soc/cix/sky1-system-control.c new file +10
-0+ .name = "sky1-system-control", + .of_match_table = sky1_system_control_of_match, + }, + .probe = sky1_system_control_probe, +}; +module_platform_driver (sky1_system_control_driver); + +MODULE_LICENSE ("GPL" ); +MODULE_AUTHOR ("Gary Yang <[email protected]>" ); +MODULE_DESCRIPTION ("Cix SoC system control driver" );
This driver doesn't really do much right now. Do you expect there will be more functionality added to it in the future?
regards
Philipp
Gary Yang
maintainer回复: [PATCH v8 2/3] reset: add Sky1 soc reset support
Hi Philipp:
Thanks for your comments
Quoted 22 lines
EXTERNAL EMAIL
CAUTION: Suspicious Email from unusual domain.
Quoted 9 lines · Gary Yang
Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain.Signed-off-by Gary Yang <[email protected]>--- drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-sky1.c | 374++++++++++++++++++++++++++
Quoted 5 lines
drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/cix/Kconfig | 11 + drivers/soc/cix/Makefile | 1 + drivers/soc/cix/sky1-system-control.c | 47 ++++
Quoted 5 lines
soc: changes must be split from the reset: changes.
I'm not sure if soc is the right place for an MFD platform driver. Why is this an MFD driver with only a single function?
As Krzysztof's advices, we will remove the file named sky1-system-control.c Make the syscon node directly bind to reset driver. Are you agree?
Quoted 13 lines
Quoted 13 lines
8 files changed, 443 insertions(+) create mode 100644 drivers/reset/reset-sky1.c create mode 100644
drivers/soc/cix/Kconfigcreate mode 100644drivers/soc/cix/Makefilecreate mode 100644drivers/soc/cix/sky1-system-control.cdrivers/reset/Kconfig index renamed from drivers/reset/Kconfig +0
-0
6e5d6deffa7d..24bf60c4e640100644drivers/reset/Kconfig +0
-0@@ -291,6 +291,13 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs
Quoted 6 lines
drivers/reset/Kconfig config RESET_SIMPLE · line 296
Quoted 3 lines
drivers/reset/Kconfig +3
-0+config RESET_SKY1 + bool "Cix Sky1 reset controller" + depends on HAS_IOMEMWhy the
HAS_IOMEMdependency? This driver uses regmap.
OK, we will delete HAS IOMEM option
Quoted 534 lines
drivers/reset/Kconfig config RESET_SIMPLE
Quoted 6 lines
drivers/reset/Kconfig +4
-0+ depends on ARCH_CIX || COMPILE_TEST + help + This enables the reset controller for Cix Sky1. + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM|| !ARCH_INTEL_SOCFPGA) > default ARM && ARCH_INTEL_SOCFPGA diff --gitQuoted 62 lines
a/drivers/reset/Makefile b/drivers/reset/Makefile index
9c3e484dfd81..0d2e1329561d100644drivers/reset/Makefile +0
-0@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o diff --gita/drivers/reset/reset-sky1.cb/drivers/reset/reset-sky1.cnew file mode 100644 index 000000000000..dcdc10013550drivers/reset/reset-sky1.c new file +44
-0@@ -0,0 +1,374 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* +* CIX System Reset Controller (SRC) driver +* +* Author: Jerry Zhu <[email protected]> */ + +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/reset/cix,sky1-rst.h> +#include <dt-bindings/reset/cix,sky1-rst-fch.h> + +#define SKY1_RESET_SLEEP_MIN_US 50 +#define SKY1_RESET_SLEEP_MAX_US 100 + +struct sky1_src_signal { +unsigned int offset; +unsigned int bit; +}; + +struct sky1_src_variant { +const struct sky1_src_signal *signals; +unsigned int signals_num; +}; + +struct sky1_src { +struct reset_controller_dev rcdev; +const struct sky1_src_signal *signals; +struct regmap *regmap; +}; + +enum { +CSU_PM_RESET =0x304 , +SENSORFUSION_RESET =0x308 , +SENSORFUSION_NOC_RESET =0x30c , +RESET_GROUP0_S0_DOMAIN_0 =0x400 , +RESET_GROUP0_S0_DOMAIN_1 =0x404 ,drivers/reset/reset-sky1.c line 54
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+RESET_GROUP1_USB_PHYS =0x408 , +RESET_GROUP1_USB_CONTROLLERS =0x40c , +RESET_GROUP0_RCSU =0x800 , + RESET_GROUP1_RCSU = 0x804, +}; + +static const struct sky1_src_signal sky1_src_signals[] = { +/* reset group1 for s0 domain modules */ + [SKY1_CSU_PM_RESET_N ] = {CSU_PM_RESET ,BIT (0 ) }, + [SKY1_SENSORFUSION_RESET_N ] = {SENSORFUSION_RESET ,BIT(0) },
drivers/reset/reset-sky1.c line 55
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_SENSORFUSION_NOC_RESET_N] ={
SENSORFUSION_NOC_RESET, BIT(0) },drivers/reset/reset-sky1.c line 56
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDRC_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(0) },drivers/reset/reset-sky1.c line 57
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GIC_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(1) },drivers/reset/reset-sky1.c line 58
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CI700_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(2) },drivers/reset/reset-sky1.c line 59
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_SYS_NI700_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(3) },drivers/reset/reset-sky1.c line 60
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_MM_NI700_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(4) },drivers/reset/reset-sky1.c line 61
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE_NI700_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(5) },drivers/reset/reset-sky1.c line 62
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GPU_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(6) },drivers/reset/reset-sky1.c line 63
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NPUTOP_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(7) },drivers/reset/reset-sky1.c line 64
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NPUCORE0_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(8) },drivers/reset/reset-sky1.c line 65
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NPUCORE1_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(9) },drivers/reset/reset-sky1.c line 66
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NPUCORE2_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(10) },drivers/reset/reset-sky1.c line 67
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_VPU_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(11) },drivers/reset/reset-sky1.c line 68
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_SRESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(12) },drivers/reset/reset-sky1.c line 69
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_ARESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(13) },drivers/reset/reset-sky1.c line 70
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_HRESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(14) },drivers/reset/reset-sky1.c line 71
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_GDCRESET_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(15) },drivers/reset/reset-sky1.c line 72
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU_RESET0_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(16) },drivers/reset/reset-sky1.c line 73
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU_RESET1_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(17) },drivers/reset/reset-sky1.c line 74
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU_RESET2_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(18) },drivers/reset/reset-sky1.c line 75
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU_RESET3_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(19) },drivers/reset/reset-sky1.c line 76
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU_RESET4_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(20) },drivers/reset/reset-sky1.c line 77
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_RESET0_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(21) },drivers/reset/reset-sky1.c line 78
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_RESET1_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(22) },drivers/reset/reset-sky1.c line 79
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_RESET2_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(23) },drivers/reset/reset-sky1.c line 80
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_RESET3_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(24) },drivers/reset/reset-sky1.c line 81
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_RESET4_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(25) },drivers/reset/reset-sky1.c line 82
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP_PHY_RST_N] ={
RESET_GROUP0_S0_DOMAIN_0, BIT(26) },drivers/reset/reset-sky1.c
Quoted 3 lines
drivers/reset/reset-sky1.c new file +3
-0+ + /* reset group1 for s0 domain modules */ + [SKY1_AUDIO_HIFI5_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(0) },drivers/reset/reset-sky1.c line 86
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_AUDIO_HIFI5_NOC_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(1) },drivers/reset/reset-sky1.c line 87
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIDPHY_PRST0_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(2) },drivers/reset/reset-sky1.c line 88
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIDPHY_CMNRST0_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(3) },drivers/reset/reset-sky1.c line 89
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI0_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(4) },drivers/reset/reset-sky1.c line 90
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIDPHY_PRST1_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(5) },drivers/reset/reset-sky1.c line 91
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIDPHY_CMNRST1_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(6) },drivers/reset/reset-sky1.c line 92
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI1_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(7) },drivers/reset/reset-sky1.c line 93
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI2_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(8) },drivers/reset/reset-sky1.c line 94
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI3_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(9) },drivers/reset/reset-sky1.c line 95
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIBRDGE0_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(10) },drivers/reset/reset-sky1.c line 96
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIBRDGE1_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(11) },drivers/reset/reset-sky1.c line 97
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIBRDGE2_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(12) },drivers/reset/reset-sky1.c line 98
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSIBRDGE3_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(13) },drivers/reset/reset-sky1.c line 99
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GMAC0_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(14) },drivers/reset/reset-sky1.c line 100
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GMAC1_RST_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(15) },drivers/reset/reset-sky1.c line 101
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE0_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(16) },drivers/reset/reset-sky1.c line 102
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE1_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(17) },drivers/reset/reset-sky1.c line 103
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE2_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(18) },drivers/reset/reset-sky1.c line 104
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE3_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(19) },drivers/reset/reset-sky1.c line 105
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE4_RESET_N] ={
RESET_GROUP0_S0_DOMAIN_1, BIT(20) },drivers/reset/reset-sky1.c
Quoted 3 lines
drivers/reset/reset-sky1.c new file +3
-0+ + /* reset group1 for usb phys */ + [SKY1_USB_DP_PHY0_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(0) },drivers/reset/reset-sky1.c line 109
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY1_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(1) },drivers/reset/reset-sky1.c line 110
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY2_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(2) },drivers/reset/reset-sky1.c line 111
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY3_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(3) },drivers/reset/reset-sky1.c line 112
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY0_RST_N] ={
RESET_GROUP1_USB_PHYS, BIT(4) },drivers/reset/reset-sky1.c line 113
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY1_RST_N] ={
RESET_GROUP1_USB_PHYS, BIT(5) },drivers/reset/reset-sky1.c line 114
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY2_RST_N] ={
RESET_GROUP1_USB_PHYS, BIT(6) },drivers/reset/reset-sky1.c line 115
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USB_DP_PHY3_RST_N] ={
RESET_GROUP1_USB_PHYS, BIT(7) },drivers/reset/reset-sky1.c line 116
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_SS_PST_N] ={
RESET_GROUP1_USB_PHYS, BIT(8) },drivers/reset/reset-sky1.c line 117
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_SS_RST_N] ={
RESET_GROUP1_USB_PHYS, BIT(9) },drivers/reset/reset-sky1.c line 118
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS0_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(10) },drivers/reset/reset-sky1.c line 119
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS1_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(11) },drivers/reset/reset-sky1.c line 120
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS2_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(12) },drivers/reset/reset-sky1.c line 121
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS3_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(13) },drivers/reset/reset-sky1.c line 122
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS4_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(14) },drivers/reset/reset-sky1.c line 123
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS5_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(15) },drivers/reset/reset-sky1.c line 124
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS6_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(16) },drivers/reset/reset-sky1.c line 125
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS7_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(17) },drivers/reset/reset-sky1.c line 126
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS8_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(18) },drivers/reset/reset-sky1.c line 127
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBPHY_HS9_PRST_N] ={
RESET_GROUP1_USB_PHYS, BIT(19) },drivers/reset/reset-sky1.c
Quoted 3 lines
drivers/reset/reset-sky1.c new file +3
-0+ + /* reset group1 for usb controllers */ + [SKY1_USBC_SS0_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(0) },drivers/reset/reset-sky1.c line 131
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS1_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(1) },drivers/reset/reset-sky1.c line 132
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS2_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(2) },drivers/reset/reset-sky1.c line 133
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS3_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(3) },drivers/reset/reset-sky1.c line 134
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS4_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(4) },drivers/reset/reset-sky1.c line 135
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS5_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(5) },drivers/reset/reset-sky1.c line 136
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS0_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(6) },drivers/reset/reset-sky1.c line 137
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS1_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(7) },drivers/reset/reset-sky1.c line 138
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS2_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(8) },drivers/reset/reset-sky1.c line 139
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS3_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(9) },drivers/reset/reset-sky1.c line 140
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS4_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(10) },drivers/reset/reset-sky1.c line 141
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_SS5_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(11) },drivers/reset/reset-sky1.c line 142
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS0_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(12) },drivers/reset/reset-sky1.c line 143
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS1_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(13) },drivers/reset/reset-sky1.c line 144
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS2_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(14) },drivers/reset/reset-sky1.c line 145
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS3_PRST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(15) },drivers/reset/reset-sky1.c line 146
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS0_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(16) },drivers/reset/reset-sky1.c line 147
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS1_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(17) },drivers/reset/reset-sky1.c line 148
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS2_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(18) },drivers/reset/reset-sky1.c line 149
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_USBC_HS3_RST_N] ={
RESET_GROUP1_USB_CONTROLLERS, BIT(19) },drivers/reset/reset-sky1.c
Quoted 3 lines
drivers/reset/reset-sky1.c new file +3
-0+ + /* reset group0 for rcsu */ + [SKY1_AUDIO_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(0) },drivers/reset/reset-sky1.c line 153
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CI700_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(1) },drivers/reset/reset-sky1.c line 154
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI_RCSU0_RESET_N] ={
RESET_GROUP0_RCSU, BIT(2) },drivers/reset/reset-sky1.c line 155
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSI_RCSU1_RESET_N] ={
RESET_GROUP0_RCSU, BIT(3) },drivers/reset/reset-sky1.c line 156
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_CSU_PM_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(4) },drivers/reset/reset-sky1.c line 157
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_BROADCAST_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(5) },drivers/reset/reset-sky1.c line 158
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_CTRL_RCSU_0_RESET_N] ={
RESET_GROUP0_RCSU, BIT(6) },drivers/reset/reset-sky1.c line 159
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_CTRL_RCSU_1_RESET_N] ={
RESET_GROUP0_RCSU, BIT(7) },drivers/reset/reset-sky1.c line 160
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_CTRL_RCSU_2_RESET_N] ={
RESET_GROUP0_RCSU, BIT(8) },drivers/reset/reset-sky1.c line 161
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_CTRL_RCSU_3_RESET_N] ={
RESET_GROUP0_RCSU, BIT(9) },drivers/reset/reset-sky1.c line 162
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_TZC400_RCSU_0_RESET_N] ={
RESET_GROUP0_RCSU, BIT(10) },drivers/reset/reset-sky1.c line 163
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_TZC400_RCSU_1_RESET_N] ={
RESET_GROUP0_RCSU, BIT(11) },drivers/reset/reset-sky1.c line 164
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_TZC400_RCSU_2_RESET_N] ={
RESET_GROUP0_RCSU, BIT(12) },drivers/reset/reset-sky1.c line 165
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DDR_TZC400_RCSU_3_RESET_N] ={
RESET_GROUP0_RCSU, BIT(13) },drivers/reset/reset-sky1.c line 166
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP0_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(14) },drivers/reset/reset-sky1.c line 167
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP1_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(15) },drivers/reset/reset-sky1.c line 168
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP2_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(16) },drivers/reset/reset-sky1.c line 169
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP3_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(17) },drivers/reset/reset-sky1.c line 170
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DP4_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(18) },drivers/reset/reset-sky1.c line 171
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU0_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(19) },drivers/reset/reset-sky1.c line 172
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU1_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(20) },drivers/reset/reset-sky1.c line 173
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU2_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(21) },drivers/reset/reset-sky1.c line 174
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU3_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(22) },drivers/reset/reset-sky1.c line 175
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DPU4_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(23) },drivers/reset/reset-sky1.c line 176
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_DSU_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(24) },drivers/reset/reset-sky1.c line 177
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_FCH_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(25) },drivers/reset/reset-sky1.c line 178
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GICD_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(26) },drivers/reset/reset-sky1.c line 179
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GMAC_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(27) },drivers/reset/reset-sky1.c line 180
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_GPU_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(28) },drivers/reset/reset-sky1.c line 181
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_RCSU0_RESET_N] ={
RESET_GROUP0_RCSU, BIT(29) },drivers/reset/reset-sky1.c line 182
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_ISP_RCSU1_RESET_N] ={
RESET_GROUP0_RCSU, BIT(30) },drivers/reset/reset-sky1.c line 183
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NI700_MMHUB_RCSU_RESET_N] ={
RESET_GROUP0_RCSU, BIT(31) },drivers/reset/reset-sky1.c
Quoted 3 lines
drivers/reset/reset-sky1.c new file +3
-0+ + /* reset group1 for rcsu */ + [SKY1_NPU_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(0) },drivers/reset/reset-sky1.c line 187
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NI700_PCIE_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(1) },drivers/reset/reset-sky1.c line 188
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE_X421_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(2) },drivers/reset/reset-sky1.c line 189
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_PCIE_X8_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(3) },drivers/reset/reset-sky1.c line 190
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_SF_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(4) },drivers/reset/reset-sky1.c line 191
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_SMMU_MMHUB_RESET_N] ={
RESET_GROUP1_RCSU, BIT(5) },drivers/reset/reset-sky1.c line 192
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_SMMU_PCIEHUB_RESET_N] ={
RESET_GROUP1_RCSU, BIT(6) },drivers/reset/reset-sky1.c line 193
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_SYSHUB_RESET_N] ={
RESET_GROUP1_RCSU, BIT(7) },drivers/reset/reset-sky1.c line 194
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NI700_SMN_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(8) },drivers/reset/reset-sky1.c line 195
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_NI700_SYSHUB_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(9) },drivers/reset/reset-sky1.c line 196
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB2_HOST0_RESET_N] ={
RESET_GROUP1_RCSU, BIT(10) },drivers/reset/reset-sky1.c line 197
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB2_HOST1_RESET_N] ={
RESET_GROUP1_RCSU, BIT(11) },drivers/reset/reset-sky1.c line 198
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB2_HOST2_RESET_N] ={
RESET_GROUP1_RCSU, BIT(12) },drivers/reset/reset-sky1.c line 199
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB2_HOST3_RESET_N] ={
RESET_GROUP1_RCSU, BIT(13) },drivers/reset/reset-sky1.c line 200
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N] ={
RESET_GROUP1_RCSU, BIT(14) },drivers/reset/reset-sky1.c line 201
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N] ={
RESET_GROUP1_RCSU, BIT(15) },drivers/reset/reset-sky1.c line 202
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N] ={
RESET_GROUP1_RCSU, BIT(16) },drivers/reset/reset-sky1.c line 203
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N] ={
RESET_GROUP1_RCSU, BIT(17) },drivers/reset/reset-sky1.c line 204
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N] ={
RESET_GROUP1_RCSU, BIT(18) },drivers/reset/reset-sky1.c line 205
Quoted 1 line
drivers/reset/reset-sky1.c new file +1
-0+ [SKY1_VPU_RCSU_RESET_N] ={
RESET_GROUP1_RCSU, BIT(19) },Quoted 113 lines
drivers/reset/reset-sky1.c new file +113
-0+}; + +static const struct sky1_src_variant variant_sky1 = { + .signals = sky1_src_signals, + .signals_num =ARRAY_SIZE (sky1_src_signals), }; + +enum { +FCH_SW_RST_FUNC =0x8 , +FCH_SW_RST_BUS =0xc , +FCH_SW_XSPI =0x10 , +}; + +static const struct sky1_src_signal sky1_src_fch_signals[] = { +/* resets for fch_sw_rst_func */ + [SW_I3C0_RST_FUNC_G_N ] = {FCH_SW_RST_FUNC ,BIT (0 ) }, + [SW_I3C0_RST_FUNC_I_N ] = {FCH_SW_RST_FUNC ,BIT (1 ) }, + [SW_I3C1_RST_FUNC_G_N ] = {FCH_SW_RST_FUNC ,BIT (2 ) }, + [SW_I3C1_RST_FUNC_I_N ] = {FCH_SW_RST_FUNC ,BIT (3 ) }, + [SW_UART0_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (4 ) }, + [SW_UART1_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (5 ) }, + [SW_UART2_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (6 ) }, + [SW_UART3_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (7 ) }, + [SW_TIMER_RST_FUNC_N ] = {FCH_SW_RST_FUNC ,BIT (20 ) }, + +/* resets for fch_sw_rst_bus */ + [SW_I3C0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (0 ) }, + [SW_I3C1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (1 ) }, + [SW_DMA_RST_AXI_N ] = {FCH_SW_RST_BUS ,BIT (2 ) }, + [SW_UART0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (4 ) }, + [SW_UART1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (5 ) }, + [SW_UART2_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (6 ) }, + [SW_UART3_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (7 ) }, + [SW_SPI0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (8 ) }, + [SW_SPI1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (9 ) }, + [SW_I2C0_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (12 ) }, + [SW_I2C1_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (13 ) }, + [SW_I2C2_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (14 ) }, + [SW_I2C3_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (15 ) }, + [SW_I2C4_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (16 ) }, + [SW_I2C5_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (17 ) }, + [SW_I2C6_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (18 ) }, + [SW_I2C7_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (19 ) }, + [SW_GPIO_RST_APB_N ] = {FCH_SW_RST_BUS ,BIT (21 ) }, + +/* resets for fch_sw_xspi */ + [SW_XSPI_REG_RST_N ] = {FCH_SW_XSPI ,BIT (0 ) }, + [SW_XSPI_SYS_RST_N ] = {FCH_SW_XSPI ,BIT (1 ) }, +}; + +static const struct sky1_src_variant variant_sky1_fch = { + .signals = sky1_src_fch_signals, + .signals_num =ARRAY_SIZE (sky1_src_fch_signals), }; + +static struct sky1_src *to_sky1_src (struct reset_controller_dev +*rcdev) { + return container_of(rcdev, struct sky1_src, rcdev); } + +static int sky1_reset_set (struct reset_controller_dev *rcdev, +unsigned long id,bool assert) { +struct sky1_src *sky1src =to_sky1_src (rcdev); +const struct sky1_src_signal *signal = &sky1src->signals[id]; +unsigned int value = assert ?0 : sky1src->signals[id].bit; + +return regmap_update_bits (sky1src->regmap, + signal->offset, signal->bit, value); } + +static int sky1_reset_assert (struct reset_controller_dev *rcdev, +unsigned long id) { +sky1_reset_set (rcdev, id, true); +usleep_range (SKY1_RESET_SLEEP_MIN_US , +SKY1_RESET_SLEEP_MAX_US ); +return 0 ; +} + +static int sky1_reset_deassert (struct reset_controller_dev *rcdev, +unsigned long id) { +sky1_reset_set (rcdev, id, false); +usleep_range (SKY1_RESET_SLEEP_MIN_US , +SKY1_RESET_SLEEP_MAX_US ); +return 0 ; +} + +static int sky1_reset (struct reset_controller_dev *rcdev, +unsigned long id) +{ +sky1_reset_assert (rcdev, id); +sky1_reset_deassert (rcdev, id); +return 0 ; +} + +static int sky1_reset_status (struct reset_controller_dev *rcdev, +unsigned long id) { +unsigned int value =0 ; +struct sky1_src *sky1src =to_sky1_src (rcdev); +const struct sky1_src_signal *signal = &sky1src->signals[id]; + +regmap_read (sky1src->regmap, signal->offset, &value); +return !(value & signal->bit); +} + +static const struct reset_control_ops sky1_src_ops = { + .reset = sky1_reset, + .assert = sky1_reset_assert, + .deassert = sky1_reset_deassert, + .status = sky1_reset_status +}; + +static int sky1_reset_probe (struct platform_device *pdev) { +struct sky1_src *sky1src; +struct device *dev = &pdev->dev; +const struct platform_device_id *id; +const struct sky1_src_variant *variant; +drivers/reset/reset-sky1.c line 338
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+ sky1src =devm_kzalloc (dev,sizeof (*sky1src),GFP_KERNEL ); +if (!sky1src) +return -ENOMEM ; + + id =platform_get_device_id (pdev); +if (!id) +return -ENODEV ; + variant = (struct sky1_src_variant *)id->driver_data; + + sky1src->regmap =device_node_to_regmap (dev->parent->of_node);Can you use
dev_get_regmap()here?Quoted 12 lines
drivers/reset/reset-sky1.c new file +12
-0+if (IS_ERR (sky1src->regmap)) { +dev_err (dev,"Unable to get sky1-src regmap" ); +return PTR_ERR (sky1src->regmap); + } + + sky1src->signals = variant->signals; + sky1src->rcdev.owner =THIS_MODULE ; + sky1src->rcdev.nr_resets = variant->signals_num; + sky1src->rcdev.ops = &sky1_src_ops; + sky1src->rcdev.of_node = dev->parent->of_node; + sky1src->rcdev.dev = dev; +drivers/reset/reset-sky1.c line 361
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+return devm_reset_controller_register (dev, &sky1src->rcdev); } + +static struct platform_device_id reset_id_table[] = { + { .name ="cix,sky1-rst" , + .driver_data = (kernel_ulong_t)&variant_sky1 }, + { .name ="cix,sky1-rst-fch" , + .driver_data = (kernel_ulong_t)&variant_sky1_fch }, + {/* sentinel */ }, +}; +MODULE_DEVICE_TABLE (platform, reset_id_table);I think the reset driver should be put on the auxiliary bus instead.
Quoted 10 lines
drivers/reset/reset-sky1.c new file +10
-0+ +static struct platform_driver sky1_reset_driver = { + .probe = sky1_reset_probe, + .driver = { + .name ="cix,sky1-rst" , + }, + .id_table = reset_id_table, +}; +module_platform_driver (sky1_reset_driver) +
Quoted 8 lines
drivers/soc/Kconfig
Quoted 6 lines
drivers/reset/reset-sky1.c new file +2
-0+MODULE_AUTHOR ("Jerry Zhu <[email protected]>" ); +MODULE_DESCRIPTION ("Cix Sky1 reset driver" );MODULE_LICENSE ("GPL" );drivers/soc/Kconfig index renamed from drivers/soc/Kconfig +0
-0
a2d65adffb80..150352c50be9100644drivers/soc/Kconfig +0
-0Everything that follows doesn't belong in reset:
We will delete sky1-system-control.c as Krzysztof's advices. Are you Agree?
Quoted 91 lines
Quoted 91 lines
drivers/soc/Kconfig +1
-0@@ -8,6 +8,7 @@ source "drivers/soc/atmel/Kconfig" source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" source "drivers/soc/cirrus/Kconfig" +source "drivers/soc/cix/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" source "drivers/soc/hisilicon/Kconfig"drivers/soc/Makefile index renamed from drivers/soc/Makefile +0
-0
c9e689080ceb..e36645abf20a100644drivers/soc/Makefile +1
-0@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ obj-$(CONFIG_ARCH_CANAAN) += canaan/ obj-$(CONFIG_EP93XX_SOC) += cirrus/ +obj-$(CONFIG_ARCH_CIX) += cix/ obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/drivers/soc/cix/Kconfig new renamed from drivers/soc/cix/Kconfig +0
-0file mode 100644 index 000000000000..3487499d4b2a
drivers/soc/cix/Kconfig new file +11
-0@@ -0,0 +1,11 @@ +config CIX_SOC_SYSCONS + bool "Cix SoC syscon drivers" + default y + depends on ARCH_CIX + select MFD_CORE + help + The drivers add support for the syscons on Cix SoC. Without + the drivers core parts of the kernel such as resets will not + function correctly. + + If unsure, and on a Cix SoC, say y.drivers/soc/cix/Makefile new renamed from drivers/soc/cix/Makefile +0
-0file mode 100644 index 000000000000..e1252cf836ba
drivers/soc/cix/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-$(CONFIG_CIX_SOC_SYSCONS) += sky1-system-control.odrivers/soc/cix/sky1-system-control.c new file +41
-0@@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/array_size.h> +#include <linux/of.h> +#include <linux/mfd/core.h> +#include <linux/mfd/syscon.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> + +static const struct mfd_cell sky1_system_control_devs[] = { +MFD_CELL_NAME ("cix,sky1-rst-fch" ), +}; + +static const struct mfd_cell sky1_s5_system_control_devs[] = { +MFD_CELL_NAME ("cix,sky1-rst" ), +}; + +static int sky1_system_control_probe (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +const struct mfd_cell *cell = + (struct mfd_cell +*)of_device_get_match_data (dev); + +return mfd_add_devices (dev,PLATFORM_DEVID_NONE , cell,1 ,NULL , +0 ,NULL ); } + +static const struct of_device_id sky1_system_control_of_match[] = { + { .compatible ="cix,sky1-system-control" , + .data = sky1_system_control_devs}, + { .compatible ="cix,sky1-s5-system-control" , + .data = sky1_s5_system_control_devs}, + {}, +}; +MODULE_DEVICE_TABLE (of, sky1_system_control_of_match); + +static struct platform_driver sky1_system_control_driver = { + .driver = { + .name ="sky1-system-control" , + .of_match_table = sky1_system_control_of_match, + }, + .probe = sky1_system_control_probe, };
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drivers/soc/cix/sky1-system-control.c line 47
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drivers/soc/cix/sky1-system-control.c new file +5
-0+module_platform_driver (sky1_system_control_driver); + +MODULE_LICENSE ("GPL" ); +MODULE_AUTHOR ("Gary Yang <[email protected]>" ); +MODULE_DESCRIPTION ("Cix SoC system control driver" );This driver doesn't really do much right now. Do you expect there will be more functionality added to it in the future?
Yes, you're right. We intend to adopt the advices from conor. But I saw the new syscon scheme from spacemit,k210-syscon and these comments from Krzysztof. We will delete sky1-system-control.c as Krzysztof's advices. Are you Agree?
Best Regards
Gary
Quoted 2 lines
regards
Philipp
Philipp Zabel
maintainerRe: 回复: [PATCH v8 2/3] reset: add Sky1 soc reset support
On Mi, 2026-02-11 at 01:56 +0000, Gary Yang wrote:
[...]
Quoted 2 lines
As Krzysztof's advices, we will remove the file named
sky1-system-control.cMake the syscon node directly bind to reset driver. Are you agree?
[...]
Quoted 6 lines
Quoted 4 lines
We will delete
sky1-system-control.cas Krzysztof's advices. Are you Agree?
[...]
Quoted 3 lines
Yes, you're right. We intend to adopt the advices from conor. But I saw the new syscon scheme from spacemit,k210-syscon and these comments from Krzysztof. We will delete
sky1-system-control.cas Krzysztof's advices. Are you Agree?
I agree.
regards
Philipp
Gary Yang
maintainer回复: 回复: [PATCH v8 2/3] reset: add Sky1 soc reset support
Hi Philipp:
Sorry for delay reply.
Quoted 15 lines
CAUTION: Suspicious Email from unusual domain.
On Mi, 2026-02-11 at 01:56 +0000, Gary Yang wrote:
[...]Quoted 2 lines
As Krzysztof's advices, we will remove the file named
sky1-system-control.cMake the syscon node directly bind to reset driver. Areyou agree?
[...]Quoted 6 lines
Quoted 4 lines
We will delete
sky1-system-control.cas Krzysztof's advices. Are you Agree?
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[...]
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Yes, you're right. We intend to adopt the advices from conor. But I saw the new syscon scheme from spacemit,k210-syscon and these comments
from Krzysztof. We will delete
sky1-system-control.cas Krzysztof's advices. Are you Agree?I agree.
It's a surprise! I'm glad to see your agreement. We will submit v9 following Krzysztof's advices.
Best Regards
Gary
Quoted 2 lines
regards
Philipp
Re: [PATCH v8 2/3] reset: add Sky1 soc reset support
In reply to Gary YangQuoted 14 lines · Gary Yang
drivers/soc/cix/sky1-system-control.c new file +14
-0+static int sky1_system_control_probe (struct platform_device *pdev) +{ +struct device *dev = &pdev->dev; +const struct mfd_cell *cell = + (struct mfd_cell *)of_device_get_match_data (dev); + +return mfd_add_devices (dev,PLATFORM_DEVID_NONE , cell,1 ,NULL ,0 ,NULL ); +} + +static const struct of_device_id sky1_system_control_of_match[] = { + { .compatible ="cix,sky1-system-control" , + .data = sky1_system_control_devs}, + { .compatible ="cix,sky1-s5-system-control" , + .data = sky1_s5_system_control_devs},
drivers/soc/cix/sky1-system-control.c line 41
Quoted 10 lines
drivers/soc/cix/sky1-system-control.c new file +10
-0+ {}, +}; +MODULE_DEVICE_TABLE (of, sky1_system_control_of_match); + +static struct platform_driver sky1_system_control_driver = { + .driver = { + .name ="sky1-system-control" , + .of_match_table = sky1_system_control_of_match, + }, + .probe = sky1_system_control_probe,
I do not understand why do you need thish driver in the first place. It's completely empty - just spawns reset driver, so you only need a reset driver.
Layers of indirection are never helpful.
Best regards,
Krzysztof
Gary Yang
maintainer回复: [PATCH v8 2/3] reset: add Sky1 soc reset support
Hi Krzysztof:
Thanks for your comments
Quoted 31 lines
EXTERNAL EMAIL
Quoted 14 lines · Gary Yang
drivers/soc/cix/sky1-system-control.c new file +14
-0+static int sky1_system_control_probe (struct platform_device *pdev) { +struct device *dev = &pdev->dev; +const struct mfd_cell *cell = + (struct mfd_cell +*)of_device_get_match_data (dev); + +return mfd_add_devices (dev,PLATFORM_DEVID_NONE , cell,1 ,NULL , +0 ,NULL ); } + +static const struct of_device_id sky1_system_control_of_match[] = { + { .compatible ="cix,sky1-system-control" , + .data = sky1_system_control_devs}, + { .compatible ="cix,sky1-s5-system-control" , + .data = sky1_s5_system_control_devs},drivers/soc/cix/sky1-system-control.c line 41
Quoted 10 lines
drivers/soc/cix/sky1-system-control.c new file +10
-0+ {}, +}; +MODULE_DEVICE_TABLE (of, sky1_system_control_of_match); + +static struct platform_driver sky1_system_control_driver = { + .driver = { + .name ="sky1-system-control" , + .of_match_table = sky1_system_control_of_match, + }, + .probe = sky1_system_control_probe,I do not understand why do you need thish driver in the first place. It's completely empty - just spawns reset driver, so you only need a reset driver.
Quoted 2 lines
Layers of indirection are never helpful.
OK, we will remove this file next version. Thanks for your advices
Best Regards
Gary
Quoted 2 lines
Best regards,
Krzysztof
Gary Yang
maintainerPATCH v8 3/3 arm64: dts: cix: add support for cix sky1 resets
In reply to Gary YangThere are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S0 and S5 domain.
--- arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/cix/sky1.dtsi +12 -0
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 { status = "disabled"; }; + syscon: syscon@4160000 { + compatible = "cix,sky1-system-control", "syscon"; + reg = <0x0 0x4160000 0x0 0x100>; + #reset-cells = <1>; + }; + iomuxc: pinctrl@4170000 { compatible = "cix,sky1-pinctrl"; reg = <0x0 0x04170000 0x0 0x1000>;
@@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 { }; }; + s5_syscon: syscon@16000000 { + compatible = "cix,sky1-s5-system-control", "syscon"; + reg = <0x0 0x16000000 0x0 0x1000>; + #reset-cells = <1>; + }; + iomuxc_s5: pinctrl@16007000 { compatible = "cix,sky1-pinctrl-s5"; reg = <0x0 0x16007000 0x0 0x1000>;
Signature · 1 line
2.49.0