drivers: clk: meson: Add Amlogic T7 fix pll support
Subsystems (4)
PATCH 1/7 drivers: clk: meson: Add Amlogic T7 fix pll support
Add PLL for the clock controller of the Amlogic T7 SoC family.
--- drivers/clk/meson/t7-pll.c | 257 +++++++++++++++++++++++++++++++++++++ 1 file changed, 257 insertions(+)
drivers/clk/meson/t7-pll.c +257 -0
@@ -71,6 +71,15 @@#define MCLK_PLL_CNTL4 0x10#define MCLK_PLL_STS 0x14 +#define FPLL_CTRL0 0x00 +#define FPLL_CTRL1 0x04 +#define FPLL_CTRL2 0x08 +#define FPLL_CTRL3 0x0c +#define FPLL_CTRL4 0x10 +#define FPLL_CTRL5 0x14 +#define FPLL_CTRL6 0x18 +#define FPLL_STS 0x1c +static const struct pll_mult_range t7_media_pll_mult_range = { .min =125 , .max =250 ,
@@ -1047,6 +1056,253 @@ static const struct meson_clkc_data t7_mclk_data = { }, }; +static struct clk_regmap t7_fpll_dco = { + .data = &(struct meson_clk_pll_data ){ + .en = { + .reg_off =FPLL_CTRL0 , + .shift =28 , + .width =1 , + }, + .m = { + .reg_off =FPLL_CTRL0 , + .shift =0 , + .width =8 , + }, + .n = { + .reg_off =FPLL_CTRL0 , + .shift =10 , + .width =5 , + }, + .frac = { + .reg_off =FPLL_CTRL1 , + .shift =0 , + .width =17 , + }, + .l = { + .reg_off =FPLL_CTRL0 , + .shift =31 , + .width =1 , + }, + .rst = { + .reg_off =FPLL_CTRL0 , + .shift =29 , + .width =1 , + }, + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll_dco" , + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data ) { + .fw_name ="xtal" , + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fpll = { + .data = &(struct clk_regmap_div_data ){ + .offset =FPLL_CTRL0 , + .shift =16 , + .width =2 , + .flags =CLK_DIVIDER_POWER_OF_TWO , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll" , + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll_dco.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div = { + .mult =1 , + .div =2 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =24 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv2p5_div = { + .mult =2 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2p5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =25 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2p5_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv3_div = { + .mult =1 , + .div =3 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv3 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =20 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv3_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv4_div = { + .mult =1 , + .div =4 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv4 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =21 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv4_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv5_div = { + .mult =1 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =22 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv5_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv7_div = { + .mult =1 , + .div =7 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv7 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =23 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv7_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_hw *t7_fpll_hw_clks[] = { + [CLKID_FPLL_DCO ] = &t7_fpll_dco.hw, + [CLKID_FPLL ] = &t7_fpll.hw, + [CLKID_FDIV2_DIV ] = &t7_fdiv2_div.hw, + [CLKID_FDIV2 ] = &t7_fdiv2.hw, + [CLKID_FDIV2P5_DIV ] = &t7_fdiv2p5_div.hw, + [CLKID_FDIV2P5 ] = &t7_fdiv2p5.hw, + [CLKID_FDIV3_DIV ] = &t7_fdiv3_div.hw, + [CLKID_FDIV3 ] = &t7_fdiv3.hw, + [CLKID_FDIV4_DIV ] = &t7_fdiv4_div.hw, + [CLKID_FDIV4 ] = &t7_fdiv4.hw, + [CLKID_FDIV5_DIV ] = &t7_fdiv5_div.hw, + [CLKID_FDIV5 ] = &t7_fdiv5.hw, + [CLKID_FDIV7_DIV ] = &t7_fdiv7_div.hw, + [CLKID_FDIV7 ] = &t7_fdiv7.hw, +}; + +static const struct meson_clkc_data t7_fpll_data = { + .hw_clks = { + .hws = t7_fpll_hw_clks, + .num =ARRAY_SIZE (t7_fpll_hw_clks), + }, +}; +static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible ="amlogic,t7-gp0-pll" , .data = &t7_gp0_data, }, { .compatible ="amlogic,t7-gp1-pll" , .data = &t7_gp1_data, },
@@ -1055,6 +1311,7 @@ static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, }, { .compatible = "amlogic,t7-hdmi-pll", .data = &t7_hdmi_data, }, { .compatible = "amlogic,t7-mclk-pll", .data = &t7_mclk_data, }, + { .compatible = "amlogic,t7-fpll", .data = &t7_fpll_data, }, {} }; MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
Signature · 1 line
2.49.0
PATCH 2/7 dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Add PLL for the clock controller of the Amlogic T7 SoC family.
--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
include/dt-bindings/clock/amlogic,t7-pll-clkc.h +16 -0
@@ -53,4 +53,20 @@#define CLKID_MCLK_1_PRE 9#define CLKID_MCLK_1 10 +/* ANALOG */ +#define CLKID_FPLL_DCO 0 +#define CLKID_FPLL 1 +#define CLKID_FDIV2_DIV 2 +#define CLKID_FDIV2 3 +#define CLKID_FDIV2P5_DIV 4 +#define CLKID_FDIV2P5 5 +#define CLKID_FDIV3_DIV 6 +#define CLKID_FDIV3 7 +#define CLKID_FDIV4_DIV 8 +#define CLKID_FDIV4 9 +#define CLKID_FDIV5_DIV 10 +#define CLKID_FDIV5 11 +#define CLKID_FDIV7_DIV 12 +#define CLKID_FDIV7 13 +#endif /* __T7_PLL_CLKC_H */
Signature · 1 line
2.49.0
Jerome Brunet
maintainerRe: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Quoted 1 line · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Usually bindings changes should comes before the driver changes in a series.
This is especially important here because you are using the IDs in the driver. With order used here, bisect is broken.
Quoted 11 lines
Signed-off-by Ronald Claveau <[email protected]>--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)include/dt-bindings/clock/amlogic,t7-pll-clkc.h +0
-0
include/dt-bindings/clock/amlogic,t7-pll-clkc.h line 56
Quoted 4 lines
include/dt-bindings/clock/amlogic,t7-pll-clkc.h +1
-0@@ -53,4 +53,20 @@#define CLKID_MCLK_1_PRE 9#define CLKID_MCLK_1 10 +/* ANALOG */
No idea what you mean with this ...
Quoted 16 lines
include/dt-bindings/clock/amlogic,t7-pll-clkc.h +15
-0+#define CLKID_FPLL_DCO 0 +#define CLKID_FPLL 1 +#define CLKID_FDIV2_DIV 2 +#define CLKID_FDIV2 3 +#define CLKID_FDIV2P5_DIV 4 +#define CLKID_FDIV2P5 5 +#define CLKID_FDIV3_DIV 6 +#define CLKID_FDIV3 7 +#define CLKID_FDIV4_DIV 8 +#define CLKID_FDIV4 9 +#define CLKID_FDIV5_DIV 10 +#define CLKID_FDIV5 11 +#define CLKID_FDIV7_DIV 12 +#define CLKID_FDIV7 13 +#endif /* __T7_PLL_CLKC_H */
Signature · 1 line
Jerome
Re: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
In reply to Ronald ClaveauQuoted 6 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Signed-off-by Ronald Claveau <[email protected]>--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
So you ignored my comments?
And that's v2, not v1. You sent v1 and GOT the comments.
Best regards,
Krzysztof
Jerome Brunet
maintainerRe: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Quoted 11 lines · Krzysztof Kozlowski
Quoted 6 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Signed-off-by Ronald Claveau <[email protected]>--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)So you ignored my comments?
And that's v2, not v1. You sent v1 and GOT the comments.
I think this was still v1 and if you look at timestamps, Patch 1 was sent before your first reply, then there is lot of time between the different patches - probably done manually ... at patch 6 (the one you've commented fist) was sent twice.
I think there is no malice here, just first time contribution with a few mistakes ;)
Quoted 8 lines
Best regards,
Krzysztof_______________________________________________
linux-amlogic mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-amlogic
Signature · 1 line
Jerome
Re: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Quoted 10 lines · Jerome Brunet
Quoted 8 lines · Krzysztof Kozlowski
Quoted 6 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Signed-off-by Ronald Claveau <[email protected]>--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Quoted 5 lines
Quoted 3 lines
So you ignored my comments?
And that's v2, not v1. You sent v1 and GOT the comments.
I think this was still v1 and if you look at timestamps, Patch 1 was sent
No
Quoted 3 lines
before your first reply, then there is lot of time between the different patches - probably done manually ... at patch 6 (the one you've commented fist) was sent twice.
1. v1:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 11:17:26 +0100
2. My reply 5 minutes later:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 11:21:13 +0100
3. This patch send half an hour later:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 *11:56:09* +0100
after I already provided feedback about wrong threading.
Best regards,
Krzysztof
Re: [PATCH 2/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Quoted 27 lines · Krzysztof Kozlowski
Quoted 10 lines · Jerome Brunet
Quoted 8 lines · Krzysztof Kozlowski
Quoted 6 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Signed-off-by Ronald Claveau <[email protected]>--- include/dt-bindings/clock/amlogic,t7-pll-clkc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)Quoted 5 lines
Quoted 3 lines
So you ignored my comments?
And that's v2, not v1. You sent v1 and GOT the comments.
I think this was still v1 and if you look at timestamps, Patch 1 was sent
No
Quoted 3 lines
before your first reply, then there is lot of time between the different patches - probably done manually ... at patch 6 (the one you've commented fist) was sent twice.
1. v1:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 11:17:26 +0100
Quoted 7 lines
2. My reply 5 minutes later:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 11:21:13 +01003. This patch send half an hour later:
https://lore.kernel.org/all/[email protected]/
Wed, 18 Feb 2026 *11:56:09* +0100
Ah, and I forgot to mention - author replied to me in private at:
Wed, 18 Feb 2026 11:28:23 +0100
So BEFORE this was sent, thus he already received my first reply to v1 and this had to be conscious sending of next version, thus v2.
Quoted 6 lines
after I already provided feedback about wrong threading.
Best regards,
Krzysztof
Best regards,
Krzysztof
PATCH 3/7 dt-bindings: clk: meson: Add Amlogic T7 fix pll support
In reply to Ronald ClaveauAdd PLL for the clock controller of the Amlogic T7 SoC family.
--- .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +4 -1
@@ -23,6 +23,7 @@ properties: - amlogic,t7-mpll - amlogic,t7-hdmi-pll - amlogic,t7-mclk-pll + - amlogic,t7-fpll reg: maxItems: 1
@@ -42,6 +43,7 @@ properties: - const: in0 - const: in1 - const: in2 + - const: xtal minItems: 1 required:
@@ -72,11 +74,12 @@ allOf: contains: enum: - amlogic,t7-gp0-pll - - amlogic,t7-gp1--pll + - amlogic,t7-gp1-pll - amlogic,t7-hifi-pll - amlogic,t7-pcie-pll - amlogic,t7-mpll - amlogic,t7-hdmi-pll + - amlogic,t7-fpll then: properties:
Signature · 1 line
2.49.0
Jerome Brunet
maintainerRe: [PATCH 3/7] dt-bindings: clk: meson: Add Amlogic T7 fix pll support
Quoted 1 line · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
Assuming the 3 first patch are actually needed (I don't think they are) I think patch 2 and 3 should be squashed together
Quoted 19 lines
Signed-off-by Ronald Claveau <[email protected]>--- .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +1
-0@@ -23,6 +23,7 @@ properties: - amlogic,t7-mpll - amlogic,t7-hdmi-pll - amlogic,t7-mclk-pll + - amlogic,t7-fpll reg: maxItems: 1
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml properties: · line 46
Quoted 4 lines
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +1
-0@@ -42,6 +43,7 @@ properties: - const: in0 - const: in1 - const: in2 + - const: xtal
Fishy. Maybe it will get more clear with a more detailed commit description
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml allOf: · line 77
Quoted 9 lines
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +1
-1minItems: 1 required:@@ -72,11 +74,12 @@ allOf: contains: enum: - amlogic,t7-gp0-pll - - amlogic,t7-gp1--pll + - amlogic,t7-gp1-pll
Indeed that's not good ! but you need specific patch for this, and Fixes tag. You can send this separately.
Quoted 8 lines
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +1
-0- amlogic,t7-hifi-pll - amlogic,t7-pcie-pll - amlogic,t7-mpll - amlogic,t7-hdmi-pll + - amlogic,t7-fpll then: properties:
Signature · 1 line
Jerome
PATCH 4/7 drivers: clk: meson: Add Amlogic T7 sys pll support
In reply to Ronald ClaveauAdd SYS PLL for the clock controller of the Amlogic T7 SoC family.
--- drivers/clk/meson/t7-peripherals.c | 134 ++++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 3 deletions(-)
drivers/clk/meson/t7-peripherals.c +131 -3
@@ -176,6 +176,127 @@ static struct clk_regmap t7_rtc = { }, }; +static u32 t7_sys_parents_val_table[] = {0 ,1 ,2 ,3 ,4 ,5 ,7 }; +static const struct clk_parent_data t7_sys_parents[] = { + { .fw_name ="xtal" , }, + { .fw_name ="fdiv2" , }, + { .fw_name ="fdiv3" , }, + { .fw_name ="fdiv4" , }, + { .fw_name ="fdiv5" , }, + { .fw_name ="axi_clk_frcpu" , }, + { .hw = &t7_rtc.hw }, +}; + +static struct clk_regmap t7_sys_a_sel = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x7 , + .shift =10 , + .table = t7_sys_parents_val_table, + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a_sel" , + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sys_parents, + .num_parents =ARRAY_SIZE (t7_sys_parents), + }, +}; + +static struct clk_regmap t7_sys_a_div = { + .data = &(struct clk_regmap_div_data ){ + .offset =SYS_CLK_CTRL0 , + .shift =0 , + .width =10 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a_div" , + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a_sel.hw + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + }, +}; + +static struct clk_regmap t7_sys_a = { + .data = &(struct clk_regmap_gate_data ){ + .offset =SYS_CLK_CTRL0 , + .bit_idx =13 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys_b_sel = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x7 , + .shift =26 , + .table = t7_sys_parents_val_table, + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b_sel" , + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sys_parents, + .num_parents =ARRAY_SIZE (t7_sys_parents), + }, +}; + +static struct clk_regmap t7_sys_b_div = { + .data = &(struct clk_regmap_div_data ){ + .offset =SYS_CLK_CTRL0 , + .shift =16 , + .width =10 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b_div" , + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_b_sel.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys_b = { + .data = &(struct clk_regmap_gate_data ){ + .offset =SYS_CLK_CTRL0 , + .bit_idx =29 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_b_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x1 , + .shift =15 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_clk" , + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a.hw, + &t7_sys_b.hw, + }, + .num_parents =2 , + }, +}; +static struct clk_regmap t7_ceca_dualdiv_in = { .data = &(struct clk_regmap_gate_data ){ .offset =CECA_CTRL0 ,
@@ -824,7 +945,7 @@ static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0);static const struct clk_parent_data t7_spicc_parents[] = { { .fw_name ="xtal" , }, - { .fw_name ="sys" , }, + { .hw = &t7_sys.hw }, { .fw_name ="fdiv4" , }, { .fw_name ="fdiv3" , }, { .fw_name ="fdiv2" , },
@@ -859,7 +980,7 @@ static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0);static const struct clk_parent_data t7_saradc_parents[] = { { .fw_name ="xtal" }, - { .fw_name ="sys" }, + { .hw = &t7_sys.hw }, }; static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents);
@@ -929,7 +1050,7 @@ static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents); static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8); static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0); -static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name ="sys" }; +static const struct clk_parent_data t7_sys_pclk_parents = { .hw = &t7_sys.hw };#define T7_SYS_PCLK (_name, _reg, _bit, _flags) \ MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags)
@@ -1161,6 +1282,13 @@ static struct clk_hw *t7_peripherals_hw_clks[] = { [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw, [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw, [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw, + [CLKID_SYS_A_SEL] = &t7_sys_a_sel.hw, + [CLKID_SYS_A_DIV] = &t7_sys_a_div.hw, + [CLKID_SYS_A] = &t7_sys_a.hw, + [CLKID_SYS_B_SEL] = &t7_sys_b_sel.hw, + [CLKID_SYS_B_DIV] = &t7_sys_b_div.hw, + [CLKID_SYS_B] = &t7_sys_b.hw, + [CLKID_SYS] = &t7_sys.hw, [CLKID_SYS_DDR] = &t7_sys_ddr.hw, [CLKID_SYS_DOS] = &t7_sys_dos.hw, [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw,
Signature · 1 line
2.49.0
Jerome Brunet
maintainerRe: [PATCH 4/7] drivers: clk: meson: Add Amlogic T7 sys pll support
Quoted 1 line · Ronald Claveau
Add SYS PLL for the clock controller of the Amlogic T7 SoC family.
Like the FDIVs, I think this is provided by SCMI.
Check include/dt-bindings/clock/amlogic,t7-scmi.h
Quoted 179 lines
Signed-off-by Ronald Claveau <[email protected]>--- drivers/clk/meson/t7-peripherals.c | 134 ++++++++++++++++++++++++++++- 1 file changed, 131 insertions(+), 3 deletions(-)drivers/clk/meson/t7-peripherals.c +131
-3@@ -176,6 +176,127 @@ static struct clk_regmap t7_rtc = { }, }; +static u32 t7_sys_parents_val_table[] = {0 ,1 ,2 ,3 ,4 ,5 ,7 }; +static const struct clk_parent_data t7_sys_parents[] = { + { .fw_name ="xtal" , }, + { .fw_name ="fdiv2" , }, + { .fw_name ="fdiv3" , }, + { .fw_name ="fdiv4" , }, + { .fw_name ="fdiv5" , }, + { .fw_name ="axi_clk_frcpu" , }, + { .hw = &t7_rtc.hw }, +}; + +static struct clk_regmap t7_sys_a_sel = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x7 , + .shift =10 , + .table = t7_sys_parents_val_table, + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a_sel" , + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sys_parents, + .num_parents =ARRAY_SIZE (t7_sys_parents), + }, +}; + +static struct clk_regmap t7_sys_a_div = { + .data = &(struct clk_regmap_div_data ){ + .offset =SYS_CLK_CTRL0 , + .shift =0 , + .width =10 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a_div" , + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a_sel.hw + }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + }, +}; + +static struct clk_regmap t7_sys_a = { + .data = &(struct clk_regmap_gate_data ){ + .offset =SYS_CLK_CTRL0 , + .bit_idx =13 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_a" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys_b_sel = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x7 , + .shift =26 , + .table = t7_sys_parents_val_table, + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b_sel" , + .ops = &clk_regmap_mux_ops, + .parent_data = t7_sys_parents, + .num_parents =ARRAY_SIZE (t7_sys_parents), + }, +}; + +static struct clk_regmap t7_sys_b_div = { + .data = &(struct clk_regmap_div_data ){ + .offset =SYS_CLK_CTRL0 , + .shift =16 , + .width =10 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b_div" , + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_b_sel.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys_b = { + .data = &(struct clk_regmap_gate_data ){ + .offset =SYS_CLK_CTRL0 , + .bit_idx =29 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_b" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_b_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_sys = { + .data = &(struct clk_regmap_mux_data ){ + .offset =SYS_CLK_CTRL0 , + .mask =0x1 , + .shift =15 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="sys_clk" , + .ops = &clk_regmap_mux_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_sys_a.hw, + &t7_sys_b.hw, + }, + .num_parents =2 , + }, +}; +static struct clk_regmap t7_ceca_dualdiv_in = { .data = &(struct clk_regmap_gate_data ){ .offset =CECA_CTRL0 ,@@ -824,7 +945,7 @@ static T7_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7, 0);static const struct clk_parent_data t7_spicc_parents[] = { { .fw_name ="xtal" , }, - { .fw_name ="sys" , }, + { .hw = &t7_sys.hw }, { .fw_name ="fdiv4" , }, { .fw_name ="fdiv3" , }, { .fw_name ="fdiv2" , },@@ -859,7 +980,7 @@ static T7_COMP_GATE(spicc5, SPICC_CLK_CTRL2, 22, 0);static const struct clk_parent_data t7_saradc_parents[] = { { .fw_name ="xtal" }, - { .fw_name ="sys" }, + { .hw = &t7_sys.hw }, }; static T7_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, t7_saradc_parents);@@ -929,7 +1050,7 @@ static T7_COMP_SEL(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 25, 0x3, t7_pwm_parents); static T7_COMP_DIV(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 16, 8); static T7_COMP_GATE(pwm_ao_h, PWM_CLK_AO_GH_CTRL, 24, 0); -static const struct clk_parent_data t7_sys_pclk_parents = { .fw_name ="sys" }; +static const struct clk_parent_data t7_sys_pclk_parents = { .hw = &t7_sys.hw };#define T7_SYS_PCLK (_name, _reg, _bit, _flags) \ MESON_PCLK(t7_##_name, _reg, _bit, &t7_sys_pclk_parents, _flags)@@ -1161,6 +1282,13 @@ static struct clk_hw *t7_peripherals_hw_clks[] = { [CLKID_PWM_AO_H_SEL] = &t7_pwm_ao_h_sel.hw, [CLKID_PWM_AO_H_DIV] = &t7_pwm_ao_h_div.hw, [CLKID_PWM_AO_H] = &t7_pwm_ao_h.hw, + [CLKID_SYS_A_SEL] = &t7_sys_a_sel.hw, + [CLKID_SYS_A_DIV] = &t7_sys_a_div.hw, + [CLKID_SYS_A] = &t7_sys_a.hw, + [CLKID_SYS_B_SEL] = &t7_sys_b_sel.hw, + [CLKID_SYS_B_DIV] = &t7_sys_b_div.hw, + [CLKID_SYS_B] = &t7_sys_b.hw, + [CLKID_SYS] = &t7_sys.hw, [CLKID_SYS_DDR] = &t7_sys_ddr.hw, [CLKID_SYS_DOS] = &t7_sys_dos.hw, [CLKID_SYS_MIPI_DSI_A] = &t7_sys_mipi_dsi_a.hw,
Signature · 1 line
Jerome
PATCH 5/7 dt-bindings: clk: meson: Add Amlogic T7 sys pll support
In reply to Ronald ClaveauAdd SYS PLL for the clock controller of the Amlogic T7 SoC family.
--- include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h | 7 +++++++ 1 file changed, 7 insertions(+)
include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h +7 -0
@@ -224,5 +224,12 @@#define CLKID_SYS_PWM_AO_CD 215#define CLKID_SYS_PWM_AO_EF 216#define CLKID_SYS_PWM_AO_GH 217 +#define CLKID_SYS_A_SEL 218 +#define CLKID_SYS_A_DIV 219 +#define CLKID_SYS_A 220 +#define CLKID_SYS_B_SEL 221 +#define CLKID_SYS_B_DIV 222 +#define CLKID_SYS_B 223 +#define CLKID_SYS 224#endif /* __T7_PERIPHERALS_CLKC_H */
Signature · 1 line
2.49.0
Re: [PATCH 5/7] dt-bindings: clk: meson: Add Amlogic T7 sys pll support
Hi,
Quoted 1 line · Ronald Claveau
Add SYS PLL for the clock controller of the Amlogic T7 SoC family.
Your commit description is almost the same on every patch in the series. Probably having a more specific description per commit would be much more useful, for reviewers to better understand your commit.
There are documentation pages on how to write informative commit messages at [1] and [2], but in summary, your description should talk about *what* is being done and (provided that makes sense), *why*.
You also have multiple commits with the exact same commit message ("dt-bindings: clk: meson: Add Amlogic T7 sys pll support"), did you mean to squash them all into one? (You can do so with git rebase -i.)
It probably also would make sense to add a cover letter, which would describe overall what you goal is with this patch series, and on a high level (doesn't have to be too detailled, because you'd describe these in more detail in the respective commit messages themselves) what each patch does. This once again helps people reviewing your code to understand what problem you're trying to solve.
[1]: https://docs.kernel.org/process/submitting-patches.html#explanation-body
[2]: https://docs.kernel.org/process/submitting-patches.html#describe-your-changes
Best regards,
Ferass
[PS: sorry if this email was sent twice, my email client did something
strange]
Quoted 31 lines
Signed-off-by Ronald Claveau <[email protected]>---
include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h| 7 +++++++1 file changed, 7 insertions(+)include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h +7
-0@@ -224,5 +224,12 @@#define CLKID_SYS_PWM_AO_CD 215#define CLKID_SYS_PWM_AO_EF 216#define CLKID_SYS_PWM_AO_GH 217 +#define CLKID_SYS_A_SEL 218 +#define CLKID_SYS_A_DIV 219 +#define CLKID_SYS_A 220 +#define CLKID_SYS_B_SEL 221 +#define CLKID_SYS_B_DIV 222 +#define CLKID_SYS_B 223 +#define CLKID_SYS 224#endif /* __T7_PERIPHERALS_CLKC_H */ Signature · 7 lines
2.49.0 _______________________________________________ linux-amlogic mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-amlogic
Re: [PATCH 5/7] dt-bindings: clk: meson: Add Amlogic T7 sys pll support
Quoted 26 lines · Ferass El Hafidi
Hi,
Quoted 1 line · Ronald Claveau
Add SYS PLL for the clock controller of the Amlogic T7 SoC family.
Your commit description is almost the same on every patch in the series. Probably having a more specific description per commit would be much more useful, for reviewers to better understand your commit.
There are documentation pages on how to write informative commit messages at [1] and [2], but in summary, your description should talk about *what* is being done and (provided that makes sense), *why*.
You also have multiple commits with the exact same commit message ("dt-bindings: clk: meson: Add Amlogic T7 sys pll support"), did you mean to squash them all into one? (You can do so with
git rebase -i.)It probably also would make sense to add a cover letter, which would describe
overall what you goal is with this patch series, and on a high level (doesn't have to be too detailled, because you'd describe these in more detail in the respective commit messages themselves) what each patch does. This once again helps people reviewing your code to understand what problem you're trying to solve.
Quoted 5 lines
[1]: https://docs.kernel.org/process/submitting-
patches.html#explanation-body
[2]: https://docs.kernel.org/process/submitting-patches.html#describe-
your-changes
Thanks for your help Ferass, I definitely will.
I think I have misread this part of the doc :
"The Documentation/ and include/dt-bindings/ portion of the patch should be a separate patch."
If I am allowed to combine the header and yaml doc in the same commit, I will do so.
Best regards,
Ronald
Re: [PATCH 5/7] dt-bindings: clk: meson: Add Amlogic T7 sys pll support
In reply to Ronald ClaveauQuoted 1 line · Ronald Claveau
Add SYS PLL for the clock controller of the Amlogic T7 SoC family.
You already sent v1 and received feedback. Implement that one.
Best regards,
Krzysztof
PATCH 6/7 arm64: dts: amlogic: Add clock and EMMC for T7
In reply to Ronald ClaveauAdd fixed clock and EMMC support for Amlogic T7 SoC family dtsi.
--- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 129 ++++++++++++++++++++ 1 file changed, 129 insertions(+)
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +129 -0
@@ -3,6 +3,8 @@ * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/amlogic,t7-pwrc.h> #include "amlogic-t7-reset.h"
@@ -224,6 +226,24 @@ apb4: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc: clock-controller@0 { + compatible = "amlogic,t7-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x49c>; + #clock-cells = <1>; + clocks = <&xtal>, + <&fpll CLKID_FDIV2>, + <&fpll CLKID_FDIV2P5>, + <&fpll CLKID_FDIV3>, + <&fpll CLKID_FDIV4>, + <&fpll CLKID_FDIV5>, + <&hifi_pll CLKID_HIFI_PLL>, + <&mpll CLKID_MPLL2>, + <&mpll CLKID_MPLL3>, + <&gp0_pll CLKID_GP0_PLL>; + clock-names = "xtal", "fdiv2", "fdiv2p5", "fdiv3", "fdiv4", + "fdiv5", "hifi", "mpll2", "mpll3", "gp0"; + }; + reset: reset-controller@2000 { compatible = "amlogic,t7-reset"; reg = <0x0 0x2000 0x0 0x98>;
@@ -250,6 +270,68 @@ gpio: bank@4000 { #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 157>; }; + + emmc_ctrl_pins: emmc-ctrl { + mux-0 { + groups = "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_data_4b_pins: emmc-data-4b { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + emmc_data_8b_pins: emmc-data-8b { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "GPIOB_8"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; }; gpio_intc: interrupt-controller@4080 {
@@ -262,6 +344,38 @@ gpio_intc: interrupt-controller@4080 { <10 11 12 13 14 15 16 17 18 19 20 21>; }; + fpll: clock-controller@8040 { + compatible = "amlogic,t7-fpll"; + reg = <0x0 0x8040 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + gp0_pll: clock-controller@8080 { + compatible = "amlogic,t7-gp0-pll"; + reg = <0x0 0x8080 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "in0"; + }; + + hifi_pll: clock-controller@8100 { + compatible = "amlogic,t7-hifi-pll"; + reg = <0x0 0x8100 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "in0"; + }; + + mpll: clock-controller@8180 { + compatible = "amlogic,t7-mpll"; + reg = <0x0 0x8180 0x0 0x20>; + #clock-cells = <1>; + clocks = <&fpll CLKID_FPLL_DCO>; + clock-names = "in0"; + }; + uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>;
@@ -276,6 +390,21 @@ sec_ao: ao-secure@10220 { reg = <0x0 0x10220 0x0 0x140>; amlogic,has-chip-id; }; + + sd_emmc_c: mmc@8c000{ + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SYS_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C>, + <&gp0_pll CLKID_GP0_PLL>; + clock-names = "core", "clkin0", "clkin1"; + assigned-clocks = <&clkc CLKID_SD_EMMC_C_SEL>; + assigned-clock-parents = <&xtal>; + no-sdio; + no-sd; + }; }; };
Signature · 1 line
2.49.0
Jerome Brunet
maintainerRe: [PATCH 6/7] arm64: dts: amlogic: Add clock and EMMC for T7
Quoted 1 line · Ronald Claveau
Add fixed clock and EMMC support for Amlogic T7 SoC family dtsi.
One topic per patch please
Quoted 174 lines
Signed-off-by Ronald Claveau <[email protected]>--- arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 129 ++++++++++++++++++++ 1 file changed, 129 insertions(+)arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +129
-0@@ -3,6 +3,8 @@ * Copyright (c) 2019 Amlogic, Inc. All rights reserved. */ +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/amlogic,t7-pwrc.h> #include "amlogic-t7-reset.h"@@ -224,6 +226,24 @@ apb4: bus@fe000000 { #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + clkc: clock-controller@0 { + compatible = "amlogic,t7-peripherals-clkc"; + reg = <0x0 0x0 0x0 0x49c>; + #clock-cells = <1>; + clocks = <&xtal>, + <&fpll CLKID_FDIV2>, + <&fpll CLKID_FDIV2P5>, + <&fpll CLKID_FDIV3>, + <&fpll CLKID_FDIV4>, + <&fpll CLKID_FDIV5>, + <&hifi_pll CLKID_HIFI_PLL>, + <&mpll CLKID_MPLL2>, + <&mpll CLKID_MPLL3>, + <&gp0_pll CLKID_GP0_PLL>; + clock-names = "xtal", "fdiv2", "fdiv2p5", "fdiv3", "fdiv4", + "fdiv5", "hifi", "mpll2", "mpll3", "gp0"; + }; + reset: reset-controller@2000 { compatible = "amlogic,t7-reset"; reg = <0x0 0x2000 0x0 0x98>;@@ -250,6 +270,68 @@ gpio: bank@4000 { #gpio-cells = <2>; gpio-ranges = <&periphs_pinctrl 0 0 157>; }; + + emmc_ctrl_pins: emmc-ctrl { + mux-0 { + groups = "emmc_cmd"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + mux-1 { + groups = "emmc_clk"; + function = "emmc"; + bias-disable; + drive-strength-microamp = <4000>; + }; + }; + + emmc_data_4b_pins: emmc-data-4b { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + emmc_data_8b_pins: emmc-data-8b { + mux-0 { + groups = "emmc_nand_d0", + "emmc_nand_d1", + "emmc_nand_d2", + "emmc_nand_d3", + "emmc_nand_d4", + "emmc_nand_d5", + "emmc_nand_d6", + "emmc_nand_d7"; + function = "emmc"; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + emmc_ds_pins: emmc-ds { + mux { + groups = "emmc_nand_ds"; + function = "emmc"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; + + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "GPIOB_8"; + function = "gpio_periphs"; + bias-pull-down; + drive-strength-microamp = <4000>; + }; + }; }; gpio_intc: interrupt-controller@4080 {@@ -262,6 +344,38 @@ gpio_intc: interrupt-controller@4080 { <10 11 12 13 14 15 16 17 18 19 20 21>; }; + fpll: clock-controller@8040 { + compatible = "amlogic,t7-fpll"; + reg = <0x0 0x8040 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "xtal"; + }; + + gp0_pll: clock-controller@8080 { + compatible = "amlogic,t7-gp0-pll"; + reg = <0x0 0x8080 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "in0"; + }; + + hifi_pll: clock-controller@8100 { + compatible = "amlogic,t7-hifi-pll"; + reg = <0x0 0x8100 0x0 0x20>; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "in0"; + }; + + mpll: clock-controller@8180 { + compatible = "amlogic,t7-mpll"; + reg = <0x0 0x8180 0x0 0x20>; + #clock-cells = <1>; + clocks = <&fpll CLKID_FPLL_DCO>; + clock-names = "in0"; + }; + uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>;@@ -276,6 +390,21 @@ sec_ao: ao-secure@10220 { reg = <0x0 0x10220 0x0 0x140>; amlogic,has-chip-id; }; + + sd_emmc_c: mmc@8c000{ + compatible = "amlogic,meson-axg-mmc"; + reg = <0x0 0x8c000 0x0 0x800>; + interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + clocks = <&clkc CLKID_SYS_SD_EMMC_C>, + <&clkc CLKID_SD_EMMC_C>, + <&gp0_pll CLKID_GP0_PLL>; + clock-names = "core", "clkin0", "clkin1"; + assigned-clocks = <&clkc CLKID_SD_EMMC_C_SEL>; + assigned-clock-parents = <&xtal>; + no-sdio; + no-sd; + }; }; };
Signature · 1 line
Jerome
Re: [PATCH 6/7] arm64: dts: amlogic: Add clock and EMMC for T7
In reply to Ronald Claveauarch/arm64/boot/dts/amlogic/amlogic-t7.dtsi sec_ao: ao-secure@10220 { · line 395
Quoted 11 lines · Ronald Claveau
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi +4
-0+ uart_a: serial@78000 { compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; reg = <0x0 0x78000 0x0 0x18>;@@ -276,6 +390,21 @@ sec_ao: ao-secure@10220 { reg = <0x0 0x10220 0x0 0x140>; amlogic,has-chip-id; }; + + sd_emmc_c: mmc@8c000{ + compatible = "amlogic,meson-axg-mmc";
This was already sent and I already commented here.
Best regards,
Krzysztof
PATCH 7/7 arm64: dts: amlogic: Add EMMC for T7 khadas VIM4
In reply to Ronald ClaveauAdd EMMC support for Amlogic T7 Khadas VIM4 device dts.
--- .../amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+)
arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +62 -0
@@ -15,6 +15,10 @@ aliases { serial0 = &uart_a; }; + chosen { + stdout-path = "serial0:921600n8"; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x2 0x0>; /* 8 GB */
@@ -45,6 +49,42 @@ xtal: xtal-clk { #clock-cells = <0>; }; + dc_in: regulator-dc-in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vsys_3v3: regulator-vsys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VSYS_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + regulator-always-on; + /* FIXME: actually controlled by VDDCPU_B_EN */ + }; + + emmc_1v8: regulator-emmc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + regulator-always-on; + }; + }; &uart_a {
@@ -52,3 +92,25 @@ &uart_a { clocks = <&xtal>, <&xtal>, <&xtal>; clock-names = "xtal", "pclk", "baud"; }; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + max-frequency = <200000000>; + disable-wp; + non-removable; + + power-domains = <&pwrc PWRC_T7_EMMC_ID>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_1v8>; +};
Signature · 1 line
2.49.0
Jerome Brunet
maintainerQuoted 2 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
As Krzysztof pointed out, a series like this needs a cover letter to explain what you are trying to acheive overall, and proper threading.
The description above is too vague.
Quoted 11 lines
Signed-off-by Ronald Claveau <[email protected]>--- drivers/clk/meson/t7-pll.c | 257 +++++++++++++++++++++++++++++++++++++ 1 file changed, 257 insertions(+)drivers/clk/meson/t7-pll.c +0
-0@@ -71,6 +71,15 @@#define MCLK_PLL_CNTL4 0x10
drivers/clk/meson/t7-pll.c line 81
Quoted 10 lines
drivers/clk/meson/t7-pll.c +8
-0#define MCLK_PLL_STS 0x14 +#define FPLL_CTRL0 0x00 +#define FPLL_CTRL1 0x04 +#define FPLL_CTRL2 0x08 +#define FPLL_CTRL3 0x0c +#define FPLL_CTRL4 0x10 +#define FPLL_CTRL5 0x14 +#define FPLL_CTRL6 0x18 +#define FPLL_STS 0x1c
The PLL you are adding is described in the datasheet as the MPLL. FPLL is nowhere to be found. Prefer using names that relate to the documentation.
If you must make a name up, you need to have a very good reason and to explain it.
Still from the public documentation, this PLL belong in the same device as MPLL0, MPLL1, etc ... BUT, I remember correctly the T7 initial submission, the fixed PLL and fdivs are supposed to be provided through SCMI clocks. Have you checked that ?
Quoted 266 lines
drivers/clk/meson/t7-pll.c +249
-0+static const struct pll_mult_range t7_media_pll_mult_range = { .min =125 , .max =250 ,@@ -1047,6 +1056,253 @@ static const struct meson_clkc_data t7_mclk_data = { }, }; +static struct clk_regmap t7_fpll_dco = { + .data = &(struct meson_clk_pll_data ){ + .en = { + .reg_off =FPLL_CTRL0 , + .shift =28 , + .width =1 , + }, + .m = { + .reg_off =FPLL_CTRL0 , + .shift =0 , + .width =8 , + }, + .n = { + .reg_off =FPLL_CTRL0 , + .shift =10 , + .width =5 , + }, + .frac = { + .reg_off =FPLL_CTRL1 , + .shift =0 , + .width =17 , + }, + .l = { + .reg_off =FPLL_CTRL0 , + .shift =31 , + .width =1 , + }, + .rst = { + .reg_off =FPLL_CTRL0 , + .shift =29 , + .width =1 , + }, + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll_dco" , + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data ) { + .fw_name ="xtal" , + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fpll = { + .data = &(struct clk_regmap_div_data ){ + .offset =FPLL_CTRL0 , + .shift =16 , + .width =2 , + .flags =CLK_DIVIDER_POWER_OF_TWO , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll" , + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll_dco.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div = { + .mult =1 , + .div =2 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =24 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv2p5_div = { + .mult =2 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2p5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =25 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2p5_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv3_div = { + .mult =1 , + .div =3 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv3 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =20 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv3_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv4_div = { + .mult =1 , + .div =4 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv4 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =21 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv4_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv5_div = { + .mult =1 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =22 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv5_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv7_div = { + .mult =1 , + .div =7 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv7 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =23 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv7_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_hw *t7_fpll_hw_clks[] = { + [CLKID_FPLL_DCO ] = &t7_fpll_dco.hw, + [CLKID_FPLL ] = &t7_fpll.hw, + [CLKID_FDIV2_DIV ] = &t7_fdiv2_div.hw, + [CLKID_FDIV2 ] = &t7_fdiv2.hw, + [CLKID_FDIV2P5_DIV ] = &t7_fdiv2p5_div.hw, + [CLKID_FDIV2P5 ] = &t7_fdiv2p5.hw, + [CLKID_FDIV3_DIV ] = &t7_fdiv3_div.hw, + [CLKID_FDIV3 ] = &t7_fdiv3.hw, + [CLKID_FDIV4_DIV ] = &t7_fdiv4_div.hw, + [CLKID_FDIV4 ] = &t7_fdiv4.hw, + [CLKID_FDIV5_DIV ] = &t7_fdiv5_div.hw, + [CLKID_FDIV5 ] = &t7_fdiv5.hw, + [CLKID_FDIV7_DIV ] = &t7_fdiv7_div.hw, + [CLKID_FDIV7 ] = &t7_fdiv7.hw, +}; + +static const struct meson_clkc_data t7_fpll_data = { + .hw_clks = { + .hws = t7_fpll_hw_clks, + .num =ARRAY_SIZE (t7_fpll_hw_clks), + }, +}; +static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible ="amlogic,t7-gp0-pll" , .data = &t7_gp0_data, }, { .compatible ="amlogic,t7-gp1-pll" , .data = &t7_gp1_data, },@@ -1055,6 +1311,7 @@ static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, }, { .compatible = "amlogic,t7-hdmi-pll", .data = &t7_hdmi_data, }, { .compatible = "amlogic,t7-mclk-pll", .data = &t7_mclk_data, }, + { .compatible = "amlogic,t7-fpll", .data = &t7_fpll_data, }, {} }; MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
Signature · 1 line
Jerome
Quoted 10 lines · Jerome Brunet
Quoted 2 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
As Krzysztof pointed out, a series like this needs a cover letter to explain what you are trying to acheive overall, and proper threading.
The description above is too vague.
Indeed, I will do that for the next one.
Quoted 26 lines
Quoted 11 lines
Signed-off-by Ronald Claveau <[email protected]>--- drivers/clk/meson/t7-pll.c | 257 +++++++++++++++++++++++++++++++++++++ 1 file changed, 257 insertions(+)drivers/clk/meson/t7-pll.c +0
-0@@ -71,6 +71,15 @@#define MCLK_PLL_CNTL4 0x10drivers/clk/meson/t7-pll.c line 81
Quoted 10 lines
drivers/clk/meson/t7-pll.c +8
-0#define MCLK_PLL_STS 0x14 +#define FPLL_CTRL0 0x00 +#define FPLL_CTRL1 0x04 +#define FPLL_CTRL2 0x08 +#define FPLL_CTRL3 0x0c +#define FPLL_CTRL4 0x10 +#define FPLL_CTRL5 0x14 +#define FPLL_CTRL6 0x18 +#define FPLL_STS 0x1cThe PLL you are adding is described in the datasheet as the MPLL. FPLL is nowhere to be found. Prefer using names that relate to the documentation.
Quoted 8 lines
If you must make a name up, you need to have a very good reason and to explain it.
Still from the public documentation, this PLL belong in the same device as MPLL0, MPLL1, etc ... BUT, I remember correctly the T7 initial submission, the fixed PLL and fdivs are supposed to be provided through SCMI clocks. Have you checked that ?
Yes, I read the initial submission, and I tried first with scmi-smc and scmi-mailbox, but with no success.
I will try it again and ask khadas team for more information related to this.
Quoted 267 lines
Quoted 266 lines
drivers/clk/meson/t7-pll.c +249
-0+static const struct pll_mult_range t7_media_pll_mult_range = { .min =125 , .max =250 ,@@ -1047,6 +1056,253 @@ static const struct meson_clkc_data t7_mclk_data = { }, }; +static struct clk_regmap t7_fpll_dco = { + .data = &(struct meson_clk_pll_data ){ + .en = { + .reg_off =FPLL_CTRL0 , + .shift =28 , + .width =1 , + }, + .m = { + .reg_off =FPLL_CTRL0 , + .shift =0 , + .width =8 , + }, + .n = { + .reg_off =FPLL_CTRL0 , + .shift =10 , + .width =5 , + }, + .frac = { + .reg_off =FPLL_CTRL1 , + .shift =0 , + .width =17 , + }, + .l = { + .reg_off =FPLL_CTRL0 , + .shift =31 , + .width =1 , + }, + .rst = { + .reg_off =FPLL_CTRL0 , + .shift =29 , + .width =1 , + }, + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll_dco" , + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data ) { + .fw_name ="xtal" , + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fpll = { + .data = &(struct clk_regmap_div_data ){ + .offset =FPLL_CTRL0 , + .shift =16 , + .width =2 , + .flags =CLK_DIVIDER_POWER_OF_TWO , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fpll" , + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll_dco.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv2_div = { + .mult =1 , + .div =2 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =24 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv2p5_div = { + .mult =2 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fpll.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv2p5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =25 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv2p5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv2p5_div.hw + }, + .num_parents =1 , + }, +}; + +static struct clk_fixed_factor t7_fdiv3_div = { + .mult =1 , + .div =3 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv3 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =20 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv3" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv3_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv4_div = { + .mult =1 , + .div =4 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv4 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =21 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv4" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv4_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv5_div = { + .mult =1 , + .div =5 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv5 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =22 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv5" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv5_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_fixed_factor t7_fdiv7_div = { + .mult =1 , + .div =7 , + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7_div" , + .ops = &clk_fixed_factor_ops, + .parent_hws = (const struct clk_hw *[]) { &t7_fpll.hw }, + .num_parents =1 , + }, +}; + +static struct clk_regmap t7_fdiv7 = { + .data = &(struct clk_regmap_gate_data ){ + .offset =FPLL_CTRL1 , + .bit_idx =23 , + }, + .hw.init = &(struct clk_init_data ){ + .name ="fdiv7" , + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &t7_fdiv7_div.hw + }, + .num_parents =1 , + .flags =CLK_IS_CRITICAL , + }, +}; + +static struct clk_hw *t7_fpll_hw_clks[] = { + [CLKID_FPLL_DCO ] = &t7_fpll_dco.hw, + [CLKID_FPLL ] = &t7_fpll.hw, + [CLKID_FDIV2_DIV ] = &t7_fdiv2_div.hw, + [CLKID_FDIV2 ] = &t7_fdiv2.hw, + [CLKID_FDIV2P5_DIV ] = &t7_fdiv2p5_div.hw, + [CLKID_FDIV2P5 ] = &t7_fdiv2p5.hw, + [CLKID_FDIV3_DIV ] = &t7_fdiv3_div.hw, + [CLKID_FDIV3 ] = &t7_fdiv3.hw, + [CLKID_FDIV4_DIV ] = &t7_fdiv4_div.hw, + [CLKID_FDIV4 ] = &t7_fdiv4.hw, + [CLKID_FDIV5_DIV ] = &t7_fdiv5_div.hw, + [CLKID_FDIV5 ] = &t7_fdiv5.hw, + [CLKID_FDIV7_DIV ] = &t7_fdiv7_div.hw, + [CLKID_FDIV7 ] = &t7_fdiv7.hw, +}; + +static const struct meson_clkc_data t7_fpll_data = { + .hw_clks = { + .hws = t7_fpll_hw_clks, + .num =ARRAY_SIZE (t7_fpll_hw_clks), + }, +}; +static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible ="amlogic,t7-gp0-pll" , .data = &t7_gp0_data, }, { .compatible ="amlogic,t7-gp1-pll" , .data = &t7_gp1_data, },@@ -1055,6 +1311,7 @@ static const struct of_device_id t7_pll_clkc_match_table[] = { { .compatible = "amlogic,t7-mpll", .data = &t7_mpll_data, }, { .compatible = "amlogic,t7-hdmi-pll", .data = &t7_hdmi_data, }, { .compatible = "amlogic,t7-mclk-pll", .data = &t7_mclk_data, }, + { .compatible = "amlogic,t7-fpll", .data = &t7_fpll_data, }, {} }; MODULE_DEVICE_TABLE(of, t7_pll_clkc_match_table);
Signature · 2 lines
Best regards, Ronald
Quoted 47 lines · Ronald Claveau
[ EXTERNAL EMAIL ]
Quoted 9 lines · Jerome Brunet
Quoted 2 lines · Ronald Claveau
Add PLL for the clock controller of the Amlogic T7 SoC family.
As Krzysztof pointed out, a series like this needs a cover letter to explain what you are trying to acheive overall, and proper threading.
The description above is too vague.
Indeed, I will do that for the next one.
Quoted 25 lines
Quoted 11 lines
Signed-off-by Ronald Claveau <[email protected]>--- drivers/clk/meson/t7-pll.c | 257 +++++++++++++++++++++++++++++++++++++ 1 file changed, 257 insertions(+)drivers/clk/meson/t7-pll.c +0
-0@@ -71,6 +71,15 @@#define MCLK_PLL_CNTL4 0x10drivers/clk/meson/t7-pll.c line 81
Quoted 10 lines
drivers/clk/meson/t7-pll.c +8
-0#define MCLK_PLL_STS 0x14 +#define FPLL_CTRL0 0x00 +#define FPLL_CTRL1 0x04 +#define FPLL_CTRL2 0x08 +#define FPLL_CTRL3 0x0c +#define FPLL_CTRL4 0x10 +#define FPLL_CTRL5 0x14 +#define FPLL_CTRL6 0x18 +#define FPLL_STS 0x1cThe PLL you are adding is described in the datasheet as the MPLL. FPLL is nowhere to be found. Prefer using names that relate to the documentation.
Quoted 8 lines
If you must make a name up, you need to have a very good reason and to explain it.
Still from the public documentation, this PLL belong in the same device as MPLL0, MPLL1, etc ... BUT, I remember correctly the T7 initial submission, the fixed PLL and fdivs are supposed to be provided through SCMI clocks. Have you checked that ?
Quoted 4 lines
Yes, I read the initial submission, and I tried first with scmi-smc and scmi-mailbox, but with no success.
I will try it again and ask khadas team for more information related to this.
The fixed pll and sys clocks registers cannot be accessed in kernel, so these clocks are
implemented in the Bootloader BL31.
Please ask the Khadas team to contact Amlogic for the latest Bootloader version, then you can use
the fixed pll and fdivs SCMI clocks defined in include/dt-bindings/clock/amlogic,t7,scmi.h.
Reference:
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drivers/clk/meson/t7-pll.c +1
-0+static const struct pll_mult_range t7_media_pll_mult_range = { .min =125 , .max =250 ,@@ -1047,6 +1056,253 @@ static const struct meson_clkc_data t7_mclk_data = { }, };
[...]
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Best regards,
Ronald_______________________________________________
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