dt-bindings: Microchip/Atmel AT91/SAMA system peripherals: convert to YAML
Subsystems (2)
v2 cover dt-bindings: Microchip/Atmel AT91/SAMA system peripherals: convert to YAML
Convert various legacy .txt bindings for Microchip (formerly Atmel) AT91/SAMA family system peripherals to proper YAML schemas. This includes:
- CHIPID (SoC ID register block)
- PIT (Period Interval Timer, old style)
- PIT64B (64-bit Period Interval Timer, newer parts)
- ST (System Timer, including watchdog subnode)
- RAMC/SDRAMC/DDRAMC/UDDRC (SDRAM/DDR memory controller
---
Changes in v2:
- Change email for maintainers.
- microchip,sam9x60-pit64b: modify compatible and clock-names in properties.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Akhila YS (5):
dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema
dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema
dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema
dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema
.../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 +++++++++++++++++++++ .../bindings/arm/atmel,at91rm9200-st.yaml | 65 +++++++++++++++++++++ .../bindings/arm/atmel,at91sam9260-pit.yaml | 49 ++++++++++++++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 48 --------------- .../bindings/arm/microchip,sam9x60-pit64b.yaml | 68 ++++++++++++++++++++++ .../bindings/arm/microchip,sama7g5-chipid.yaml | 41 +++++++++++++ 6 files changed, 290 insertions(+), 48 deletions(-)
---
base-commit: ca3a02fda4da8e2c1cb6baee5d72352e9e2cfaea
change-id: 20260128-arm-microchip-c0c0515024e6
Best regards,
Signature · 1 line
Akhila YS <[email protected]>
PATCH v2 1/5 dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema
Convert Atmel system registers binding to YAML format.
--- .../bindings/arm/microchip,sama7g5-chipid.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+)
Documentation/devicetree/bindings/arm/microchip,sama7g5-chipid.yaml new file +41 -0
@@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sama7g5-chipid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip RAMC SDRAM/DDR Controller + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + This binding describes the Atmel/Microchip Chip ID register block used + for SoC identification and revision information. It requires compatible + strings matching specific SoC families and a reg property defining the + register address and size. + +properties: + compatible: + enum: + - atmel,sama5d2-chipid + - microchip,sama7g5-chipid + - microchip,sama7d65-chipid + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + chipid@fc069000 { + compatible = "atmel,sama5d2-chipid"; + reg = <0xfc069000 0x8>; + }; +...
Signature · 1 line
2.43.0
PATCH v2 2/5 dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema
In reply to Akhila YSConvert Atmel Periodic interval timer (PIT) binding to YAML format.
--- .../bindings/arm/atmel,at91sam9260-pit.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+)
Documentation/devicetree/bindings/arm/atmel,at91sam9260-pit.yaml new file +49 -0
@@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel AT91SAM9260 Periodic Interval Timer (PIT) + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The Periodic Interval Timer (PIT) is part of the System Controller of + various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series). + It is a simple down-counter timer used mainly as the kernel tick source. + The PIT is clocked from the slow clock and shares a single IRQ line with + other System Controller peripherals. + +properties: + compatible: + const: atmel,at91sam9260-pit + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk32k>; + }; +...
Signature · 1 line
2.43.0
PATCH v2 3/5 dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema
In reply to Akhila YSConvert Atmel Periodic interval timer of 64bit (PIT64b) binding to YAML format.
Changes during conversion:
- Add missing compatible "microchip,sama7g5-pit64b" along with a fallback compatible "microchip,sam9x60-pit64b".
--- .../bindings/arm/microchip,sam9x60-pit64b.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+)
Documentation/devicetree/bindings/arm/microchip,sam9x60-pit64b.yaml new file +68 -0
@@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIT64B 64-bit Periodic Interval Timer + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The Microchip PIT64B is a 64-bit periodic interval timer used in + several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and + SAMA7D65 families. It provides extended timing range, flexible + clock selection and supports both periodic and one-shot interrupt + generation modes. + +properties: + compatible: + oneOf: + - const: microchip,sam9x60-pit64b + - items: + - enum: + - microchip,sama7d65-pit64b + - microchip,sama7g5-pit64b + - microchip,sam9x7-pit64b + - const: microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + enum: + - pclk + - gclk + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/at91.h> + timer@f0028000 { + compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; +...
Signature · 1 line
2.43.0
PATCH v2 4/5 dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
In reply to Akhila YSConvert System Timer binding to YAML format.
--- .../bindings/arm/atmel,at91rm9200-st.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +65 -0
@@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel System Timer + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The System Timer (ST) module in AT91RM9200 provides periodic tick and + alarm capabilities. It is exposed as a simple multi-function device + (simple-mfd + syscon) because it shares its register space and interrupt + with other System Controller blocks. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + watchdog: + type: object + description: Watchdog timer subnode. + properties: + compatible: + const: atmel,at91rm9200-wdt + required: + - compatible + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; +...
Signature · 1 line
2.43.0
Rob Herring (Arm)
maintainerRe: [PATCH v2 4/5] dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
Quoted 7 lines · Akhila YS
Convert System Timer binding to YAML format.
Signed-off-by Akhila YS <[email protected]>--- .../bindings/arm/atmel,at91rm9200-st.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.example.dtb: watchdog (atmel,at91rm9200-wdt): 'reg' is a required property
from schema $id: http://devicetree.org/schemas/watchdog/atmel,at91rm9200-wdt.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Re: [PATCH v2 4/5] dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
In reply to Akhila YSQuoted 45 lines · Akhila YS
Convert System Timer binding to YAML format.
Signed-off-by Akhila YS <[email protected]>--- .../bindings/arm/atmel,at91rm9200-st.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +32
-0@@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel System Timer + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The System Timer (ST) module in AT91RM9200 provides periodic tick and + alarm capabilities. It is exposed as a simple multi-function device + (simple-mfd + syscon) because it shares its register space and interrupt + with other System Controller blocks. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks:
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml line 42
Quoted 10 lines
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +10
-0+ maxItems: 1 + + watchdog: + type: object + description: Watchdog timer subnode. + properties: + compatible: + const: atmel,at91rm9200-wdt + required: + - compatible
This should just be a ref to the binding providing the watchdog.
I am guessing you didn't test this against all bindings, only against /this/ binding and therefore missed the fact that it doesn't comply with the binding for the watchdog itself.
Quoted 27 lines
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +23
-0+ +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; +...Signature · 2 lines
-- 2.43.0
Re: [PATCH v2 4/5] dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
Quoted 58 lines · Conor Dooley
Quoted 45 lines · Akhila YS
Convert System Timer binding to YAML format.
Signed-off-by Akhila YS <[email protected]>--- .../bindings/arm/atmel,at91rm9200-st.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +32
-0@@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel System Timer + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The System Timer (ST) module in AT91RM9200 provides periodic tick and + alarm capabilities. It is exposed as a simple multi-function device + (simple-mfd + syscon) because it shares its register space and interrupt + with other System Controller blocks. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks:Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml line 42
Quoted 10 lines
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +10
-0+ maxItems: 1 + + watchdog: + type: object + description: Watchdog timer subnode. + properties: + compatible: + const: atmel,at91rm9200-wdt + required: + - compatibleThis should just be a ref to the binding providing the watchdog.
Quoted 3 lines
I am guessing you didn't test this against all bindings, only against /this/ binding and therefore missed the fact that it doesn't comply with the binding for the watchdog itself.
Ok, i will take watchdog properties as a ref from different yaml.
Quoted 27 lines
Quoted 27 lines
Documentation/devicetree/bindings/arm/atmel,at91rm9200-st.yaml new file +23
-0+ +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; +...Signature · 2 lines
-- 2.43.0
Signature · 2 lines
Best Regards, Akhila.
PATCH v2 5/5 dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema
In reply to Akhila YSConvert RAMC SDRAM/DDR controller binding to YAML format.
--- .../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 ++++++++++++++++++++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 48 ---------------- 2 files changed, 67 insertions(+), 48 deletions(-)
Documentation/devicetree/bindings/arm/atmel,at91rm9200-sdramc.yaml new file +67 -0
@@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC) + +maintainers: + - Nicolas Ferre <[email protected]> + - Claudiu Beznea <[email protected]> + +description: + The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various + Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external + SDRAM / DDR memory. It is typically exposed as a syscon node for + register access from other drivers (e.g. for initialization or mode + configuration). No interrupts or clocks are usually required in the + binding. + +properties: + compatible: + oneOf: + - items: + - const: atmel,at91rm9200-sdramc + - const: syscon + - items: + - const: microchip,sama7d65-uddrc + - const: microchip,sama7g5-uddrc + - items: + enum: + - atmel,at91sam9260-sdramc + - atmel,at91sam9g45-ddramc + - atmel,sama5d3-ddramc + - microchip,sam9x60-ddramc + - microchip,sam9x7-ddramc + - microchip,sama7g5-uddrc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: ddrck + - const: mpddr + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/at91.h> + ramc@ffffe400 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe400 0x200>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>; + clock-names = "ddrck"; + }; +...
Documentation/devicetree/bindings/arm/atmel-sysregs.txt deleted +0 -48
48 lines not on this page · raw message
Signature · 1 line
2.43.0
Quoted 9 lines · Akhila YS
Convert various legacy .txt bindings for Microchip (formerly Atmel) AT91/SAMA family system peripherals to proper YAML schemas. This includes:
- CHIPID (SoC ID register block)
- PIT (Period Interval Timer, old style)
- PIT64B (64-bit Period Interval Timer, newer parts)
- ST (System Timer, including watchdog subnode)
- RAMC/SDRAMC/DDRAMC/UDDRC (SDRAM/DDR memory controller
Quoted 6 lines
Signed-off-by Akhila YS <[email protected]>---
Changes in v2:
- Change email for maintainers.
- microchip,sam9x60-pit64b: modify compatible and clock-names in properties.
- Link to v1: https://lore.kernel.org/r/[email protected]
Please give me a chance to respond to your messages before sending new versions. My comment about partial removal of the text file still applies. You've got to send another version anyway.
Quoted 24 lines
---
Akhila YS (5):
dt-bindings: arm: microchip,sama7g5-chipid : convert to DT schema
dt-bindings: arm: atmel,at91sam9260-pit: convert to DT schema
dt-bindings: arm: microchip,sam9x60-pit64b : convert to DT schema
dt-bindings: arm: atmel,at91rm9200-st: convert to DT schema
dt-bindings: arm: atmel,at91rm9200-sdramc: convert to DT schema.../bindings/arm/atmel,at91rm9200-sdramc.yaml | 67 +++++++++++++++++++++ .../bindings/arm/atmel,at91rm9200-st.yaml | 65 +++++++++++++++++++++ .../bindings/arm/atmel,at91sam9260-pit.yaml | 49 ++++++++++++++++ .../devicetree/bindings/arm/atmel-sysregs.txt | 48 --------------- .../bindings/arm/microchip,sam9x60-pit64b.yaml | 68 ++++++++++++++++++++++ .../bindings/arm/microchip,sama7g5-chipid.yaml | 41 +++++++++++++ 6 files changed, 290 insertions(+), 48 deletions(-)---
base-commit:ca3a02fda4da8e2c1cb6baee5d72352e9e2cfaea
change-id: 20260128-arm-microchip-c0c0515024e6Best regards,
Signature · 1 line
Akhila YS <[email protected]>
Quoted 17 lines · Conor Dooley
Quoted 9 lines · Akhila YS
Convert various legacy .txt bindings for Microchip (formerly Atmel) AT91/SAMA family system peripherals to proper YAML schemas. This includes:
- CHIPID (SoC ID register block)
- PIT (Period Interval Timer, old style)
- PIT64B (64-bit Period Interval Timer, newer parts)
- ST (System Timer, including watchdog subnode)
- RAMC/SDRAMC/DDRAMC/UDDRC (SDRAM/DDR memory controllerQuoted 6 lines
Signed-off-by Akhila YS <[email protected]>---
Changes in v2:
- Change email for maintainers.
- microchip,sam9x60-pit64b: modify compatible and clock-names in properties.
- Link to v1: https://lore.kernel.org/r/[email protected]
Quoted 3 lines
Please give me a chance to respond to your messages before sending new versions. My comment about partial removal of the text file still applies. You've got to send another version anyway.
Also, you probably should have checked the what I thought was Claudiu's email was actually correct. It's actually [email protected]!
Quoted 17 lines · Conor Dooley
Quoted 16 lines · Conor Dooley
Quoted 15 lines · Akhila YS
Convert various legacy .txt bindings for Microchip (formerly Atmel) AT91/SAMA family system peripherals to proper YAML schemas. This includes:
- CHIPID (SoC ID register block)
- PIT (Period Interval Timer, old style)
- PIT64B (64-bit Period Interval Timer, newer parts)
- ST (System Timer, including watchdog subnode)
- RAMC/SDRAMC/DDRAMC/UDDRC (SDRAM/DDR memory controllerSigned-off-by Akhila YS <[email protected]>---
Changes in v2:
- Change email for maintainers.
- microchip,sam9x60-pit64b: modify compatible and clock-names in properties.
- Link to v1: https://lore.kernel.org/r/[email protected]
Quoted 3 lines
Quoted 3 lines
Please give me a chance to respond to your messages before sending new versions. My comment about partial removal of the text file still applies. You've got to send another version anyway.
Ok, i partially remove binding from txt for each patch.
Quoted 2 lines
Also, you probably should have checked the what I thought was Claudiu's email was actually correct. It's actually [email protected]!
Sure, i will change email id for each patch under maintainer.
Signature · 2 lines
Best Regards, Akhila.