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Add support for Cix Sky1 resets

PATCH Superseded Gary Yang 3 participants 10 messages Feb 24 – Feb 25

Subsystems (3)
Device tree bindings Reset controller framework Arm/CIX SoC support

v9 of 10 Superseded Latest is v10 →

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Gary Yang

author maintainer
#0 lore raw

v9 cover Add support for Cix Sky1 resets

Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets

v9 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver

v8 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- remove "simple-mfd" strings

v7 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix build warning

v6 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style

v5 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-controller.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style

v4 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- add syscon
- refine reset driver
- fix dt-bindings style

v3 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- remove syscon

v2 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix dt-bindings style
- refine reset driver

Gary Yang (3):
dt-bindings: soc: cix: document the syscon on Sky1 SoC
reset: add Sky1 soc reset support
arm64: dts: cix: add support for cix sky1 resets

 .../soc/cix/cix,sky1-system-control.yaml      |  42 ++
 arch/arm64/boot/dts/cix/sky1.dtsi             |  12 +
 drivers/reset/Kconfig                         |   7 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sky1.c                    | 367 ++++++++++++++++++
 include/dt-bindings/reset/cix,sky1-rst-fch.h  |  42 ++
 include/dt-bindings/reset/cix,sky1-rst.h      | 164 ++++++++
 7 files changed, 635 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
 create mode 100644 drivers/reset/reset-sky1.c
 create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
 create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
Signature · 1 line
2.49.0
author maintainer
#1 lore raw

PATCH v9 1/3 dt-bindings: soc: cix: document the syscon on Sky1 SoC

There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle.

Signed-off-by Gary Yang <[email protected]>
---
 .../soc/cix/cix,sky1-system-control.yaml      |  42 +++++
 include/dt-bindings/reset/cix,sky1-rst-fch.h  |  42 +++++
 include/dt-bindings/reset/cix,sky1-rst.h      | 164 ++++++++++++++++++
 3 files changed, 248 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
 create mode 100644 include/dt-bindings/reset/cix,sky1-rst-fch.h
 create mode 100644 include/dt-bindings/reset/cix,sky1-rst.h
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +42 -0
new file mode 100644
index 000000000000..5507deb54ebd
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 SoC system control register region
+
+maintainers:
+  - Gary Yang <[email protected]>
+
+description:
+  An wide assortment of registers of the system controller on Sky1 SoC,
+  including resets, usb, wakeup sources and so on.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - cix,sky1-system-control
+          - cix,sky1-s5-system-control
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@16000000 {
+      compatible = "cix,sky1-s5-system-control", "syscon";
+      reg = <0x16000000 0x1000>;
+      #reset-cells = <1>;
+    };
include/dt-bindings/reset/cix,sky1-rst-fch.h new file +42 -0

42 lines not on this page · raw message

include/dt-bindings/reset/cix,sky1-rst.h new file +164 -0

164 lines not on this page · raw message

Signature · 1 line
2.49.0
NAK
#2 lore raw

Re: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

include/dt-bindings/reset/cix,sky1-rst-fch.h

Quoted 11 lines · Gary Yang
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +10 -0
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@16000000 {
+      compatible = "cix,sky1-s5-system-control", "syscon";
+      reg = <0x16000000 0x1000>;
+      #reset-cells = <1>;
+    };
include/dt-bindings/reset/cix,sky1-rst-fch.h +0 -0

I am not going to repeat my reviews.

NAK, I mark it as changes requested in Patchwork.

Krzysztof

#3 lore raw

Re: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

Quoted 14 lines · Krzysztof Kozlowski

include/dt-bindings/reset/cix,sky1-rst-fch.h

Quoted 11 lines · Gary Yang
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +10 -0
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@16000000 {
+      compatible = "cix,sky1-s5-system-control", "syscon";
+      reg = <0x16000000 0x1000>;
+      #reset-cells = <1>;
+    };
include/dt-bindings/reset/cix,sky1-rst-fch.h +0 -0

I am not going to repeat my reviews.

Quoting myself last time from second email:

"It's the last time I am asking you of it"

Quoted 5 lines

NAK, I mark it as changes requested in Patchwork.

Krzysztof

Best regards,
Krzysztof

author maintainer
#4 lore raw

回复: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

Hi Krzysztof:

I'm sorry for my mistakes.

Quoted 17 lines

EXTERNAL EMAIL

Quoted 12 lines · Krzysztof Kozlowski

Review

Quoted 11 lines · Gary Yang
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +10 -0
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@16000000 {
+      compatible = "cix,sky1-s5-system-control", "syscon";
+      reg = <0x16000000 0x1000>;
+      #reset-cells = <1>;
+    };
(quoted diff) +0 -0

b/include/dt-bindings/reset/cix,sky1-rst-fch.h

Quoted 1 line
Quoted 12 lines
Quoted 1 line

I am not going to repeat my reviews.

Quoting myself last time from second email:

"It's the last time I am asking you of it"

Quoted 5 lines

NAK, I mark it as changes requested in Patchwork.

Krzysztof

Sorry for missing your advices. We just come back from the Chinese New Year Festival.
It almost takes two weeks, so we forget your advices. Do you mean that cix,sky1-rst-fch.h should be named cix,sky1-system-control.h and cix,sky1-rst.h should be named cix,sky1-s5-system-control.h? Are there other advices forgot, except this one? Please give us one more chances.

If miss any information, please let us know. Thanks

Best Regards
Gary

Quoted 3 lines

Best regards,
Krzysztof

#5 lore raw

Re: 回复: [PATCH v9 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

Quoted 34 lines · Gary Yang

Hi Krzysztof:

I'm sorry for my mistakes.

Quoted 17 lines

EXTERNAL EMAIL

Quoted 12 lines · Krzysztof Kozlowski

Review

Quoted 11 lines · Gary Yang
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +10 -0
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@16000000 {
+      compatible = "cix,sky1-s5-system-control", "syscon";
+      reg = <0x16000000 0x1000>;
+      #reset-cells = <1>;
+    };
(quoted diff) +0 -0

b/include/dt-bindings/reset/cix,sky1-rst-fch.h

Quoted 1 line
Quoted 12 lines
Quoted 1 line

I am not going to repeat my reviews.

Quoting myself last time from second email:

"It's the last time I am asking you of it"

Quoted 5 lines

NAK, I mark it as changes requested in Patchwork.

Krzysztof

Quoted 6 lines

Sorry for missing your advices. We just come back from the Chinese New Year Festival.
It almost takes two weeks, so we forget your advices. Do you mean that cix,sky1-rst-fch.h should be named cix,sky1-system-control.h and cix,sky1-rst.h should be named cix,sky1-s5-system-control.h? Are there other advices forgot, except this one? Please give us one more chances.

If miss any information, please let us know. Thanks

The same filename as used for binding.

Best regards,
Krzysztof

author maintainer
#6 lore raw

PATCH v9 2/3 reset: add Sky1 soc reset support

In reply to Gary Yang

Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>
---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-sky1.c | 367 +++++++++++++++++++++++++++++++++++++
 3 files changed, 375 insertions(+)
 create mode 100644 drivers/reset/reset-sky1.c
drivers/reset/Kconfig +7 -0
index 6e5d6deffa7d..0aaac1b88d02 100644
@@ -291,6 +291,13 @@ config RESET_SIMPLE
 	   - SiFive FU740 SoCs
 	   - Sophgo SoCs
 
+config RESET_SKY1
+	bool "Cix Sky1 reset controller"
+	depends on OF && REGMAP_MMIO
+	depends on ARCH_CIX || COMPILE_TEST
+	help
+	  This enables the reset controller for Cix Sky1.
+
 config RESET_SOCFPGA
 	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
 	default ARM && ARCH_INTEL_SOCFPGA
drivers/reset/Makefile +1 -0
index 9c3e484dfd81..0d2e1329561d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
drivers/reset/reset-sky1.c new file +367 -0

367 lines not on this page · raw message

Signature · 1 line
2.49.0
maintainer
#7 lore raw

Re: [PATCH v9 2/3] reset: add Sky1 soc reset support

Quoted 3 lines · Gary Yang

Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

The second controller is not in S0 domain anymore? This change was not explained in the change log.

This seems to contradict a comment in "cix,sky1-s5-system-control" -> variant_sky1 -> sky1_src_signals:

	/* reset group1 for s0 domain modules */
Quoted 13 lines
Signed-off-by Gary Yang <[email protected]>
---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-sky1.c | 367 +++++++++++++++++++++++++++++++++++++
 3 files changed, 375 insertions(+)
 create mode 100644 drivers/reset/reset-sky1.c
drivers/reset/Kconfig +0 -0
index 6e5d6deffa7d..0aaac1b88d02 100644

drivers/reset/Kconfig config RESET_SIMPLE · line 296

Quoted 6 lines
drivers/reset/Kconfig +3 -0
@@ -291,6 +291,13 @@ config RESET_SIMPLE
 	   - SiFive FU740 SoCs
 	   - Sophgo SoCs
 
+config RESET_SKY1
+	bool "Cix Sky1 reset controller"
+	depends on OF && REGMAP_MMIO

Select REGMAP_MMIO instead.

Quoted 286 lines
drivers/reset/Kconfig +4 -0
+	depends on ARCH_CIX || COMPILE_TEST
+	help
+	  This enables the reset controller for Cix Sky1.
+
 config RESET_SOCFPGA
 	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
 	default ARM && ARCH_INTEL_SOCFPGA
drivers/reset/Makefile +1 -0
index 9c3e484dfd81..0d2e1329561d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
drivers/reset/reset-sky1.c new file +261 -0
new file mode 100644
index 000000000000..fb8a919fd3f7
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * CIX System Reset Controller (SRC) driver
+ *
+ * Author: Jerry Zhu <[email protected]>
+ */
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/cix,sky1-rst.h>
+#include <dt-bindings/reset/cix,sky1-rst-fch.h>
+
+#define SKY1_RESET_SLEEP_MIN_US		50
+#define SKY1_RESET_SLEEP_MAX_US		100
+
+struct sky1_src_signal {
+	unsigned int offset;
+	unsigned int bit;
+};
+
+struct sky1_src_variant {
+	const struct sky1_src_signal *signals;
+	unsigned int signals_num;
+};
+
+struct sky1_src {
+	struct reset_controller_dev rcdev;
+	const struct sky1_src_signal *signals;
+	struct regmap *regmap;
+};
+
+enum {
+	CSU_PM_RESET				= 0x304,
+	SENSORFUSION_RESET			= 0x308,
+	SENSORFUSION_NOC_RESET			= 0x30c,
+	RESET_GROUP0_S0_DOMAIN_0		= 0x400,
+	RESET_GROUP0_S0_DOMAIN_1		= 0x404,
+	RESET_GROUP1_USB_PHYS			= 0x408,
+	RESET_GROUP1_USB_CONTROLLERS		= 0x40c,
+	RESET_GROUP0_RCSU			= 0x800,
+	RESET_GROUP1_RCSU			= 0x804,
+};
+
+static const struct sky1_src_signal sky1_src_signals[] = {
+	/* reset group1 for s0 domain modules */
+	[SKY1_CSU_PM_RESET_N]		= { CSU_PM_RESET, BIT(0) },
+	[SKY1_SENSORFUSION_RESET_N]	= { SENSORFUSION_RESET, BIT(0) },
+	[SKY1_SENSORFUSION_NOC_RESET_N]	= { SENSORFUSION_NOC_RESET, BIT(0) },
+	[SKY1_DDRC_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(0) },
+	[SKY1_GIC_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(1) },
+	[SKY1_CI700_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(2) },
+	[SKY1_SYS_NI700_RESET_N]	= { RESET_GROUP0_S0_DOMAIN_0, BIT(3) },
+	[SKY1_MM_NI700_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(4) },
+	[SKY1_PCIE_NI700_RESET_N]	= { RESET_GROUP0_S0_DOMAIN_0, BIT(5) },
+	[SKY1_GPU_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(6) },
+	[SKY1_NPUTOP_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(7) },
+	[SKY1_NPUCORE0_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(8) },
+	[SKY1_NPUCORE1_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(9) },
+	[SKY1_NPUCORE2_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(10) },
+	[SKY1_VPU_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(11) },
+	[SKY1_ISP_SRESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(12) },
+	[SKY1_ISP_ARESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(13) },
+	[SKY1_ISP_HRESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(14) },
+	[SKY1_ISP_GDCRESET_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(15) },
+	[SKY1_DPU_RESET0_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(16) },
+	[SKY1_DPU_RESET1_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(17) },
+	[SKY1_DPU_RESET2_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(18) },
+	[SKY1_DPU_RESET3_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(19) },
+	[SKY1_DPU_RESET4_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(20) },
+	[SKY1_DP_RESET0_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(21) },
+	[SKY1_DP_RESET1_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(22) },
+	[SKY1_DP_RESET2_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(23) },
+	[SKY1_DP_RESET3_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(24) },
+	[SKY1_DP_RESET4_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(25) },
+	[SKY1_DP_PHY_RST_N]		= { RESET_GROUP0_S0_DOMAIN_0, BIT(26) },
+
+	/* reset group1 for s0 domain modules */
+	[SKY1_AUDIO_HIFI5_RESET_N]	= { RESET_GROUP0_S0_DOMAIN_1, BIT(0) },
+	[SKY1_AUDIO_HIFI5_NOC_RESET_N]	= { RESET_GROUP0_S0_DOMAIN_1, BIT(1) },
+	[SKY1_CSIDPHY_PRST0_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(2) },
+	[SKY1_CSIDPHY_CMNRST0_N]	= { RESET_GROUP0_S0_DOMAIN_1, BIT(3) },
+	[SKY1_CSI0_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(4) },
+	[SKY1_CSIDPHY_PRST1_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(5) },
+	[SKY1_CSIDPHY_CMNRST1_N]	= { RESET_GROUP0_S0_DOMAIN_1, BIT(6) },
+	[SKY1_CSI1_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(7) },
+	[SKY1_CSI2_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(8) },
+	[SKY1_CSI3_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(9) },
+	[SKY1_CSIBRDGE0_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(10) },
+	[SKY1_CSIBRDGE1_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(11) },
+	[SKY1_CSIBRDGE2_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(12) },
+	[SKY1_CSIBRDGE3_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(13) },
+	[SKY1_GMAC0_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(14) },
+	[SKY1_GMAC1_RST_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(15) },
+	[SKY1_PCIE0_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(16) },
+	[SKY1_PCIE1_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(17) },
+	[SKY1_PCIE2_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(18) },
+	[SKY1_PCIE3_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(19) },
+	[SKY1_PCIE4_RESET_N]		= { RESET_GROUP0_S0_DOMAIN_1, BIT(20) },
+
+	/* reset group1 for usb phys */
+	[SKY1_USB_DP_PHY0_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(0) },
+	[SKY1_USB_DP_PHY1_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(1) },
+	[SKY1_USB_DP_PHY2_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(2) },
+	[SKY1_USB_DP_PHY3_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(3) },
+	[SKY1_USB_DP_PHY0_RST_N]		= { RESET_GROUP1_USB_PHYS, BIT(4) },
+	[SKY1_USB_DP_PHY1_RST_N]		= { RESET_GROUP1_USB_PHYS, BIT(5) },
+	[SKY1_USB_DP_PHY2_RST_N]		= { RESET_GROUP1_USB_PHYS, BIT(6) },
+	[SKY1_USB_DP_PHY3_RST_N]		= { RESET_GROUP1_USB_PHYS, BIT(7) },
+	[SKY1_USBPHY_SS_PST_N]			= { RESET_GROUP1_USB_PHYS, BIT(8) },
+	[SKY1_USBPHY_SS_RST_N]			= { RESET_GROUP1_USB_PHYS, BIT(9) },
+	[SKY1_USBPHY_HS0_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(10) },
+	[SKY1_USBPHY_HS1_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(11) },
+	[SKY1_USBPHY_HS2_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(12) },
+	[SKY1_USBPHY_HS3_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(13) },
+	[SKY1_USBPHY_HS4_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(14) },
+	[SKY1_USBPHY_HS5_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(15) },
+	[SKY1_USBPHY_HS6_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(16) },
+	[SKY1_USBPHY_HS7_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(17) },
+	[SKY1_USBPHY_HS8_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(18) },
+	[SKY1_USBPHY_HS9_PRST_N]		= { RESET_GROUP1_USB_PHYS, BIT(19) },
+
+	/* reset group1 for usb controllers */
+	[SKY1_USBC_SS0_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(0) },
+	[SKY1_USBC_SS1_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(1) },
+	[SKY1_USBC_SS2_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(2) },
+	[SKY1_USBC_SS3_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(3) },
+	[SKY1_USBC_SS4_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(4) },
+	[SKY1_USBC_SS5_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(5) },
+	[SKY1_USBC_SS0_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(6) },
+	[SKY1_USBC_SS1_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(7) },
+	[SKY1_USBC_SS2_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(8) },
+	[SKY1_USBC_SS3_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(9) },
+	[SKY1_USBC_SS4_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(10) },
+	[SKY1_USBC_SS5_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(11) },
+	[SKY1_USBC_HS0_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(12) },
+	[SKY1_USBC_HS1_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(13) },
+	[SKY1_USBC_HS2_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(14) },
+	[SKY1_USBC_HS3_PRST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(15) },
+	[SKY1_USBC_HS0_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(16) },
+	[SKY1_USBC_HS1_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(17) },
+	[SKY1_USBC_HS2_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(18) },
+	[SKY1_USBC_HS3_RST_N]		= { RESET_GROUP1_USB_CONTROLLERS, BIT(19) },
+
+	/* reset group0 for rcsu */
+	[SKY1_AUDIO_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(0) },
+	[SKY1_CI700_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(1) },
+	[SKY1_CSI_RCSU0_RESET_N]		= { RESET_GROUP0_RCSU, BIT(2) },
+	[SKY1_CSI_RCSU1_RESET_N]		= { RESET_GROUP0_RCSU, BIT(3) },
+	[SKY1_CSU_PM_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(4) },
+	[SKY1_DDR_BROADCAST_RCSU_RESET_N]	= { RESET_GROUP0_RCSU, BIT(5) },
+	[SKY1_DDR_CTRL_RCSU_0_RESET_N]		= { RESET_GROUP0_RCSU, BIT(6) },
+	[SKY1_DDR_CTRL_RCSU_1_RESET_N]		= { RESET_GROUP0_RCSU, BIT(7) },
+	[SKY1_DDR_CTRL_RCSU_2_RESET_N]		= { RESET_GROUP0_RCSU, BIT(8) },
+	[SKY1_DDR_CTRL_RCSU_3_RESET_N]		= { RESET_GROUP0_RCSU, BIT(9) },
+	[SKY1_DDR_TZC400_RCSU_0_RESET_N]	= { RESET_GROUP0_RCSU, BIT(10) },
+	[SKY1_DDR_TZC400_RCSU_1_RESET_N]	= { RESET_GROUP0_RCSU, BIT(11) },
+	[SKY1_DDR_TZC400_RCSU_2_RESET_N]	= { RESET_GROUP0_RCSU, BIT(12) },
+	[SKY1_DDR_TZC400_RCSU_3_RESET_N]	= { RESET_GROUP0_RCSU, BIT(13) },
+	[SKY1_DP0_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(14) },
+	[SKY1_DP1_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(15) },
+	[SKY1_DP2_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(16) },
+	[SKY1_DP3_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(17) },
+	[SKY1_DP4_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(18) },
+	[SKY1_DPU0_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(19) },
+	[SKY1_DPU1_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(20) },
+	[SKY1_DPU2_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(21) },
+	[SKY1_DPU3_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(22) },
+	[SKY1_DPU4_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(23) },
+	[SKY1_DSU_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(24) },
+	[SKY1_FCH_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(25) },
+	[SKY1_GICD_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(26) },
+	[SKY1_GMAC_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(27) },
+	[SKY1_GPU_RCSU_RESET_N]			= { RESET_GROUP0_RCSU, BIT(28) },
+	[SKY1_ISP_RCSU0_RESET_N]		= { RESET_GROUP0_RCSU, BIT(29) },
+	[SKY1_ISP_RCSU1_RESET_N]		= { RESET_GROUP0_RCSU, BIT(30) },
+	[SKY1_NI700_MMHUB_RCSU_RESET_N]		= { RESET_GROUP0_RCSU, BIT(31) },
+
+	/* reset group1 for rcsu */
+	[SKY1_NPU_RCSU_RESET_N]			= { RESET_GROUP1_RCSU, BIT(0) },
+	[SKY1_NI700_PCIE_RCSU_RESET_N]		= { RESET_GROUP1_RCSU, BIT(1) },
+	[SKY1_PCIE_X421_RCSU_RESET_N]		= { RESET_GROUP1_RCSU, BIT(2) },
+	[SKY1_PCIE_X8_RCSU_RESET_N]		= { RESET_GROUP1_RCSU, BIT(3) },
+	[SKY1_SF_RCSU_RESET_N]			= { RESET_GROUP1_RCSU, BIT(4) },
+	[SKY1_RCSU_SMMU_MMHUB_RESET_N]		= { RESET_GROUP1_RCSU, BIT(5) },
+	[SKY1_RCSU_SMMU_PCIEHUB_RESET_N]	= { RESET_GROUP1_RCSU, BIT(6) },
+	[SKY1_RCSU_SYSHUB_RESET_N]		= { RESET_GROUP1_RCSU, BIT(7) },
+	[SKY1_NI700_SMN_RCSU_RESET_N]		= { RESET_GROUP1_RCSU, BIT(8) },
+	[SKY1_NI700_SYSHUB_RCSU_RESET_N]	= { RESET_GROUP1_RCSU, BIT(9) },
+	[SKY1_RCSU_USB2_HOST0_RESET_N]		= { RESET_GROUP1_RCSU, BIT(10) },
+	[SKY1_RCSU_USB2_HOST1_RESET_N]		= { RESET_GROUP1_RCSU, BIT(11) },
+	[SKY1_RCSU_USB2_HOST2_RESET_N]		= { RESET_GROUP1_RCSU, BIT(12) },
+	[SKY1_RCSU_USB2_HOST3_RESET_N]		= { RESET_GROUP1_RCSU, BIT(13) },
+	[SKY1_RCSU_USB3_TYPEA_DRD_RESET_N]	= { RESET_GROUP1_RCSU, BIT(14) },
+	[SKY1_RCSU_USB3_TYPEC_DRD_RESET_N]	= { RESET_GROUP1_RCSU, BIT(15) },
+	[SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N]	= { RESET_GROUP1_RCSU, BIT(16) },
+	[SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N]	= { RESET_GROUP1_RCSU, BIT(17) },
+	[SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N]	= { RESET_GROUP1_RCSU, BIT(18) },
+	[SKY1_VPU_RCSU_RESET_N]			= { RESET_GROUP1_RCSU, BIT(19) },
+};
+
+static const struct sky1_src_variant variant_sky1 = {
+	.signals = sky1_src_signals,
+	.signals_num = ARRAY_SIZE(sky1_src_signals),
+};
+
+enum {
+	FCH_SW_RST_FUNC			= 0x8,
+	FCH_SW_RST_BUS			= 0xc,
+	FCH_SW_XSPI			= 0x10,
+};
+
+static const struct sky1_src_signal sky1_src_fch_signals[] = {
+	/* resets for fch_sw_rst_func */
+	[SW_I3C0_RST_FUNC_G_N]	= { FCH_SW_RST_FUNC, BIT(0) },
+	[SW_I3C0_RST_FUNC_I_N]	= { FCH_SW_RST_FUNC, BIT(1) },
+	[SW_I3C1_RST_FUNC_G_N]	= { FCH_SW_RST_FUNC, BIT(2) },
+	[SW_I3C1_RST_FUNC_I_N]	= { FCH_SW_RST_FUNC, BIT(3) },
+	[SW_UART0_RST_FUNC_N]	= { FCH_SW_RST_FUNC, BIT(4) },
+	[SW_UART1_RST_FUNC_N]	= { FCH_SW_RST_FUNC, BIT(5) },
+	[SW_UART2_RST_FUNC_N]	= { FCH_SW_RST_FUNC, BIT(6) },
+	[SW_UART3_RST_FUNC_N]	= { FCH_SW_RST_FUNC, BIT(7) },
+	[SW_TIMER_RST_FUNC_N]	= { FCH_SW_RST_FUNC, BIT(20) },
+
+	/* resets for fch_sw_rst_bus */
+	[SW_I3C0_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(0) },
+	[SW_I3C1_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(1) },
+	[SW_DMA_RST_AXI_N]	= { FCH_SW_RST_BUS, BIT(2) },
+	[SW_UART0_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(4) },
+	[SW_UART1_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(5) },
+	[SW_UART2_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(6) },
+	[SW_UART3_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(7) },
+	[SW_SPI0_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(8) },
+	[SW_SPI1_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(9) },
+	[SW_I2C0_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(12) },
+	[SW_I2C1_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(13) },
+	[SW_I2C2_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(14) },
+	[SW_I2C3_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(15) },
+	[SW_I2C4_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(16) },
+	[SW_I2C5_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(17) },
+	[SW_I2C6_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(18) },
+	[SW_I2C7_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(19) },
+	[SW_GPIO_RST_APB_N]	= { FCH_SW_RST_BUS, BIT(21) },
+
+	/* resets for fch_sw_xspi */
+	[SW_XSPI_REG_RST_N]	= { FCH_SW_XSPI, BIT(0) },
+	[SW_XSPI_SYS_RST_N]	= { FCH_SW_XSPI, BIT(1) },
+};
+
+static const struct sky1_src_variant variant_sky1_fch = {
+	.signals = sky1_src_fch_signals,
+	.signals_num = ARRAY_SIZE(sky1_src_fch_signals),
+};
+
+static struct sky1_src *to_sky1_src(struct reset_controller_dev *rcdev)

drivers/reset/reset-sky1.c line 271

Quoted 10 lines
drivers/reset/reset-sky1.c new file +10 -0
+{
+	return container_of(rcdev, struct sky1_src, rcdev);
+}
+
+static int sky1_reset_set(struct reset_controller_dev *rcdev,
+			  unsigned long id, bool assert)
+{
+	struct sky1_src *sky1src = to_sky1_src(rcdev);
+	const struct sky1_src_signal *signal = &sky1src->signals[id];
+	unsigned int value = assert ? 0 : sky1src->signals[id].bit;

This could be shortened to:

	unsigned int value = assert ? 0 : signal->bit;
Quoted 55 lines
drivers/reset/reset-sky1.c new file +55 -0
+
+	return regmap_update_bits(sky1src->regmap,
+				  signal->offset, signal->bit, value);
+}
+
+static int sky1_reset_assert(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	sky1_reset_set(rcdev, id, true);
+	usleep_range(SKY1_RESET_SLEEP_MIN_US,
+		     SKY1_RESET_SLEEP_MAX_US);
+	return 0;
+}
+
+static int sky1_reset_deassert(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	sky1_reset_set(rcdev, id, false);
+	usleep_range(SKY1_RESET_SLEEP_MIN_US,
+		     SKY1_RESET_SLEEP_MAX_US);
+	return 0;
+}
+
+static int sky1_reset(struct reset_controller_dev *rcdev,
+		      unsigned long id)
+{
+	sky1_reset_assert(rcdev, id);
+	sky1_reset_deassert(rcdev, id);
+	return 0;
+}
+
+static int sky1_reset_status(struct reset_controller_dev *rcdev,
+			     unsigned long id)
+{
+	unsigned int value = 0;
+	struct sky1_src *sky1src = to_sky1_src(rcdev);
+	const struct sky1_src_signal *signal = &sky1src->signals[id];
+
+	regmap_read(sky1src->regmap, signal->offset, &value);
+	return !(value & signal->bit);
+}
+
+static const struct reset_control_ops sky1_src_ops = {
+	.reset    = sky1_reset,
+	.assert   = sky1_reset_assert,
+	.deassert = sky1_reset_deassert,
+	.status   = sky1_reset_status
+};
+
+static int sky1_reset_probe(struct platform_device *pdev)
+{
+	struct sky1_src *sky1src;
+	struct device *dev = &pdev->dev;
+	const struct sky1_src_variant *variant;
+

drivers/reset/reset-sky1.c line 336

Quoted 10 lines
drivers/reset/reset-sky1.c new file +10 -0
+	sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL);
+	if (!sky1src)
+		return -ENOMEM;
+
+	variant = of_device_get_match_data(dev);
+
+	sky1src->regmap = device_node_to_regmap(dev->of_node);
+	if (IS_ERR(sky1src->regmap)) {
+		dev_err(dev, "Unable to get sky1-src regmap");
+		return PTR_ERR(sky1src->regmap);

This can be simplified with dev_err_probe().

regards
Philipp

author maintainer
#8 lore raw

回复: [PATCH v9 2/3] reset: add Sky1 soc reset support

Hi Philipp:

Thanks for your comments

Quoted 9 lines

EXTERNAL EMAIL

CAUTION: Suspicious Email from unusual domain.

Quoted 3 lines · Gary Yang

Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Quoted 8 lines

The second controller is not in S0 domain anymore? This change was not explained in the change log.

This seems to contradict a comment in "cix,sky1-s5-system-control" -> variant_sky1 -> sky1_src_signals:

        /* reset group1 for s0 domain modules */

I'm sorry. It makes you confuse. It doesn't have any changes. The reset controller in S0 domain is only used in S0 domain. The other one in S5 domain is both used in S0 and S5 domain. This description maybe be different from the different views.

Quoted 17 lines
Quoted 17 lines
Signed-off-by Gary Yang <[email protected]>
---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-sky1.c | 367
+++++++++++++++++++++++++++++++++++++
 3 files changed, 375 insertions(+)
 create mode 100644 drivers/reset/reset-sky1.c
drivers/reset/Kconfig index renamed from drivers/reset/Kconfig +0 -0

6e5d6deffa7d..0aaac1b88d02 100644

drivers/reset/Kconfig +0 -0
@@ -291,6 +291,13 @@ config RESET_SIMPLE
         - SiFive FU740 SoCs
         - Sophgo SoCs
Quoted 6 lines

drivers/reset/Kconfig config RESET_SIMPLE · line 296

Quoted 3 lines
drivers/reset/Kconfig +3 -0
+config RESET_SKY1
+     bool "Cix Sky1 reset controller"
+     depends on OF && REGMAP_MMIO

Select REGMAP_MMIO instead.

OK, we will do it next version.

Quoted 437 lines

drivers/reset/Kconfig config RESET_SIMPLE

Quoted 6 lines
drivers/reset/Kconfig +4 -0
+     depends on ARCH_CIX || COMPILE_TEST
+     help
+       This enables the reset controller for Cix Sky1.
+
 config RESET_SOCFPGA
      bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM

|| !ARCH_INTEL_SOCFPGA)
>       default ARM && ARCH_INTEL_SOCFPGA diff --git
Quoted 61 lines

a/drivers/reset/Makefile b/drivers/reset/Makefile index 9c3e484dfd81..0d2e1329561d 100644

drivers/reset/Makefile +0 -0
@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=

reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o diff --git
a/drivers/reset/reset-sky1.c b/drivers/reset/reset-sky1.c new file mode 100644 index 000000000000..fb8a919fd3f7

drivers/reset/reset-sky1.c new file +43 -0
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ *
+ * CIX System Reset Controller (SRC) driver
+ *
+ * Author: Jerry Zhu <[email protected]>  */
+
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/reset/cix,sky1-rst.h>
+#include <dt-bindings/reset/cix,sky1-rst-fch.h>
+
+#define SKY1_RESET_SLEEP_MIN_US              50
+#define SKY1_RESET_SLEEP_MAX_US              100
+
+struct sky1_src_signal {
+     unsigned int offset;
+     unsigned int bit;
+};
+
+struct sky1_src_variant {
+     const struct sky1_src_signal *signals;
+     unsigned int signals_num;
+};
+
+struct sky1_src {
+     struct reset_controller_dev rcdev;
+     const struct sky1_src_signal *signals;
+     struct regmap *regmap;
+};
+
+enum {
+     CSU_PM_RESET                            = 0x304,
+     SENSORFUSION_RESET                      = 0x308,
+     SENSORFUSION_NOC_RESET                  = 0x30c,
+     RESET_GROUP0_S0_DOMAIN_0                = 0x400,
+     RESET_GROUP0_S0_DOMAIN_1                = 0x404,

drivers/reset/reset-sky1.c line 53

Quoted 10 lines
drivers/reset/reset-sky1.c new file +10 -0
+     RESET_GROUP1_USB_PHYS                   = 0x408,
+     RESET_GROUP1_USB_CONTROLLERS            = 0x40c,
+     RESET_GROUP0_RCSU                       = 0x800,
+     RESET_GROUP1_RCSU                       = 0x804,
+};
+
+static const struct sky1_src_signal sky1_src_signals[] = {
+     /* reset group1 for s0 domain modules */
+     [SKY1_CSU_PM_RESET_N]           = { CSU_PM_RESET, BIT(0) },
+     [SKY1_SENSORFUSION_RESET_N]     = { SENSORFUSION_RESET,

BIT(0) },

drivers/reset/reset-sky1.c line 54

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_SENSORFUSION_NOC_RESET_N] =

{ SENSORFUSION_NOC_RESET, BIT(0) },

drivers/reset/reset-sky1.c line 55

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDRC_RESET_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(0) },

drivers/reset/reset-sky1.c line 56

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GIC_RESET_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(1) },

drivers/reset/reset-sky1.c line 57

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CI700_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(2) },

drivers/reset/reset-sky1.c line 58

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_SYS_NI700_RESET_N]        =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(3) },

drivers/reset/reset-sky1.c line 59

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_MM_NI700_RESET_N]         =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(4) },

drivers/reset/reset-sky1.c line 60

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE_NI700_RESET_N]       =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(5) },

drivers/reset/reset-sky1.c line 61

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GPU_RESET_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(6) },

drivers/reset/reset-sky1.c line 62

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NPUTOP_RESET_N]           =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(7) },

drivers/reset/reset-sky1.c line 63

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NPUCORE0_RESET_N]         =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(8) },

drivers/reset/reset-sky1.c line 64

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NPUCORE1_RESET_N]         =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(9) },

drivers/reset/reset-sky1.c line 65

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NPUCORE2_RESET_N]         =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(10) },

drivers/reset/reset-sky1.c line 66

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_VPU_RESET_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(11) },

drivers/reset/reset-sky1.c line 67

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_SRESET_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(12) },

drivers/reset/reset-sky1.c line 68

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_ARESET_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(13) },

drivers/reset/reset-sky1.c line 69

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_HRESET_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(14) },

drivers/reset/reset-sky1.c line 70

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_GDCRESET_N]           =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(15) },

drivers/reset/reset-sky1.c line 71

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU_RESET0_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(16) },

drivers/reset/reset-sky1.c line 72

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU_RESET1_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(17) },

drivers/reset/reset-sky1.c line 73

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU_RESET2_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(18) },

drivers/reset/reset-sky1.c line 74

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU_RESET3_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(19) },

drivers/reset/reset-sky1.c line 75

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU_RESET4_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(20) },

drivers/reset/reset-sky1.c line 76

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_RESET0_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(21) },

drivers/reset/reset-sky1.c line 77

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_RESET1_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(22) },

drivers/reset/reset-sky1.c line 78

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_RESET2_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(23) },

drivers/reset/reset-sky1.c line 79

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_RESET3_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(24) },

drivers/reset/reset-sky1.c line 80

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_RESET4_N]              =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(25) },

drivers/reset/reset-sky1.c line 81

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP_PHY_RST_N]             =

{ RESET_GROUP0_S0_DOMAIN_0, BIT(26) },

drivers/reset/reset-sky1.c

Quoted 3 lines
drivers/reset/reset-sky1.c new file +3 -0
+
+     /* reset group1 for s0 domain modules */
+     [SKY1_AUDIO_HIFI5_RESET_N]      =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(0) },

drivers/reset/reset-sky1.c line 85

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_AUDIO_HIFI5_NOC_RESET_N]  =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(1) },

drivers/reset/reset-sky1.c line 86

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIDPHY_PRST0_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(2) },

drivers/reset/reset-sky1.c line 87

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIDPHY_CMNRST0_N]        =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(3) },

drivers/reset/reset-sky1.c line 88

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI0_RST_N]               =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(4) },

drivers/reset/reset-sky1.c line 89

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIDPHY_PRST1_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(5) },

drivers/reset/reset-sky1.c line 90

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIDPHY_CMNRST1_N]        =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(6) },

drivers/reset/reset-sky1.c line 91

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI1_RST_N]               =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(7) },

drivers/reset/reset-sky1.c line 92

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI2_RST_N]               =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(8) },

drivers/reset/reset-sky1.c line 93

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI3_RST_N]               =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(9) },

drivers/reset/reset-sky1.c line 94

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIBRDGE0_RST_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(10) },

drivers/reset/reset-sky1.c line 95

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIBRDGE1_RST_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(11) },

drivers/reset/reset-sky1.c line 96

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIBRDGE2_RST_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(12) },

drivers/reset/reset-sky1.c line 97

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSIBRDGE3_RST_N]          =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(13) },

drivers/reset/reset-sky1.c line 98

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GMAC0_RST_N]              =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(14) },

drivers/reset/reset-sky1.c line 99

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GMAC1_RST_N]              =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(15) },

drivers/reset/reset-sky1.c line 100

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE0_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(16) },

drivers/reset/reset-sky1.c line 101

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE1_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(17) },

drivers/reset/reset-sky1.c line 102

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE2_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(18) },

drivers/reset/reset-sky1.c line 103

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE3_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(19) },

drivers/reset/reset-sky1.c line 104

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE4_RESET_N]            =

{ RESET_GROUP0_S0_DOMAIN_1, BIT(20) },

drivers/reset/reset-sky1.c

Quoted 3 lines
drivers/reset/reset-sky1.c new file +3 -0
+
+     /* reset group1 for usb phys */
+     [SKY1_USB_DP_PHY0_PRST_N]               =

{ RESET_GROUP1_USB_PHYS, BIT(0) },

drivers/reset/reset-sky1.c line 108

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY1_PRST_N]               =

{ RESET_GROUP1_USB_PHYS, BIT(1) },

drivers/reset/reset-sky1.c line 109

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY2_PRST_N]               =

{ RESET_GROUP1_USB_PHYS, BIT(2) },

drivers/reset/reset-sky1.c line 110

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY3_PRST_N]               =

{ RESET_GROUP1_USB_PHYS, BIT(3) },

drivers/reset/reset-sky1.c line 111

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY0_RST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(4) },

drivers/reset/reset-sky1.c line 112

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY1_RST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(5) },

drivers/reset/reset-sky1.c line 113

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY2_RST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(6) },

drivers/reset/reset-sky1.c line 114

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USB_DP_PHY3_RST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(7) },

drivers/reset/reset-sky1.c line 115

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_SS_PST_N]                  =

{ RESET_GROUP1_USB_PHYS, BIT(8) },

drivers/reset/reset-sky1.c line 116

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_SS_RST_N]                  =

{ RESET_GROUP1_USB_PHYS, BIT(9) },

drivers/reset/reset-sky1.c line 117

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS0_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(10) },

drivers/reset/reset-sky1.c line 118

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS1_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(11) },

drivers/reset/reset-sky1.c line 119

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS2_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(12) },

drivers/reset/reset-sky1.c line 120

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS3_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(13) },

drivers/reset/reset-sky1.c line 121

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS4_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(14) },

drivers/reset/reset-sky1.c line 122

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS5_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(15) },

drivers/reset/reset-sky1.c line 123

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS6_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(16) },

drivers/reset/reset-sky1.c line 124

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS7_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(17) },

drivers/reset/reset-sky1.c line 125

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS8_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(18) },

drivers/reset/reset-sky1.c line 126

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBPHY_HS9_PRST_N]                =

{ RESET_GROUP1_USB_PHYS, BIT(19) },

drivers/reset/reset-sky1.c

Quoted 3 lines
drivers/reset/reset-sky1.c new file +3 -0
+
+     /* reset group1 for usb controllers */
+     [SKY1_USBC_SS0_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(0) },

drivers/reset/reset-sky1.c line 130

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS1_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(1) },

drivers/reset/reset-sky1.c line 131

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS2_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(2) },

drivers/reset/reset-sky1.c line 132

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS3_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(3) },

drivers/reset/reset-sky1.c line 133

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS4_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(4) },

drivers/reset/reset-sky1.c line 134

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS5_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(5) },

drivers/reset/reset-sky1.c line 135

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS0_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(6) },

drivers/reset/reset-sky1.c line 136

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS1_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(7) },

drivers/reset/reset-sky1.c line 137

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS2_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(8) },

drivers/reset/reset-sky1.c line 138

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS3_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(9) },

drivers/reset/reset-sky1.c line 139

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS4_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(10) },

drivers/reset/reset-sky1.c line 140

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_SS5_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(11) },

drivers/reset/reset-sky1.c line 141

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS0_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(12) },

drivers/reset/reset-sky1.c line 142

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS1_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(13) },

drivers/reset/reset-sky1.c line 143

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS2_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(14) },

drivers/reset/reset-sky1.c line 144

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS3_PRST_N]          =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(15) },

drivers/reset/reset-sky1.c line 145

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS0_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(16) },

drivers/reset/reset-sky1.c line 146

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS1_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(17) },

drivers/reset/reset-sky1.c line 147

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS2_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(18) },

drivers/reset/reset-sky1.c line 148

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_USBC_HS3_RST_N]           =

{ RESET_GROUP1_USB_CONTROLLERS, BIT(19) },

drivers/reset/reset-sky1.c

Quoted 3 lines
drivers/reset/reset-sky1.c new file +3 -0
+
+     /* reset group0 for rcsu */
+     [SKY1_AUDIO_RCSU_RESET_N]               =

{ RESET_GROUP0_RCSU, BIT(0) },

drivers/reset/reset-sky1.c line 152

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CI700_RCSU_RESET_N]               =

{ RESET_GROUP0_RCSU, BIT(1) },

drivers/reset/reset-sky1.c line 153

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI_RCSU0_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(2) },

drivers/reset/reset-sky1.c line 154

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSI_RCSU1_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(3) },

drivers/reset/reset-sky1.c line 155

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_CSU_PM_RCSU_RESET_N]              =

{ RESET_GROUP0_RCSU, BIT(4) },

drivers/reset/reset-sky1.c line 156

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_BROADCAST_RCSU_RESET_N]       =

{ RESET_GROUP0_RCSU, BIT(5) },

drivers/reset/reset-sky1.c line 157

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_CTRL_RCSU_0_RESET_N]          =

{ RESET_GROUP0_RCSU, BIT(6) },

drivers/reset/reset-sky1.c line 158

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_CTRL_RCSU_1_RESET_N]          =

{ RESET_GROUP0_RCSU, BIT(7) },

drivers/reset/reset-sky1.c line 159

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_CTRL_RCSU_2_RESET_N]          =

{ RESET_GROUP0_RCSU, BIT(8) },

drivers/reset/reset-sky1.c line 160

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_CTRL_RCSU_3_RESET_N]          =

{ RESET_GROUP0_RCSU, BIT(9) },

drivers/reset/reset-sky1.c line 161

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_TZC400_RCSU_0_RESET_N]        =

{ RESET_GROUP0_RCSU, BIT(10) },

drivers/reset/reset-sky1.c line 162

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_TZC400_RCSU_1_RESET_N]        =

{ RESET_GROUP0_RCSU, BIT(11) },

drivers/reset/reset-sky1.c line 163

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_TZC400_RCSU_2_RESET_N]        =

{ RESET_GROUP0_RCSU, BIT(12) },

drivers/reset/reset-sky1.c line 164

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DDR_TZC400_RCSU_3_RESET_N]        =

{ RESET_GROUP0_RCSU, BIT(13) },

drivers/reset/reset-sky1.c line 165

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP0_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(14) },

drivers/reset/reset-sky1.c line 166

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP1_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(15) },

drivers/reset/reset-sky1.c line 167

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP2_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(16) },

drivers/reset/reset-sky1.c line 168

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP3_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(17) },

drivers/reset/reset-sky1.c line 169

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DP4_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(18) },

drivers/reset/reset-sky1.c line 170

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU0_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(19) },

drivers/reset/reset-sky1.c line 171

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU1_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(20) },

drivers/reset/reset-sky1.c line 172

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU2_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(21) },

drivers/reset/reset-sky1.c line 173

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU3_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(22) },

drivers/reset/reset-sky1.c line 174

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DPU4_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(23) },

drivers/reset/reset-sky1.c line 175

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_DSU_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(24) },

drivers/reset/reset-sky1.c line 176

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_FCH_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(25) },

drivers/reset/reset-sky1.c line 177

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GICD_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(26) },

drivers/reset/reset-sky1.c line 178

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GMAC_RCSU_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(27) },

drivers/reset/reset-sky1.c line 179

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_GPU_RCSU_RESET_N]                 =

{ RESET_GROUP0_RCSU, BIT(28) },

drivers/reset/reset-sky1.c line 180

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_RCSU0_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(29) },

drivers/reset/reset-sky1.c line 181

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_ISP_RCSU1_RESET_N]                =

{ RESET_GROUP0_RCSU, BIT(30) },

drivers/reset/reset-sky1.c line 182

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NI700_MMHUB_RCSU_RESET_N]         =

{ RESET_GROUP0_RCSU, BIT(31) },

drivers/reset/reset-sky1.c

Quoted 3 lines
drivers/reset/reset-sky1.c new file +3 -0
+
+     /* reset group1 for rcsu */
+     [SKY1_NPU_RCSU_RESET_N]                 =

{ RESET_GROUP1_RCSU, BIT(0) },

drivers/reset/reset-sky1.c line 186

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NI700_PCIE_RCSU_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(1) },

drivers/reset/reset-sky1.c line 187

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE_X421_RCSU_RESET_N]           =

{ RESET_GROUP1_RCSU, BIT(2) },

drivers/reset/reset-sky1.c line 188

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_PCIE_X8_RCSU_RESET_N]             =

{ RESET_GROUP1_RCSU, BIT(3) },

drivers/reset/reset-sky1.c line 189

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_SF_RCSU_RESET_N]                  =

{ RESET_GROUP1_RCSU, BIT(4) },

drivers/reset/reset-sky1.c line 190

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_SMMU_MMHUB_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(5) },

drivers/reset/reset-sky1.c line 191

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_SMMU_PCIEHUB_RESET_N]        =

{ RESET_GROUP1_RCSU, BIT(6) },

drivers/reset/reset-sky1.c line 192

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_SYSHUB_RESET_N]              =

{ RESET_GROUP1_RCSU, BIT(7) },

drivers/reset/reset-sky1.c line 193

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NI700_SMN_RCSU_RESET_N]           =

{ RESET_GROUP1_RCSU, BIT(8) },

drivers/reset/reset-sky1.c line 194

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_NI700_SYSHUB_RCSU_RESET_N]        =

{ RESET_GROUP1_RCSU, BIT(9) },

drivers/reset/reset-sky1.c line 195

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB2_HOST0_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(10) },

drivers/reset/reset-sky1.c line 196

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB2_HOST1_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(11) },

drivers/reset/reset-sky1.c line 197

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB2_HOST2_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(12) },

drivers/reset/reset-sky1.c line 198

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB2_HOST3_RESET_N]          =

{ RESET_GROUP1_RCSU, BIT(13) },

drivers/reset/reset-sky1.c line 199

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB3_TYPEA_DRD_RESET_N]      =

{ RESET_GROUP1_RCSU, BIT(14) },

drivers/reset/reset-sky1.c line 200

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB3_TYPEC_DRD_RESET_N]      =

{ RESET_GROUP1_RCSU, BIT(15) },

drivers/reset/reset-sky1.c line 201

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB3_TYPEC_HOST0_RESET_N]    =

{ RESET_GROUP1_RCSU, BIT(16) },

drivers/reset/reset-sky1.c line 202

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB3_TYPEC_HOST1_RESET_N]    =

{ RESET_GROUP1_RCSU, BIT(17) },

drivers/reset/reset-sky1.c line 203

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_RCSU_USB3_TYPEC_HOST2_RESET_N]    =

{ RESET_GROUP1_RCSU, BIT(18) },

drivers/reset/reset-sky1.c line 204

Quoted 1 line
drivers/reset/reset-sky1.c new file +1 -0
+     [SKY1_VPU_RCSU_RESET_N]                 =

{ RESET_GROUP1_RCSU, BIT(19) },

Quoted 52 lines
drivers/reset/reset-sky1.c new file +52 -0
+};
+
+static const struct sky1_src_variant variant_sky1 = {
+     .signals = sky1_src_signals,
+     .signals_num = ARRAY_SIZE(sky1_src_signals), };
+
+enum {
+     FCH_SW_RST_FUNC                 = 0x8,
+     FCH_SW_RST_BUS                  = 0xc,
+     FCH_SW_XSPI                     = 0x10,
+};
+
+static const struct sky1_src_signal sky1_src_fch_signals[] = {
+     /* resets for fch_sw_rst_func */
+     [SW_I3C0_RST_FUNC_G_N]  = { FCH_SW_RST_FUNC, BIT(0) },
+     [SW_I3C0_RST_FUNC_I_N]  = { FCH_SW_RST_FUNC, BIT(1) },
+     [SW_I3C1_RST_FUNC_G_N]  = { FCH_SW_RST_FUNC, BIT(2) },
+     [SW_I3C1_RST_FUNC_I_N]  = { FCH_SW_RST_FUNC, BIT(3) },
+     [SW_UART0_RST_FUNC_N]   = { FCH_SW_RST_FUNC, BIT(4) },
+     [SW_UART1_RST_FUNC_N]   = { FCH_SW_RST_FUNC, BIT(5) },
+     [SW_UART2_RST_FUNC_N]   = { FCH_SW_RST_FUNC, BIT(6) },
+     [SW_UART3_RST_FUNC_N]   = { FCH_SW_RST_FUNC, BIT(7) },
+     [SW_TIMER_RST_FUNC_N]   = { FCH_SW_RST_FUNC, BIT(20) },
+
+     /* resets for fch_sw_rst_bus */
+     [SW_I3C0_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(0) },
+     [SW_I3C1_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(1) },
+     [SW_DMA_RST_AXI_N]      = { FCH_SW_RST_BUS, BIT(2) },
+     [SW_UART0_RST_APB_N]    = { FCH_SW_RST_BUS, BIT(4) },
+     [SW_UART1_RST_APB_N]    = { FCH_SW_RST_BUS, BIT(5) },
+     [SW_UART2_RST_APB_N]    = { FCH_SW_RST_BUS, BIT(6) },
+     [SW_UART3_RST_APB_N]    = { FCH_SW_RST_BUS, BIT(7) },
+     [SW_SPI0_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(8) },
+     [SW_SPI1_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(9) },
+     [SW_I2C0_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(12) },
+     [SW_I2C1_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(13) },
+     [SW_I2C2_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(14) },
+     [SW_I2C3_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(15) },
+     [SW_I2C4_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(16) },
+     [SW_I2C5_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(17) },
+     [SW_I2C6_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(18) },
+     [SW_I2C7_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(19) },
+     [SW_GPIO_RST_APB_N]     = { FCH_SW_RST_BUS, BIT(21) },
+
+     /* resets for fch_sw_xspi */
+     [SW_XSPI_REG_RST_N]     = { FCH_SW_XSPI, BIT(0) },
+     [SW_XSPI_SYS_RST_N]     = { FCH_SW_XSPI, BIT(1) },
+};
+
+static const struct sky1_src_variant variant_sky1_fch = {
+     .signals = sky1_src_fch_signals,
+     .signals_num = ARRAY_SIZE(sky1_src_fch_signals), };

drivers/reset/reset-sky1.c line 271

Quoted 10 lines
drivers/reset/reset-sky1.c new file +10 -0
+
+static struct sky1_src *to_sky1_src(struct reset_controller_dev
+*rcdev) {
+     return container_of(rcdev, struct sky1_src, rcdev); }
+
+static int sky1_reset_set(struct reset_controller_dev *rcdev,
+                       unsigned long id, bool assert) {
+     struct sky1_src *sky1src = to_sky1_src(rcdev);
+     const struct sky1_src_signal *signal = &sky1src->signals[id];
+     unsigned int value = assert ? 0 : sky1src->signals[id].bit;

This could be shortened to:

Quoted 2 lines
        unsigned int value = assert ? 0 : signal->bit;

Yes, you're right. We will do it next version

Quoted 54 lines
Quoted 54 lines
drivers/reset/reset-sky1.c new file +54 -0
+
+     return regmap_update_bits(sky1src->regmap,
+                               signal->offset, signal->bit, value); }
+
+static int sky1_reset_assert(struct reset_controller_dev *rcdev,
+                          unsigned long id) {
+     sky1_reset_set(rcdev, id, true);
+     usleep_range(SKY1_RESET_SLEEP_MIN_US,
+                  SKY1_RESET_SLEEP_MAX_US);
+     return 0;
+}
+
+static int sky1_reset_deassert(struct reset_controller_dev *rcdev,
+                            unsigned long id) {
+     sky1_reset_set(rcdev, id, false);
+     usleep_range(SKY1_RESET_SLEEP_MIN_US,
+                  SKY1_RESET_SLEEP_MAX_US);
+     return 0;
+}
+
+static int sky1_reset(struct reset_controller_dev *rcdev,
+                   unsigned long id)
+{
+     sky1_reset_assert(rcdev, id);
+     sky1_reset_deassert(rcdev, id);
+     return 0;
+}
+
+static int sky1_reset_status(struct reset_controller_dev *rcdev,
+                          unsigned long id) {
+     unsigned int value = 0;
+     struct sky1_src *sky1src = to_sky1_src(rcdev);
+     const struct sky1_src_signal *signal = &sky1src->signals[id];
+
+     regmap_read(sky1src->regmap, signal->offset, &value);
+     return !(value & signal->bit);
+}
+
+static const struct reset_control_ops sky1_src_ops = {
+     .reset    = sky1_reset,
+     .assert   = sky1_reset_assert,
+     .deassert = sky1_reset_deassert,
+     .status   = sky1_reset_status
+};
+
+static int sky1_reset_probe(struct platform_device *pdev) {
+     struct sky1_src *sky1src;
+     struct device *dev = &pdev->dev;
+     const struct sky1_src_variant *variant;
+
+     sky1src = devm_kzalloc(dev, sizeof(*sky1src), GFP_KERNEL);
+     if (!sky1src)
+             return -ENOMEM;
+
Quoted 9 lines

drivers/reset/reset-sky1.c line 336

Quoted 6 lines
drivers/reset/reset-sky1.c new file +6 -0
+     variant = of_device_get_match_data(dev);
+
+     sky1src->regmap = device_node_to_regmap(dev->of_node);
+     if (IS_ERR(sky1src->regmap)) {
+             dev_err(dev, "Unable to get sky1-src regmap");
+             return PTR_ERR(sky1src->regmap);

This can be simplified with dev_err_probe().

The same

If miss any information, please remind me. Thanks

Best Regards
Gary

Quoted 2 lines

regards
Philipp

author maintainer
#9 lore raw

PATCH v9 3/3 arm64: dts: cix: add support for cix sky1 resets

In reply to Gary Yang

There are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/cix/sky1.dtsi +12 -0
index 64b76905cbff..a28b877cced2 100644
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 {
 			status = "disabled";
 		};
 
+		syscon: syscon@4160000 {
+			compatible = "cix,sky1-system-control", "syscon";
+			reg = <0x0 0x4160000 0x0 0x100>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc: pinctrl@4170000 {
 			compatible = "cix,sky1-pinctrl";
 			reg = <0x0 0x04170000 0x0 0x1000>;

@@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 {
 			};
 		};
 
+		s5_syscon: syscon@16000000 {
+			compatible = "cix,sky1-s5-system-control", "syscon";
+			reg = <0x0 0x16000000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc_s5: pinctrl@16007000 {
 			compatible = "cix,sky1-pinctrl-s5";
 			reg = <0x0 0x16007000 0x0 0x1000>;
Signature · 1 line
2.49.0