arm64: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
Subsystems (3)
Chen-Yu Tsai
maintainercover arm64: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
Hi,
This series enables the SPI NAND found on the Avaota A1 in Quad SPI mode. The SPI driver already supports Dual SPI and Quad SPI, but the bindings need to be updated to allow it.
Patch 1 updates the binding to allow Dual SPI and Quad SPI on the newer SoCs. It also allows describing no TX or no RX available.
Patch 2 adds another set of pins for spi0 on the A523 SoC family. This set is used for the SPI NAND on the Avaota A1 board.
Patch 3 enables the SPI NAND found on the board. No partition layout is provided at the moment.
Please have a look.
Thanks
ChenYu
Chen-Yu Tsai (3):
spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs
arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
.../bindings/spi/allwinner,sun6i-a31-spi.yaml | 31 +++++++++++++--- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 35 +++++++++++++++++++ .../dts/allwinner/sun55i-t527-avaota-a1.dts | 15 ++++++++ 3 files changed, 76 insertions(+), 5 deletions(-)
Signature · 1 line
2.47.3
Chen-Yu Tsai
maintainerPATCH 1/3 spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs
Support for Dual SPI and Quad SPI was added to the Linux driver in commit 0605d9fb411f ("spi: sun6i: add quirk for dual and quad SPI modes support") and commit 25453d797d7a ("spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s").
However the binding was never updated to allow these modes. Allow them by adding 2 and 4 to the allowed bus widths for the newer variants.
While at it, also add 0 to the allowed bus widths. This signals that RX or TX is not available, i.e. the MISO or MOSI pin is disconnected.
--- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 31 ++++++++++++++++--- 1 file changed, 26 insertions(+), 5 deletions(-)
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +26 -5
@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Allwinner A31 SPI Controller -allOf: - - $ref: spi-controller.yaml - maintainers: - Chen-Yu Tsai <[email protected]> - Maxime Ripard <[email protected]>
@@ -82,11 +79,35 @@ patternProperties: spi-rx-bus-width: items: - - const: 1 + enum: [0, 1, 2, 4] spi-tx-bus-width: items: - - const: 1 + enum: [0, 1, 2, 4] + +allOf: + - $ref: spi-controller.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-spi + - allwinner,sun55i-a523-spi + then: + patternProperties: + "^.*@[0-9a-f]+": + type: object + + properties: + spi-rx-bus-width: + items: + enum: [0, 1] + + spi-tx-bus-width: + items: + enum: [0, 1] required: - compatible
Signature · 1 line
2.47.3
Re: [PATCH 1/3] spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs
Quoted 6 lines · Chen-Yu Tsai
maintainers:
- Chen-Yu Tsai <[email protected]>
- Maxime Ripard <[email protected]>Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +0
-0@@ -82,11 +79,35 @@ patternProperties: spi-rx-bus-width:
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml patternProperties: · line 88
Quoted 10 lines
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +4
-2items: - - const: 1 + enum: [0, 1, 2, 4] spi-tx-bus-width: items: - - const: 1 + enum: [0, 1, 2, 4] + +allOf:
Please place the allOf after required: block.
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml patternProperties: · line 101
Quoted 13 lines
Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +13
-0+ - $ref: spi-controller.yaml + - if: + not: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-spi + - allwinner,sun55i-a523-spi + then: + patternProperties: + "^.*@[0-9a-f]+": + type: object
type is not needed here, already defined in top-level.
With these two changes:
Best regards,
Krzysztof
Chen-Yu Tsai
maintainerPATCH 2/3 arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
In reply to Chen-Yu TsaiThe Avaota A1 board uses spi0 on the PJ pins to connect a SPI NAND chip.
Add the full set of pins. Even though this board doesn't use CS1, other boards may do so in the future.
--- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)
arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +35 -0
@@ -245,6 +245,13 @@ spi0_pc_pins: spi0-pc-pins { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_pj_pins: spi0-pj-pins { + pins = "PJ21", "PJ22", "PJ23"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_cs0_pc_pin: spi0-cs0-pc-pin { pins = "PC3";
@@ -252,6 +259,13 @@ spi0_cs0_pc_pin: spi0-cs0-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_cs0_pj_pin: spi0-cs0-pj-pin { + pins = "PJ20"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_cs1_pc_pin: spi0-cs1-pc-pin { pins = "PC7";
@@ -259,6 +273,13 @@ spi0_cs1_pc_pin: spi0-cs1-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_cs1_pj_pin: spi0-cs1-pj-pin { + pins = "PJ24"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_hold_pc_pin: spi0-hold-pc-pin { /* conflicts with eMMC D7 */
@@ -267,6 +288,13 @@ spi0_hold_pc_pin: spi0-hold-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_hold_pj_pin: spi0-hold-pj-pin { + pins = "PJ26"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + /omit-if-no-ref/ spi0_wp_pc_pin: spi0-wp-pc-pin { /* conflicts with eMMC D2 */
@@ -275,6 +303,13 @@ spi0_wp_pc_pin: spi0-wp-pc-pin { allwinner,pinmux = <4>; }; + /omit-if-no-ref/ + spi0_wp_pj_pin: spi0-wp-pj-pin { + pins = "PJ25"; + function = "spi0"; + allwinner,pinmux = <5>; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB9", "PB10"; allwinner,pinmux = <2>;
Signature · 1 line
2.47.3
Re: [PATCH 2/3] arm64: dts: allwinner: sun55i-a523: Add pinmux for spi0 on PJ pins
Dne petek, 27. februar 2026 ob 18:51:54 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):
Quoted 7 lines
The Avaota A1 board uses spi0 on the PJ pins to connect a SPI NAND chip.
Add the full set of pins. Even though this board doesn't use CS1, other boards may do so in the future.
Signed-off-by Chen-Yu Tsai <[email protected]>
Best regards,
Jernej
Chen-Yu Tsai
maintainerPATCH 3/3 arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
In reply to Chen-Yu TsaiThe Avaota A1 board has a SPI NAND chip connected to spi0 on the PJ pins with support for QSPI.
Enable spi0 and add a device node for the SPI NAND chip.
--- .../boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +15 -0
@@ -403,6 +403,21 @@ &rtc { assigned-clock-rates = <32768>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pj_pins>, <&spi0_cs0_pj_pin>, + <&spi0_hold_pj_pin>, <&spi0_wp_pj_pin>; + status = "okay"; + + nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>;
Signature · 1 line
2.47.3
Re: [PATCH 3/3] arm64: dts: allwinner: sun55i-t527: avaota-a1: Add SPI NAND
Dne petek, 27. februar 2026 ob 18:51:55 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):
Quoted 6 lines
The Avaota A1 board has a SPI NAND chip connected to spi0 on the PJ pins with support for QSPI.
Enable spi0 and add a device node for the SPI NAND chip.
Signed-off-by Chen-Yu Tsai <[email protected]>
Best regards,
Jernej