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Add support for Cix Sky1 resets

PATCH Applied Gary Yang 4 participants 8 messages Mar 2 – Mar 11

Subsystems (3)
Device tree bindings Reset controller framework Arm/CIX SoC support
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Gary Yang

author maintainer
#0 lore raw

v10 cover Add support for Cix Sky1 resets

Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets

v10 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- rename dt-bindings header file

v9 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver

v8 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- remove "simple-mfd" strings

v7 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix build warning

v6 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-control.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style

v5 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-system-controller.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- refine reset driver
- fix dt-bindings style

v4 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- add syscon
- refine reset driver
- fix dt-bindings style

v3 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- remove syscon

v2 changes:
- Pass dts build check with below commands:
make O=$OUTKNL dt_binding_check
make O=$OUTKNL dt_binding_check DT_SCHEMA_FILES=cix,sky1-rst.yaml make O=$OUTKNL CHECK_DTBS=y W=1 cix/sky1-orion-o6.dtb scripts/checkpatch.pl 000*.patch
- fix dt-bindings style
- refine reset driver

Gary Yang (3):
dt-bindings: soc: cix: document the syscon on Sky1 SoC
reset: add Sky1 soc reset support
arm64: dts: cix: add support for cix sky1 resets

 .../soc/cix/cix,sky1-system-control.yaml      |  42 ++
 arch/arm64/boot/dts/cix/sky1.dtsi             |  12 +
 drivers/reset/Kconfig                         |   7 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-sky1.c                    | 367 ++++++++++++++++++
 .../reset/cix,sky1-s5-system-control.h        | 163 ++++++++
 .../reset/cix,sky1-system-control.h           |  41 ++
 7 files changed, 633 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
 create mode 100644 drivers/reset/reset-sky1.c
 create mode 100644 include/dt-bindings/reset/cix,sky1-s5-system-control.h
 create mode 100644 include/dt-bindings/reset/cix,sky1-system-control.h
Signature · 1 line
2.49.0
author maintainer
#1 lore raw

PATCH v10 1/3 dt-bindings: soc: cix: document the syscon on Sky1 SoC

There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle.

Signed-off-by Gary Yang <[email protected]>
---
 .../soc/cix/cix,sky1-system-control.yaml      |  42 +++++
 .../reset/cix,sky1-s5-system-control.h        | 163 ++++++++++++++++++
 .../reset/cix,sky1-system-control.h           |  41 +++++
 3 files changed, 246 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
 create mode 100644 include/dt-bindings/reset/cix,sky1-s5-system-control.h
 create mode 100644 include/dt-bindings/reset/cix,sky1-system-control.h
Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml new file +42 -0
new file mode 100644
index 000000000000..a01a515222c6
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/cix/cix,sky1-system-control.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cix Sky1 SoC system control register region
+
+maintainers:
+  - Gary Yang <[email protected]>
+
+description:
+  An wide assortment of registers of the system controller on Sky1 SoC,
+  including resets, usb, wakeup sources and so on.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - cix,sky1-system-control
+          - cix,sky1-s5-system-control
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@4160000 {
+      compatible = "cix,sky1-system-control", "syscon";
+      reg = <0x4160000 0x100>;
+      #reset-cells = <1>;
+    };
include/dt-bindings/reset/cix,sky1-s5-system-control.h new file +163 -0

163 lines not on this page · raw message

include/dt-bindings/reset/cix,sky1-system-control.h new file +41 -0

41 lines not on this page · raw message

Signature · 1 line
2.49.0
Reviewed-by on v10 1/3
#2 lore raw

Re: [PATCH v10 1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

Quoted 6 lines · Gary Yang

There are two system control on Cix sky1 Soc. One is located in S0 domain, and the other is located in S5 domain. The system control contains resets, usb typeC and more. At this point, only the reset controller is embedded as usb typeC uses it by phandle.

Signed-off-by Gary Yang <[email protected]>
Quoted 8 lines
---
 .../soc/cix/cix,sky1-system-control.yaml      |  42 +++++
 .../reset/cix,sky1-s5-system-control.h        | 163 ++++++++++++++++++
 .../reset/cix,sky1-system-control.h           |  41 +++++
 3 files changed, 246 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-system-control.yaml
 create mode 100644 include/dt-bindings/reset/cix,sky1-s5-system-control.h
 create mode 100644 include/dt-bindings/reset/cix,sky1-system-control.h
Reviewed-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

author maintainer
#3 lore raw

PATCH v10 2/3 reset: add Sky1 soc reset support

In reply to Gary Yang

Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>
---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-sky1.c | 367 +++++++++++++++++++++++++++++++++++++
 3 files changed, 375 insertions(+)
 create mode 100644 drivers/reset/reset-sky1.c
drivers/reset/Kconfig +7 -0
index 6e5d6deffa7d..3fee381707d8 100644
@@ -291,6 +291,13 @@ config RESET_SIMPLE
 	   - SiFive FU740 SoCs
 	   - Sophgo SoCs
 
+config RESET_SKY1
+	bool "Cix Sky1 reset controller"
+	depends on ARCH_CIX || COMPILE_TEST
+	select REGMAP_MMIO
+	help
+	  This enables the reset controller for Cix Sky1.
+
 config RESET_SOCFPGA
 	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
 	default ARM && ARCH_INTEL_SOCFPGA
drivers/reset/Makefile +1 -0
index 9c3e484dfd81..0d2e1329561d 100644
@@ -37,6 +37,7 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
 obj-$(CONFIG_RESET_RZV2H_USB2PHY) += reset-rzv2h-usb2phy.o
 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
 obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
+obj-$(CONFIG_RESET_SKY1) += reset-sky1.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_SPACEMIT) += reset-spacemit.o
 obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
drivers/reset/reset-sky1.c new file +367 -0

367 lines not on this page · raw message

Signature · 1 line
2.49.0
maintainer Reviewed-by on v10 2/3
#4 lore raw

Re: [PATCH v10 2/3] reset: add Sky1 soc reset support

Quoted 5 lines · Gary Yang

Add support for the resets on Cix's Sky1 SoC.
There are two reset controllers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>
Reviewed-by Philipp Zabel <[email protected]>

regards
Philipp

author maintainer
#5 lore raw

PATCH v10 3/3 arm64: dts: cix: add support for cix sky1 resets

In reply to Gary Yang

There are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/cix/sky1.dtsi +12 -0
index 64b76905cbff..a28b877cced2 100644
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 {
 			status = "disabled";
 		};
 
+		syscon: syscon@4160000 {
+			compatible = "cix,sky1-system-control", "syscon";
+			reg = <0x0 0x4160000 0x0 0x100>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc: pinctrl@4170000 {
 			compatible = "cix,sky1-pinctrl";
 			reg = <0x0 0x04170000 0x0 0x1000>;

@@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 {
 			};
 		};
 
+		s5_syscon: syscon@16000000 {
+			compatible = "cix,sky1-s5-system-control", "syscon";
+			reg = <0x0 0x16000000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc_s5: pinctrl@16007000 {
 			compatible = "cix,sky1-pinctrl-s5";
 			reg = <0x0 0x16007000 0x0 0x1000>;
Signature · 1 line
2.49.0
Applied
#6 lore raw

Re: [PATCH v10 3/3] arm64: dts: cix: add support for cix sky1 resets

Quoted 4 lines · Gary Yang

There are two reset conctrollers on Cix Sky1 Soc. One is located in S0 domain, and the other is located in S5 domain.

Signed-off-by Gary Yang <[email protected]>

Applied, thanks.

Peter

Quoted 37 lines
---
 arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/cix/sky1.dtsi +12 -0
index 64b76905cbff..a28b877cced2 100644
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 {
 			status = "disabled";
 		};
 
+		syscon: syscon@4160000 {
+			compatible = "cix,sky1-system-control", "syscon";
+			reg = <0x0 0x4160000 0x0 0x100>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc: pinctrl@4170000 {
 			compatible = "cix,sky1-pinctrl";
 			reg = <0x0 0x04170000 0x0 0x1000>;

@@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 {
 			};
 		};
 
+		s5_syscon: syscon@16000000 {
+			compatible = "cix,sky1-s5-system-control", "syscon";
+			reg = <0x0 0x16000000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
 		iomuxc_s5: pinctrl@16007000 {
 			compatible = "cix,sky1-pinctrl-s5";
 			reg = <0x0 0x16007000 0x0 0x1000>;
Signature · 1 line
2.49.0
Signature · 2 lines
Best regards,
Peter
maintainer Applied
#7 lore raw
In reply to Gary Yang
Quoted 3 lines · Gary Yang

Patch 1: Add yaml file for Cix Sky1 resets
Patch 2: Add driver codes for Cix Sky1 resets
Patch 3: Add dts nodes for Cix Sky1 resets

Applied patches 1-2 to reset/next, thanks!

[1/3] dt-bindings: soc: cix: document the syscon on Sky1 SoC

      https://git.pengutronix.de/cgit/pza/linux/commit/?id=c76350e7add8
[2/3] reset: add Sky1 soc reset support
      https://git.pengutronix.de/cgit/pza/linux/commit/?id=7cd3ca90d921

regards
Philipp