FAILED: patch "[PATCH] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual" failed to apply to 6.1-stable tree
Subsystems (4)
[email protected]
maintainerThe patch below does not apply to the 6.1-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.1.y
git checkout FETCH_HEAD
git cherry-pick -x d0d727746944096a6681dc6adb5f123fc5aa018d
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026031723-concierge-satisfied-da22@gregkh' --subject-prefix 'PATCH 6.1.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From d0d727746944096a6681dc6adb5f123fc5aa018d Mon Sep 17 00:00:00 2001
From: Luca Ceresoli <[email protected]>
Date: Thu, 26 Feb 2026 17:16:45 +0100
Subject: [PATCH] drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual
LVDS output
Dual LVDS output (available on the SN65DSI84) requires HSYNC_PULSE_WIDTH and HORIZONTAL_BACK_PORCH to be divided by two with respect to the values used for single LVDS output.
While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. It also makes sense intuitively because in dual LVDS output two pixels at a time are output and so the output clock is half of the pixel clock.
Some dual-LVDS panels refuse to show any picture without this fix.
Divide by two HORIZONTAL_FRONT_PORCH too, even though this register is used only for test pattern generation which is not currently implemented by this driver.
[0] https://www.ti.com/tool/DSI-TUNER
drivers/gpu/drm/bridge/ti-sn65dsi83.c +4 -3
@@ -517,6 +517,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, struct drm_atomic_state *state) {struct sn65dsi83 *ctx =bridge_to_sn65dsi83 (bridge); +const unsigned int dual_factor = ctx->lvds_dual_link ?2 :1 ;const struct drm_bridge_state *bridge_state;const struct drm_crtc_state *crtc_state;const struct drm_display_mode *mode;
@@ -653,18 +654,18 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,/* 32 + 1 pixel clock to ensure proper operation */ le16val =cpu_to_le16 (32 +1 );regmap_bulk_write (ctx->regmap,REG_VID_CHA_SYNC_DELAY_LOW , &le16val,2 ); - le16val =cpu_to_le16 (mode->hsync_end - mode->hsync_start); + le16val =cpu_to_le16 ((mode->hsync_end - mode->hsync_start) / dual_factor);regmap_bulk_write (ctx->regmap,REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW , &le16val,2 ); le16val =cpu_to_le16 (mode->vsync_end - mode->vsync_start);regmap_bulk_write (ctx->regmap,REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW , &le16val,2 );regmap_write (ctx->regmap,REG_VID_CHA_HORIZONTAL_BACK_PORCH , - mode->htotal - mode->hsync_end); + (mode->htotal - mode->hsync_end) / dual_factor);regmap_write (ctx->regmap,REG_VID_CHA_VERTICAL_BACK_PORCH , mode->vtotal - mode->vsync_end);regmap_write (ctx->regmap,REG_VID_CHA_HORIZONTAL_FRONT_PORCH , - mode->hsync_start - mode->hdisplay); + (mode->hsync_start - mode->hdisplay) / dual_factor);regmap_write (ctx->regmap,REG_VID_CHA_VERTICAL_FRONT_PORCH , mode->vsync_start - mode->vdisplay);regmap_write (ctx->regmap,REG_VID_CHA_TEST_PATTERN ,0x00 );
Sasha Levin
maintainerPATCH 1/1 drm/bridge: ti-sn65dsi83: halve horizontal syncs for dual LVDS output
From: Luca Ceresoli <[email protected]>
[ Upstream commit d0d727746944096a6681dc6adb5f123fc5aa018d ]
Dual LVDS output (available on the SN65DSI84) requires HSYNC_PULSE_WIDTH and HORIZONTAL_BACK_PORCH to be divided by two with respect to the values used for single LVDS output.
While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. It also makes sense intuitively because in dual LVDS output two pixels at a time are output and so the output clock is half of the pixel clock.
Some dual-LVDS panels refuse to show any picture without this fix.
Divide by two HORIZONTAL_FRONT_PORCH too, even though this register is used only for test pattern generation which is not currently implemented by this driver.
[0] https://www.ti.com/tool/DSI-TUNER
--- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)
drivers/gpu/drm/bridge/ti-sn65dsi83.c +4 -3
@@ -325,6 +325,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, struct drm_bridge_state *old_bridge_state) {struct sn65dsi83 *ctx =bridge_to_sn65dsi83 (bridge); +const unsigned int dual_factor = ctx->lvds_dual_link ?2 :1 ;struct drm_atomic_state *state = old_bridge_state->base.state;const struct drm_bridge_state *bridge_state;const struct drm_crtc_state *crtc_state;
@@ -452,18 +453,18 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,/* 32 + 1 pixel clock to ensure proper operation */ le16val =cpu_to_le16 (32 +1 );regmap_bulk_write (ctx->regmap,REG_VID_CHA_SYNC_DELAY_LOW , &le16val,2 ); - le16val =cpu_to_le16 (mode->hsync_end - mode->hsync_start); + le16val =cpu_to_le16 ((mode->hsync_end - mode->hsync_start) / dual_factor);regmap_bulk_write (ctx->regmap,REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW , &le16val,2 ); le16val =cpu_to_le16 (mode->vsync_end - mode->vsync_start);regmap_bulk_write (ctx->regmap,REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW , &le16val,2 );regmap_write (ctx->regmap,REG_VID_CHA_HORIZONTAL_BACK_PORCH , - mode->htotal - mode->hsync_end); + (mode->htotal - mode->hsync_end) / dual_factor);regmap_write (ctx->regmap,REG_VID_CHA_VERTICAL_BACK_PORCH , mode->vtotal - mode->vsync_end);regmap_write (ctx->regmap,REG_VID_CHA_HORIZONTAL_FRONT_PORCH , - mode->hsync_start - mode->hdisplay); + (mode->hsync_start - mode->hdisplay) / dual_factor);regmap_write (ctx->regmap,REG_VID_CHA_VERTICAL_FRONT_PORCH , mode->vsync_start - mode->vdisplay);regmap_write (ctx->regmap,REG_VID_CHA_TEST_PATTERN ,0x00 );
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2.51.0