Allow ATS to be always on for certain ATS-capable devices

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

Cc [email protected]

Suggested-by Vikram Sethi <[email protected]>

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
  include/linux/pci-ats.h       |  3 +++
  include/uapi/linux/pci_regs.h |  1 +
  drivers/pci/ats.c             | 42 +++++++++++++++++++++++++++++++++++
  3 files changed, 46 insertions(+)

include/linux/pci-ats.h +3 -0

index 75c6c86cf09dc..d14ba727d38b3 100644
@@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);
  void pci_disable_ats(struct pci_dev *dev);
  int pci_ats_queue_depth(struct pci_dev *dev);
  int pci_ats_page_aligned(struct pci_dev *dev);
+bool pci_ats_always_on(struct pci_dev *dev);
  #else /* CONFIG_PCI_ATS */
  static inline bool pci_ats_supported(struct pci_dev *d)
  { return false; }

@@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)
  { return -ENODEV; }
  static inline int pci_ats_page_aligned(struct pci_dev *dev)
  { return 0; }
+static inline bool pci_ats_always_on(struct pci_dev *dev)
+{ return false; }
  #endif /* CONFIG_PCI_ATS */
 
  #ifdef CONFIG_PCI_PRI

include/uapi/linux/pci_regs.h +1 -0

index 14f634ab9350d..6ac45be1008b8 100644
@@ -1349,6 +1349,7 @@
  /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
  #define PCI_DVSEC_CXL_DEVICE				0
  #define  PCI_DVSEC_CXL_CAP				0xA
+#define   PCI_DVSEC_CXL_CACHE_CAPABLE			_BITUL(0)
  #define   PCI_DVSEC_CXL_MEM_CAPABLE			_BITUL(2)
  #define   PCI_DVSEC_CXL_HDM_COUNT			__GENMASK(5, 4)
  #define  PCI_DVSEC_CXL_CTRL				0xC

drivers/pci/ats.c +42 -0

index ec6c8dbdc5e9c..cf262eb6e6890 100644
@@ -205,6 +205,48 @@ int pci_ats_page_aligned(struct pci_dev *pdev)
  	return 0;
  }
 
+/*
+ * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
+ * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
+ * by means of an ATS request on CXL.io.
+ *
+ * In other world, CXL.cache devices cannot access host physical memory without
+ * ATS.
+ */
+static bool pci_cxl_ats_always_on(struct pci_dev *pdev)
+{
+	u16 cap = 0;
+	int offset;
+
+	offset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
+					   PCI_DVSEC_CXL_DEVICE);
+	if (!offset)
+		return false;
+
+	pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap);
+
+	return cap & PCI_DVSEC_CXL_CACHE_CAPABLE;
+}
+
+/**
+ * pci_ats_always_on - Whether the PCI device requires ATS to be always enabled
+ * @pdev: the PCI device
+ *
+ * Returns true, if the PCI device requires ATS for basic functional operation.
+ */
+bool pci_ats_always_on(struct pci_dev *pdev)
+{
+	if (pci_ats_disabled() || !pci_ats_supported(pdev))
+		return false;
+
+	/* A VF inherits its PF's requirement for ATS function */
+	if (pdev->is_virtfn)
+		pdev = pci_physfn(pdev);
+
+	return pci_cxl_ats_always_on(pdev);
+}
+EXPORT_SYMBOL_GPL(pci_ats_always_on);
+
  #ifdef CONFIG_PCI_PRI
  void pci_pri_init(struct pci_dev *pdev)
  {

Quoted 26 lines · Nicolin Chen

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

Quoted 4 lines

Cc [email protected]

Suggested-by Vikram Sethi <[email protected]>

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

Tested the series with a Type 2 CXL device.

Tested-by Nirmoy Das <[email protected]>

Acked-by Nirmoy Das <[email protected]>

Quoted 97 lines

---
  include/linux/pci-ats.h       |  3 +++ include/uapi/linux/pci_regs.h |  1 +
  drivers/pci/ats.c             | 42 +++++++++++++++++++++++++++++++++++

  3 files changed, 46 insertions(+)

include/linux/pci-ats.h +3 -0

index 75c6c86cf09dc..d14ba727d38b3 100644
@@ -12,6 +12,7 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);
   void pci_disable_ats(struct pci_dev *dev);
   int pci_ats_queue_depth(struct pci_dev *dev);
   int pci_ats_page_aligned(struct pci_dev *dev);
+bool pci_ats_always_on(struct pci_dev *dev);
   #else /* CONFIG_PCI_ATS */
   static inline bool pci_ats_supported(struct pci_dev *d)
   { return false; }

@@ -24,6 +25,8 @@ static inline int pci_ats_queue_depth(struct 
 pci_dev *d)
   { return -ENODEV; }
   static inline int pci_ats_page_aligned(struct pci_dev *dev)
   { return 0; }
+static inline bool pci_ats_always_on(struct pci_dev *dev)
+{ return false; }
   #endif /* CONFIG_PCI_ATS */
     #ifdef CONFIG_PCI_PRI

include/uapi/linux/pci_regs.h +1 -0

index 14f634ab9350d..6ac45be1008b8 100644
@@ -1349,6 +1349,7 @@
   /* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */
   #define PCI_DVSEC_CXL_DEVICE                0
   #define  PCI_DVSEC_CXL_CAP                0xA
+#define   PCI_DVSEC_CXL_CACHE_CAPABLE            _BITUL(0)
   #define   PCI_DVSEC_CXL_MEM_CAPABLE            _BITUL(2)
   #define   PCI_DVSEC_CXL_HDM_COUNT            __GENMASK(5, 4)
   #define  PCI_DVSEC_CXL_CTRL                0xC

drivers/pci/ats.c +0 -0

index ec6c8dbdc5e9c..cf262eb6e6890 100644
@@ -205,6 +205,48 @@ int pci_ats_page_aligned(struct pci_dev *pdev)
       return 0;
   }

  +/*
+ * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
+ * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
+ * by means of an ATS request on CXL.io.
+ *
+ * In other world, CXL.cache devices cannot access host physical memory without
+ * ATS.
+ */

drivers/pci/ats.c +17 -0

+static bool pci_cxl_ats_always_on(struct pci_dev *pdev)
+{
+    u16 cap = 0;
+    int offset;
+
+    offset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
+                       PCI_DVSEC_CXL_DEVICE);
+    if (!offset)
+        return false;
+
+    pci_read_config_word(pdev, offset + PCI_DVSEC_CXL_CAP, &cap);
+
+    return cap & PCI_DVSEC_CXL_CACHE_CAPABLE;
+}
+
+/**
+ * pci_ats_always_on - Whether the PCI device requires ATS to be 

always enabled
+ * @pdev: the PCI device
+ *
+ * Returns true, if the PCI device requires ATS for basic functional operation.
+ */

drivers/pci/ats.c +13 -0

+bool pci_ats_always_on(struct pci_dev *pdev)
+{
+    if (pci_ats_disabled() || !pci_ats_supported(pdev))
+        return false;
+
+    /* A VF inherits its PF's requirement for ATS function */
+    if (pdev->is_virtfn)
+        pdev = pci_physfn(pdev);
+
+    return pci_cxl_ats_always_on(pdev);
+}
+EXPORT_SYMBOL_GPL(pci_ats_always_on);
+

  #ifdef CONFIG_PCI_PRI
  void pci_pri_init(struct pci_dev *pdev)
  {

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

Cc [email protected]

Suggested-by Vikram Sethi <[email protected]>

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

It's only called from arm-smmu-v3.c. Is there something unique about SMMU, or will other IOMMUs need something similar?

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

Cc [email protected]

Suggested-by Vikram Sethi <[email protected]>

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
 include/linux/pci-ats.h       |  3 +++
 include/uapi/linux/pci_regs.h |  1 +
 drivers/pci/ats.c             | 42 +++++++++++++++++++++++++++++++++++
 3 files changed, 46 insertions(+)

From: Nicolin Chen <[email protected]>
Sent: Saturday, March 7, 2026 7:41 AM

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a
device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

However, certain PCIe devices require non-PASID ATS on their RID even when
the RID is IOMMU bypassed. Call this "always on".

For instance, the CXL spec notes in "3.2.5.13 Memory Type on CXL.cache":
"To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io."

In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory.

Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on".

Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file.

Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS.

Cc [email protected]

Suggested-by Vikram Sethi <[email protected]>

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

+/*
+ * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
+ * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
+ * by means of an ATS request on CXL.io.
+ *
+ * In other world, CXL.cache devices cannot access host physical memory without
+ * ATS.
+ */

Quoted 8 lines

From: Nicolin Chen <[email protected]>
Sent: Saturday, March 7, 2026 7:41 AM

Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a
device requests a translation service from its associated IOMMU HW running on the channel of a given PASID. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed).

ATS is usually enabled "on demand" when a given PASID on the device is attached to an I/O page table. Above sounds like there will be a software action to enable ATS upon a device translation request.

Quoted 11 lines

+/*
+ * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
+ * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
+ * by means of an ATS request on CXL.io.
+ *
+ * In other world, CXL.cache devices cannot access host physical memory without
+ * ATS.
+ */

s/world/words/

One question regarding VM case: if a device is ats_always_on, while VM somehow doesn't set nested_domain->enable_ats. Should the kernel at least spit a warning, given that it would surely fail the device?

Quoted 3 lines · Nicolin Chen

One question regarding VM case: if a device is ats_always_on, while VM somehow doesn't set nested_domain->enable_ats. Should the kernel at least spit a warning, given that it would surely fail the device?

No, just let break, the resulting failure has to be contained to the VM or the platform is broken..

The HV can't turn on ATS because we it can't know what invalidations to push so not much other choice.

From: Jason Gunthorpe <[email protected]>
Sent: Friday, April 10, 2026 6:53 AM

Quoted 3 lines · Nicolin Chen

One question regarding VM case: if a device is ats_always_on, while VM somehow doesn't set nested_domain->enable_ats. Should the kernel at least spit a warning, given that it would surely fail the device?

No, just let break, the resulting failure has to be contained to the VM or the platform is broken..

The HV can't turn on ATS because we it can't know what invalidations to push so not much other choice.

Quoted 12 lines

From: Jason Gunthorpe <[email protected]>
Sent: Friday, April 10, 2026 6:53 AM

Quoted 3 lines · Nicolin Chen

One question regarding VM case: if a device is ats_always_on, while VM somehow doesn't set nested_domain->enable_ats. Should the kernel at least spit a warning, given that it would surely fail the device?

No, just let break, the resulting failure has to be contained to the VM or the platform is broken..

Quoted 3 lines

The HV can't turn on ATS because we it can't know what invalidations to push so not much other choice.

Taking about in theory - host can append a devtlb invalidation cmd after iotlb invalidation (if vcmdq is not used)?

From: Jason Gunthorpe <[email protected]>
Sent: Friday, April 10, 2026 8:05 PM

Quoted 7 lines · Kevin

Quoted 7 lines

From: Jason Gunthorpe <[email protected]>
Sent: Friday, April 10, 2026 6:53 AM

Quoted 2 lines · Nicolin Chen

One question regarding VM case: if a device is ats_always_on, while VM somehow doesn't set nested_domain->enable_ats. Should the

kernel

Quoted 9 lines

Quoted 8 lines

Quoted 1 line

at least spit a warning, given that it would surely fail the device?

No, just let break, the resulting failure has to be contained to the VM or the platform is broken..

The HV can't turn on ATS because we it can't know what invalidations to push so not much other choice.

Quoted 2 lines

Taking about in theory - host can append a devtlb invalidation cmd after iotlb invalidation (if vcmdq is not used)?

It can't map an ASID to a BDF without shadowing all the STE and CD tables which we don't do for nesting.

Some NVIDIA GPU/NIC devices, although don't implement the CXL config space, they have many CXL-like properties. Call this kind "pre-CXL".

Similar to CXL.cache capaiblity, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases.

Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these device. Then, include it pci_ats_always_on().

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
  drivers/pci/pci.h    |  9 +++++++++
  drivers/pci/ats.c    |  3 ++-
  drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++
  3 files changed, 37 insertions(+), 1 deletion(-)

drivers/pci/pci.h +9 -0

index 13d998fbacce6..13fa71f965900 100644
@@ -1150,6 +1150,15 @@ static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
  }
  #endif
 
+#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS)
+bool pci_dev_specific_ats_always_on(struct pci_dev *dev);
+#else
+static inline bool pci_dev_specific_ats_always_on(struct pci_dev *dev)
+{
+	return false;
+}
+#endif
+
  #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
  int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
  			  struct resource *res);

drivers/pci/ats.c +2 -1

index cf262eb6e6890..e6995b536ad4c 100644
@@ -243,7 +243,8 @@ bool pci_ats_always_on(struct pci_dev *pdev)
  	if (pdev->is_virtfn)
  		pdev = pci_physfn(pdev);
 
-	return pci_cxl_ats_always_on(pdev);
+	return pci_cxl_ats_always_on(pdev) ||
+	       pci_dev_specific_ats_always_on(pdev);
  }
  EXPORT_SYMBOL_GPL(pci_ats_always_on);
 

drivers/pci/quirks.c +26 -0

index 48946cca4be72..21451e62f284e 100644
@@ -5714,6 +5714,32 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
+
+static const struct pci_dev_ats_always_on {
+	u16 vendor;
+	u16 device;
+} pci_dev_ats_always_on[] = {
+	/* NVIDIA GPUs */
+	{ PCI_VENDOR_ID_NVIDIA, 0x2e12, },
+	{ PCI_VENDOR_ID_NVIDIA, 0x2e2a, },
+	{ PCI_VENDOR_ID_NVIDIA, 0x2e2b, },
+	/* NVIDIA CX10 Family NVlink-C2C */
+	{ PCI_VENDOR_ID_MELLANOX, 0x2101, },
+	{ 0 }
+};
+
+/* Some pre-CXL devices require ATS on the RID when it is IOMMU-bypassed */
+bool pci_dev_specific_ats_always_on(struct pci_dev *pdev)
+{
+	const struct pci_dev_ats_always_on *i;
+
+	for (i = pci_dev_ats_always_on; i->vendor; i++) {
+		if (i->vendor == pdev->vendor && i->device == pdev->device)
+			return true;
+	}
+
+	return false;
+}
  #endif /* CONFIG_PCI_ATS */
 
  /* Freescale PCIe doesn't support MSI in RC mode */

Quoted 10 lines · Nicolin Chen

Some NVIDIA GPU/NIC devices, although don't implement the CXL config space, they have many CXL-like properties. Call this kind "pre-CXL".

Similar to CXL.cache capaiblity, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases.

Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these device. Then, include it pci_ats_always_on().

Quoted 2 lines

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

Tested-by Nirmoy Das <[email protected]>

Reviewed-by Nirmoy Das <[email protected]>

Quoted 77 lines

---
  drivers/pci/pci.h    |  9 +++++++++ drivers/pci/ats.c    |  3 ++- drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++

  3 files changed, 37 insertions(+), 1 deletion(-)

drivers/pci/pci.h +8 -0

index 13d998fbacce6..13fa71f965900 100644
@@ -1150,6 +1150,15 @@ static inline int 
 pci_dev_specific_reset(struct pci_dev *dev, bool probe)
   }
   #endif
   +#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_PCI_ATS)
+bool pci_dev_specific_ats_always_on(struct pci_dev *dev);
+#else
+static inline bool pci_dev_specific_ats_always_on(struct pci_dev *dev)
+{
+    return false;
+}
+#endif
+
   #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
   int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,

                struct resource *res);

drivers/pci/ats.c +2 -0

index cf262eb6e6890..e6995b536ad4c 100644
@@ -243,7 +243,8 @@ bool pci_ats_always_on(struct pci_dev *pdev)
       if (pdev->is_virtfn)
           pdev = pci_physfn(pdev);
   -    return pci_cxl_ats_always_on(pdev);
+    return pci_cxl_ats_always_on(pdev) ||
+           pci_dev_specific_ats_always_on(pdev);
   }
   EXPORT_SYMBOL_GPL(pci_ats_always_on);

  diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 48946cca4be72..21451e62f284e 100644

drivers/pci/quirks.c +15 -0

@@ -5714,6 +5714,32 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 
 0x1457, quirk_intel_e2000_no_ats);
   DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats);
   DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats);
   DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats);
+
+static const struct pci_dev_ats_always_on {
+    u16 vendor;
+    u16 device;
+} pci_dev_ats_always_on[] = {
+    /* NVIDIA GPUs */
+    { PCI_VENDOR_ID_NVIDIA, 0x2e12, },
+    { PCI_VENDOR_ID_NVIDIA, 0x2e2a, },
+    { PCI_VENDOR_ID_NVIDIA, 0x2e2b, },
+    /* NVIDIA CX10 Family NVlink-C2C */
+    { PCI_VENDOR_ID_MELLANOX, 0x2101, },
+    { 0 }
+};
+
+/* Some pre-CXL devices require ATS on the RID when it is 

IOMMU-bypassed */

drivers/pci/quirks.c +11 -0

+bool pci_dev_specific_ats_always_on(struct pci_dev *pdev)
+{
+    const struct pci_dev_ats_always_on *i;
+
+    for (i = pci_dev_ats_always_on; i->vendor; i++) {
+        if (i->vendor == pdev->vendor && i->device == pdev->device)
+            return true;
+    }
+
+    return false;
+}

  #endif /* CONFIG_PCI_ATS */
    /* Freescale PCIe doesn't support MSI in RC mode */

Some NVIDIA GPU/NIC devices, although don't implement the CXL config space, they have many CXL-like properties. Call this kind "pre-CXL".

Similar to CXL.cache capaiblity, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases.

Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these device. Then, include it pci_ats_always_on().

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

Some NVIDIA GPU/NIC devices, although don't implement the CXL config space, they have many CXL-like properties. Call this kind "pre-CXL".

Similar to CXL.cache capaiblity, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases.

Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these device. Then, include it pci_ats_always_on().

Suggested-by Jason Gunthorpe <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
 drivers/pci/pci.h    |  9 +++++++++
 drivers/pci/ats.c    |  3 ++-
 drivers/pci/quirks.c | 26 ++++++++++++++++++++++++++
 3 files changed, 37 insertions(+), 1 deletion(-)

From: Nicolin Chen <[email protected]>
Sent: Saturday, March 7, 2026 7:41 AM

Some NVIDIA GPU/NIC devices, although don't implement the CXL config space,
they have many CXL-like properties. Call this kind "pre-CXL".

Similar to CXL.cache capaiblity, these pre-CXL devices also require the ATS

function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on"
v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases.

Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these device. Then, include it pci_ats_always_on().

(quoted diff) +2 -0

+
+/* Some pre-CXL devices require ATS on the RID when it is IOMMU-

bypassed */
+bool pci_dev_specific_ats_always_on(struct pci_dev *pdev)

When a device's default substream attaches to an identity domain, the SMMU driver currently sets the device's STE between two modes:

Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1
Mode 2: Cfg=bypass (EATS is ignored by HW)

When there is an active PASID (non-default substream), mode 1 is used. And when there is no PASID support or no active PASID, mode 2 is used.

The driver will also downgrade an STE from mode 1 to mode 2, when the last active substream becomes inactive.

However, there are PCIe devices that demand ATS to be always on. For these devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2.

Change the driver accordingly:
- always use the mode 1
- never downgrade to mode 2
- allocate and retain a CD table (see note below)

Note that these devices might not support PASID, i.e. doing non-PASID ATS. In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to a !0 value in order to keep the S1DSS field effective. Thus, when a master requires ats_always_on, set its s1cdmax to minimal 1, meaning the CD table will have a dummy entry (SSID=1) that will be never used.

Now, for these device, arm_smmu_cdtab_allocated() will always return true, v.s. false prior to this change. When its default substream is attached to an IDENTITY domain, its first CD is NULL in the table, which is a totally valid case. Thus, add "!master->ats_always_on" to the condition.

Reviewed-by Jonathan Cameron <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |  1 +
  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 72 ++++++++++++++++++---
  2 files changed, 65 insertions(+), 8 deletions(-)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +1 -0

index 3c6d65d36164f..f966d474b61fd 100644
@@ -848,6 +848,7 @@ struct arm_smmu_master {
  	bool				ats_enabled : 1;
  	bool				ste_ats_enabled : 1;
  	bool				stall_enabled;
+	bool				ats_always_on;
  	unsigned int			ssid_bits;
  	unsigned int			iopf_refcount;
  };

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +64 -8

index 4d00d796f0783..ef98e79b4e75d 100644
@@ -1482,8 +1482,11 @@ void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid)
  	if (!arm_smmu_cdtab_allocated(&master->cd_table))
  		return;
  	cdptr = arm_smmu_get_cd_ptr(master, ssid);
-	if (WARN_ON(!cdptr))
+	if (!cdptr) {
+		/* Only ats_always_on allows a NULL CD on default substream */
+		WARN_ON(!master->ats_always_on || ssid);
  		return;
+	}
  	arm_smmu_write_cd_entry(master, ssid, cdptr, &target);
  }
 

@@ -1496,6 +1499,22 @@ static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master)
  	struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table;
 
  	cd_table->s1cdmax = master->ssid_bits;
+
+	/*
+	 * When a device doesn't support PASID (non default SSID), ssid_bits is
+	 * set to 0. This also sets S1CDMAX to 0, which disables the substreams
+	 * and ignores the S1DSS field.
+	 *
+	 * On the other hand, if a device demands ATS to be always on even when
+	 * its default substream is IOMMU bypassed, it has to use EATS that is
+	 * only effective with an STE (CFG=S1translate, S1DSS=Bypass). For such
+	 * use cases, S1CDMAX has to be !0, in order to make use of S1DSS/EATS.
+	 *
+	 * Set S1CDMAX no lower than 1. This would add a dummy substream in the
+	 * CD table but it should never be used by an actual CD.
+	 */
+	if (master->ats_always_on)
+		cd_table->s1cdmax = max_t(u8, cd_table->s1cdmax, 1);
  	max_contexts = 1 << cd_table->s1cdmax;
 
  	if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) ||

@@ -3250,7 +3269,8 @@ static int arm_smmu_blocking_set_dev_pasid(struct iommu_domain *new_domain,
  	 * When the last user of the CD table goes away downgrade the STE back
  	 * to a non-cd_table one, by re-attaching its sid_domain.
  	 */
-	if (!arm_smmu_ssids_in_use(&master->cd_table)) {
+	if (!master->ats_always_on &&
+	    !arm_smmu_ssids_in_use(&master->cd_table)) {
  		struct iommu_domain *sid_domain =
  			iommu_driver_get_domain_for_dev(master->dev);
 

@@ -3274,6 +3294,8 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain,
  		.old_domain = old_domain,
  		.ssid = IOMMU_NO_PASID,
  	};
+	bool ats_always_on = master->ats_always_on &&
+			     s1dss != STRTAB_STE_1_S1DSS_TERMINATE;
 
  	/*
  	 * Do not allow any ASID to be changed while are working on the STE,

@@ -3285,7 +3307,7 @@ static void arm_smmu_attach_dev_ste(struct iommu_domain *domain,
  	 * If the CD table is not in use we can use the provided STE, otherwise
  	 * we use a cdtable STE with the provided S1DSS.
  	 */
-	if (arm_smmu_ssids_in_use(&master->cd_table)) {
+	if (ats_always_on || arm_smmu_ssids_in_use(&master->cd_table)) {
  		/*
  		 * If a CD table has to be present then we need to run with ATS
  		 * on because we have to assume a PASID is using ATS. For

@@ -3581,6 +3603,40 @@ static void arm_smmu_remove_master(struct arm_smmu_master *master)
  	kfree(master->streams);
  }
 
+static int arm_smmu_master_prepare_ats(struct arm_smmu_master *master)
+{
+	bool s1p = master->smmu->features & ARM_SMMU_FEAT_TRANS_S1;
+	unsigned int stu = __ffs(master->smmu->pgsize_bitmap);
+	struct pci_dev *pdev = to_pci_dev(master->dev);
+	int ret;
+
+	if (!arm_smmu_ats_supported(master))
+		return 0;
+
+	if (!pci_ats_always_on(pdev))
+		goto out_prepare;
+
+	/*
+	 * S1DSS is required for ATS to be always on for identity domain cases.
+	 * However, the S1DSS field is ignored if !IDR0_S1P or !IDR1_SSIDSIZE.
+	 */
+	if (!s1p || !master->smmu->ssid_bits) {
+		dev_info_once(master->dev,
+			      "SMMU doesn't support ATS to be always on\n");
+		goto out_prepare;
+	}
+
+	master->ats_always_on = true;
+
+	ret = arm_smmu_alloc_cd_tables(master);
+	if (ret)
+		return ret;
+
+out_prepare:
+	pci_prepare_ats(pdev, stu);
+	return 0;
+}
+
  static struct iommu_device *arm_smmu_probe_device(struct device *dev)
  {
  	int ret;

@@ -3629,14 +3685,14 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev)
  	    smmu->features & ARM_SMMU_FEAT_STALL_FORCE)
  		master->stall_enabled = true;
 
-	if (dev_is_pci(dev)) {
-		unsigned int stu = __ffs(smmu->pgsize_bitmap);
-
-		pci_prepare_ats(to_pci_dev(dev), stu);
-	}
+	ret = arm_smmu_master_prepare_ats(master);
+	if (ret)
+		goto err_disable_pasid;
 
  	return &smmu->iommu;
 
+err_disable_pasid:
+	arm_smmu_disable_pasid(master);
  err_free_master:
  	kfree(master);
  	return ERR_PTR(ret);

When a device's default substream attaches to an identity domain, the SMMU driver currently sets the device's STE between two modes:

Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1
Mode 2: Cfg=bypass (EATS is ignored by HW)

When there is an active PASID (non-default substream), mode 1 is used. And when there is no PASID support or no active PASID, mode 2 is used.

The driver will also downgrade an STE from mode 1 to mode 2, when the last active substream becomes inactive.

However, there are PCIe devices that demand ATS to be always on. For these devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2.

Change the driver accordingly:
- always use the mode 1
- never downgrade to mode 2
- allocate and retain a CD table (see note below)

Note that these devices might not support PASID, i.e. doing non-PASID ATS. In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to a !0 value in order to keep the S1DSS field effective. Thus, when a master requires ats_always_on, set its s1cdmax to minimal 1, meaning the CD table will have a dummy entry (SSID=1) that will be never used.

Now, for these device, arm_smmu_cdtab_allocated() will always return true, v.s. false prior to this change. When its default substream is attached to an IDENTITY domain, its first CD is NULL in the table, which is a totally valid case. Thus, add "!master->ats_always_on" to the condition.

Reviewed-by Jonathan Cameron <[email protected]>

Signed-off-by Nicolin Chen <[email protected]>

---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |  1 +
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 72 ++++++++++++++++++---
 2 files changed, 65 insertions(+), 8 deletions(-)

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c static void arm_smmu_remove_master(struct arm_smmu_master *master) · line 3637

Quoted 13 lines

From: Nicolin Chen <[email protected]>
Sent: Saturday, March 7, 2026 7:41 AM

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +10 -0

+
+	master->ats_always_on = true;
+
+	ret = arm_smmu_alloc_cd_tables(master);
+	if (ret)
+		return ret;
+
+out_prepare:
+	pci_prepare_ats(pdev, stu);
+	return 0;

is there a problem leaving ats_always_on being true while allocating cd tables fails?

From: Jason Gunthorpe <[email protected]>
Sent: Tuesday, March 31, 2026 8:08 PM

Quoted 16 lines · Kevin

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c static void arm_smmu_remove_master(struct arm_smmu_master *master) · line 3637

Quoted 13 lines

From: Nicolin Chen <[email protected]>
Sent: Saturday, March 7, 2026 7:41 AM

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +10 -0

+
+	master->ats_always_on = true;
+
+	ret = arm_smmu_alloc_cd_tables(master);
+	if (ret)
+		return ret;
+
+out_prepare:
+	pci_prepare_ats(pdev, stu);
+	return 0;

is there a problem leaving ats_always_on being true while allocating cd tables fails?

I would expect this error flow unwinds back up to failing device probe?