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Add DeepComputing FML13V05 board dts

PATCH Superseded Sandie Cao 4 participants 16 messages Mar 31 – Apr 1

Subsystems (3)
Device tree bindings RISC-V RISC-V SpacemiT SoC Support

v1 of 5 Superseded Latest is v5 →

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Sandie Cao

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#0 lore raw

cover Add DeepComputing FML13V05 board dts

This series updates Device Tree related files to introduce the FML13V05 board from DeepComputing, which incorporates a Spacemit K3 SoC. This board is designed for use on the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The series is based on riscv-dt-for-next.

sandiecao (2):
dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

 .../devicetree/bindings/riscv/spacemit.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts

base-commit: 4a1739c30fc66a59450c1f78923f94607e786882

Signature · 1 line
2.43.0
author
#1 lore raw

PATCH 1/2 dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

From: sandiecao <[email protected]>

Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>
---
 Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/spacemit.yaml +1 -0
index b958b94a924d..af8030242bdc 100644
@@ -29,6 +29,7 @@ properties:
           - const: spacemit,k1
       - items:
           - enum:
+              - deepcomputing,fml13v05
               - spacemit,k3-pico-itx
           - const: spacemit,k3
Signature · 1 line
2.43.0
maintainer
#2 lore raw

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

Hi Sandie,

Quoted 1 line · Sandie Cao

From: sandiecao <[email protected]>

Can you use more formal format for your name? which, Sandie Cao <[email protected]>

Quoted 6 lines

Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

Signed-off-by sandiecao <[email protected]>

same here

Quoted 19 lines
Reviewed-by Heinrich Schuchardt <[email protected]>
---
 Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/riscv/spacemit.yaml +1 -0
index b958b94a924d..af8030242bdc 100644
@@ -29,6 +29,7 @@ properties:
           - const: spacemit,k1
       - items:
           - enum:
+              - deepcomputing,fml13v05
               - spacemit,k3-pico-itx
           - const: spacemit,k3
Signature · 1 line
2.43.0
Signature · 1 line
Yixun Lan (dlan)
author
#3 lore raw

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

Quoted 8 lines

From: "Yixun Lan"<[email protected]>
Date:  Tue, Mar 31, 2026, 14:03
Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
To: "Sandie Cao"<[email protected]>
Cc: "Conor Dooley"<[email protected]>, "Emil Renner Berthing"<[email protected]>, "Rob Herring"<[email protected]>, "Krzysztof Kozlowski"<[email protected]>, "Paul Walmsley"<[email protected]>, "Palmer Dabbelt"<[email protected]>, "Albert Ou"<[email protected]>, "Heinrich Schuchardt"<[email protected]>, "Troy Mitchell"<[email protected]>, "Michael Opdenacker"<[email protected]>, "Guodong Xu"<[email protected]>, "Hendrik Hamerlinck"<[email protected]>, "Yangyu Chen"<[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]> Hi Sandie,
On 11:45 Tue 31 Mar     , Sandie Cao wrote:

Quoted 4 lines
Quoted 1 line

From: sandiecao <[email protected]>


Can you use more formal format for your name? which, Sandie Cao <[email protected]>

OK. Got it. I will fix it in next version.
Sandie

Quoted 31 lines

Quoted 6 lines


Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

Signed-off-by sandiecao <[email protected]>

same here

Quoted 11 lines
Reviewed-by Heinrich Schuchardt <[email protected]>

---
 Documentation/devicetree/bindings/riscv/spacemit.yaml | 1 +

 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/riscv/spacemit.yaml +0 -0
index b958b94a924d..af8030242bdc 100644
@@ -29,6 +29,7 @@ properties:

           - const: spacemit,k1

Quoted 8 lines

       - items:
           - enum:
+              - deepcomputing,fml13v05
               - spacemit,k3-pico-itx
           - const: spacemit,k3

--
2.43.0


--
Yixun Lan (dlan)

reviewer
#4 lore raw

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

Quoted 6 lines · 曹珊珊
Quoted 6 lines

From: "Yixun Lan"<[email protected]>
Date:  Tue, Mar 31, 2026, 14:03
Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
To: "Sandie Cao"<[email protected]>
Cc: "Conor Dooley"<[email protected]>, "Emil Renner Berthing"<[email protected]>, "Rob Herring"<[email protected]>, "Krzysztof Kozlowski"<[email protected]>, "Paul Walmsley"<[email protected]>, "Palmer Dabbelt"<[email protected]>, "Albert Ou"<[email protected]>, "Heinrich Schuchardt"<[email protected]>, "Troy Mitchell"<[email protected]>, "Michael Opdenacker"<[email protected]>, "Guodong Xu"<[email protected]>, "Hendrik Hamerlinck"<[email protected]>, "Yangyu Chen"<[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>

I'm just confused as to why this appeared in the body.

- Troy

author
#5 lore raw

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

Quoted 8 lines · 曹珊珊
Quoted 6 lines
Quoted 6 lines

From: "Yixun Lan"<[email protected]>
Date:  Tue, Mar 31, 2026, 14:03
Subject:  Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
To: "Sandie Cao"<[email protected]>
Cc: "Conor Dooley"<[email protected]>, "Emil Renner Berthing"<[email protected]>, "Rob Herring"<[email protected]>, "Krzysztof Kozlowski"<[email protected]>, "Paul Walmsley"<[email protected]>, "Palmer Dabbelt"<[email protected]>, "Albert Ou"<[email protected]>, "Heinrich Schuchardt"<[email protected]>, "Troy Mitchell"<[email protected]>, "Michael Opdenacker"<[email protected]>, "Guodong Xu"<[email protected]>, "Hendrik Hamerlinck"<[email protected]>, "Yangyu Chen"<[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>, <[email protected]>

Quoted 4 lines

I'm just confused as to why this appeared in the body.
                          - Troy

This was the format of my email sender.
I correct it now.
Thanks.
Sandie

#6 lore raw

Re: [PATCH v1 1/2] dt-bindings: riscv: spacemit: add deepcomputing,fml13v05

In reply to Sandie Cao
Quoted 7 lines · Sandie Cao

From: sandiecao <[email protected]>

Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

Signed-off-by sandiecao <[email protected]>

Name feels clsoe to login name and even login name has a '.' in the middle, so a bit tricky to judge. Please clarify your name.

Quoted 1 line
Reviewed-by Heinrich Schuchardt <[email protected]>

Is the review coming from some internal sysstems or downstream forks? If so, does the review checks the same things as upstream is expected, including known identity in DCO?

Best regards,
Krzysztof

author
#7 lore raw

PATCH 2/2 riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

In reply to Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
- Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
- Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
- Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>
---
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
arch/riscv/boot/dts/spacemit/Makefile +1 -0
index 7e2b87702571..acb993c452ba 100644
@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +28 -0
new file mode 100644
index 000000000000..2343ae3acc2d
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 DeepComputing (HK) Limited
+ */
+
+#include "k3.dtsi"
+
+/ {
+	model = "DeepComputing FML13V05";
+	compatible = "deepcomputing,fml13v05", "spacemit,k3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	memory@100000000 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
Signature · 1 line
2.43.0
reviewer Reviewed-by on v1 2/2
#8 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Quoted 19 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
- Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
- Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
- Port 3 & 4: USB 3.2 Gen 1

Quoted 5 lines

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>
Reviewed-by Troy Mitchell <[email protected]>
maintainer
#9 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

In reply to Sandie Cao

Hi Sandie,

Quoted 19 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
- Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
- Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
- Port 3 & 4: USB 3.2 Gen 1

Quoted 5 lines

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

should put your own signed-off at the end.

Quoted 22 lines
---
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts
arch/riscv/boot/dts/spacemit/Makefile +1 -0
index 7e2b87702571..acb993c452ba 100644
@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
+dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb
 dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +0 -0
new file mode 100644
index 000000000000..2343ae3acc2d

arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts line 3

Quoted 3 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +3 -0
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 DeepComputing (HK) Limited

should cover current year, which is 2026 now..

Quoted 13 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +13 -0
+ */
+
+#include "k3.dtsi"
+
+/ {
+	model = "DeepComputing FML13V05";
+	compatible = "deepcomputing,fml13v05", "spacemit,k3";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {

arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts line 26

Quoted 10 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +10 -0
+		stdout-path = "serial0";
+	};
+
+	memory@100000000 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {

Can you also add pinctrl data explicitly?

Quoted 4 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +2 -0
+	status = "okay";
+};
Signature · 1 line
2.43.0
Signature · 1 line
Yixun Lan (dlan)
author
#10 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Hi Lan,

Quoted 73 lines

From: "Yixun Lan"<[email protected]>
Hi Sandie,

Quoted 22 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Quoted 2 lines
Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

should put your own signed-off at the end.

Quoted 22 lines

---
 arch/riscv/boot/dts/spacemit/Makefile         |  1 + .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++

 2 files changed, 29 insertions(+)

 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts

arch/riscv/boot/dts/spacemit/Makefile +0 -0
index 7e2b87702571..acb993c452ba 100644
@@ -4,4 +4,5 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb

 dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) += k3-deepcomputing-fml13v05.dtb dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb

arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +0 -0
new file mode 100644
index 000000000000..2343ae3acc2d

arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts line 3

Quoted 3 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +3 -0
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 DeepComputing (HK) Limited

should cover current year, which is 2026 now..

Quoted 16 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +16 -0
+ */
+
+#include "k3.dtsi"
+
+/ {
+        model = "DeepComputing FML13V05";
+        compatible = "deepcomputing,fml13v05", "spacemit,k3";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0";
+        };
+
Quoted 8 lines

arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts line 26

Quoted 7 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +7 -0
+        memory@100000000 {
+                device_type = "memory";
+                reg = <0x1 0x00000000 0x4 0x00000000>;
+        };
+};
+
+&uart0 {

Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. Sandie

Quoted 9 lines

Quoted 4 lines
arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts new file +2 -0
+        status = "okay";
+};

--
2.43.0


--
Yixun Lan (dlan)

reviewer
#11 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Quoted 31 lines · 曹珊珊

Hi Lan,

Quoted 29 lines

From: "Yixun Lan"<[email protected]>
Hi Sandie,

Quoted 25 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

+&uart0 {

Quoted 5 lines
Quoted 1 line

Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. Sandie

I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";

While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties ensures hardware state consistency.

- Troy

author
#12 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Hi Troy,

Quoted 40 lines

From: "Troy Mitchell"<[email protected]> Date:  Wed, Apr 1, 2026, 14:42

Quoted 31 lines · 曹珊珊

Hi Lan,

Quoted 29 lines

From: "Yixun Lan"<[email protected]>
Hi Sandie,

Quoted 25 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

+&uart0 {

Quoted 5 lines
Quoted 1 line

Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. Sandie

Quoted 10 lines

I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";

While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties ensures hardware state consistency.

                                      - Troy

Yes, I know this.
If I add
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_0_cfg>;
Then also need to add
&pinctrl {
        uart0_0_cfg: uart0-0-cfg {
                uart0-0-pins {
                        pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */ <K3_PADCONF(150, 2)>;        /* uart0 rx */

                        bias-pull-up;                        /* normal pull-up */
                        drive-strength = <25>;                /* DS8 */
                };
        };
};
But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream. If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again.
So we just empty it for simple.
Sandie

reviewer
#13 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Quoted 64 lines · 曹珊珊

Hi Troy,

Quoted 40 lines

From: "Troy Mitchell"<[email protected]> Date:  Wed, Apr 1, 2026, 14:42

Quoted 31 lines · 曹珊珊

Hi Lan,

Quoted 29 lines

From: "Yixun Lan"<[email protected]>
Hi Sandie,

Quoted 25 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

+&uart0 {

Quoted 5 lines
Quoted 1 line

Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. Sandie

Quoted 10 lines

I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";

While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties ensures hardware state consistency.

                                      - Troy

Yes, I know this.
If I add
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_0_cfg>;
Then also need to add
&pinctrl {
        uart0_0_cfg: uart0-0-cfg {
                uart0-0-pins {
                        pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */ <K3_PADCONF(150, 2)>;        /* uart0 rx */

Quoted 6 lines

                        bias-pull-up;                        /* normal pull-up */
                        drive-strength = <25>;                /* DS8 */
                };
        };
};
But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.

This line exceeds 100 characters

Quoted 2 lines

If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again. So we just empty it for simple.

No, It looks like your base commit is wrong.
It has been merged here [1] that what you said.

By the way, I noticed that the name in your 'From' header for this reply doesn't match the one in your patch submission. It would be better to keep them consistent to avoid any confusion for the maintainers/reviewers regarding the authorship of the response.

Link:
https://lore.kernel.org/all/[email protected]/ [1]

- Troy

author
#14 lore raw

Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

Hi Troy,

Quoted 74 lines

From: "Troy Mitchell"<[email protected]> Date:  Wed, Apr 1, 2026, 15:55

Quoted 64 lines · 曹珊珊

Hi Troy,

Quoted 40 lines

From: "Troy Mitchell"<[email protected]> Date:  Wed, Apr 1, 2026, 14:42

Quoted 31 lines · 曹珊珊

Hi Lan,

Quoted 29 lines

From: "Yixun Lan"<[email protected]>
Hi Sandie,

Quoted 25 lines · Sandie Cao

From: sandiecao <[email protected]>

The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V SoC.It is a mainboard designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The FML13V05 board features:
- SpacemiT K3 RISC-V SoC
- LPDDR5 16GB or 32GB
- eMMC 32GB ~128GB (Optional)
- UFS 3.1 256G (Optional)
- QSPI Flash
- MicroSD Slot
- PCIe-based Wi-Fi
- 4 USB-C Ports
 - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
 - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
 - Port 3 & 4: USB 3.2 Gen 1

This minimal device tree enables booting into a serial console with UART output.

Signed-off-by sandiecao <[email protected]>
Reviewed-by Heinrich Schuchardt <[email protected]>

+&uart0 {

Quoted 5 lines
Quoted 1 line

Can you also add pinctrl data explicitly?

To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit. Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch. Sandie

Quoted 10 lines

I think you don't understand what Yixun said.
You should add pinctrl properties here like:
pinctrl-0 = xxx;
pinctrl-names = "default";

While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties ensures hardware state consistency.

                                      - Troy

Yes, I know this.
If I add
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_0_cfg>;
Then also need to add
&pinctrl {
        uart0_0_cfg: uart0-0-cfg {
                uart0-0-pins {
                        pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */ <K3_PADCONF(150, 2)>;        /* uart0 rx */

Quoted 6 lines

                        bias-pull-up;                        /* normal pull-up */
                        drive-strength = <25>;                /* DS8 */
                };
        };
};
But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.

Quoted 7 lines

This line exceeds 100 characters

Quoted 2 lines

If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again. So we just empty it for simple.

No, It looks like your base commit is wrong.
It has been merged here [1] that what you said.

Got it. I will use https://github.com/spacemit-com/linux/tree/k1/dt-for-next  to rebase my patch.

Quoted 4 lines

By the way, I noticed that the name in your 'From' header for this reply doesn't match the one in your patch submission. It would be better to keep them consistent to avoid any confusion for the maintainers/reviewers regarding the authorship of the response.

Already fixed it.
Thanks a lot.
Sandie

Quoted 6 lines

Link:
https://lore.kernel.org/all/[email protected]/ [1]

                                    - Troy

author
#15 lore raw

v2 cover Add DeepComputing FML13V05 board dts

In reply to Sandie Cao

This series updates Device Tree related files to introduce the FML13V05 board from DeepComputing, which incorporates a Spacemit K3 SoC. This board is designed for use on the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001.

The series is based on riscv-dt-for-next.

v2:
- Patch 1:
Use formal format user name.
- Patch 2:
Use formal format user name.
Add Reviewed-by from Troy Mitchell.

Link to v1: https://lore.kernel.org/all/[email protected]/

Sandie Cao (2):
dt-bindings: riscv: spacemit: add deepcomputing,fml13v05
riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

 .../devicetree/bindings/riscv/spacemit.yaml   |  1 +
 arch/riscv/boot/dts/spacemit/Makefile         |  1 +
 .../spacemit/k3-deepcomputing-fml13v05.dts    | 28 +++++++++++++++++++
 3 files changed, 30 insertions(+)
 create mode 100644 arch/riscv/boot/dts/spacemit/k3-deepcomputing-fml13v05.dts

base-commit: 4a1739c30fc66a59450c1f78923f94607e786882

Signature · 1 line
2.43.0