Conor Dooley (3):
riscv: dts: microchip: add tsu clock to macb on pic64gx
riscv: dts: microchip: update pic64gx gpio interrupts to better match
the SoC
riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically

 .../dts/microchip/pic64gx-curiosity-kit.dts   | 63 +++++++++++--------
 arch/riscv/boot/dts/microchip/pic64gx.dtsi    | 40 +++++++++---
 2 files changed, 70 insertions(+), 33 deletions(-)

Signature · 1 line

2.53.0

Conor Dooley

author

2026-04-07 15:36 UTC #1 lore raw

PATCH 1/3 riscv: dts: microchip: add tsu clock to macb on pic64gx

From: Conor Dooley <[email protected]>

In increment mode, the tsu clock for the macb is provided separately to the pck, usually the same clock as the reference to the rtc provided by an off-chip oscillator. pclk is 150 MHz typically, and the reference is either 100 MHz or 125 MHz, so having the tsu clock is required for correct rate selection.

Signed-off-by Conor Dooley <[email protected]>

---
 arch/riscv/boot/dts/microchip/pic64gx.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/riscv/boot/dts/microchip/pic64gx.dtsi +4 -4

index c164d7bc270a2..e9ec376b1776b 100644
@@ -459,8 +459,8 @@ mac0: ethernet@20110000 {
 			interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 			/* Filled in by a bootloader */
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+			clock-names = "pclk", "hclk", "tsu_clk";
 			resets = <&mss_top_sysreg CLK_MAC0>;
 			status = "disabled";
 		};

@@ -475,8 +475,8 @@ mac1: ethernet@20112000 {
 			interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 			/* Filled in by a bootloader */
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+			clock-names = "pclk", "hclk", "tsu_clk";
 			resets = <&mss_top_sysreg CLK_MAC1>;
 			status = "disabled";
 		};

Signature · 1 line

2.53.0

Conor Dooley

author

2026-04-07 15:36 UTC #2 lore raw

PATCH 2/3 riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Just like PolarFire SoC, the same issues with GPIO interrupts exist in the pic64gx, due to their similarity. Yoinking from the commit message for the same change for PolarFire SoC:

There are 3 GPIO controllers on this SoC, of which:
- GPIO controller 0 has 14 GPIOs
- GPIO controller 1 has 24 GPIOs
- GPIO controller 2 has 32 GPIOs

All GPIOs are capable of generating interrupts, for a total of 70. There are only 41 IRQs available however, so a configurable mux is used to ensure all GPIOs can be used for interrupt generation.
38 of the 41 interrupts are in what the documentation calls "direct mode", as they provide an exclusive connection from a GPIO to the PLIC. The 3 remaining interrupts are used to mux the interrupts which do not have a exclusive connection, one for each GPIO controller.

The mux was overlooked when the bindings and driver were originally written for the GPIO controllers on Polarfire SoC, and the interrupts property in the GPIO nodes used to try and convey what the mapping was. Instead, the mux should be a device in its own right, and the GPIO controllers should be connected to it, rather than to the PLIC. Now that a binding exists for that mux, fix the inaccurate description of the interrupt controller hierarchy.

Signed-off-by Conor Dooley <[email protected]>

---
 .../dts/microchip/pic64gx-curiosity-kit.dts   | 47 ++++++++++++-------
 arch/riscv/boot/dts/microchip/pic64gx.dtsi    | 32 +++++++++++--
 2 files changed, 58 insertions(+), 21 deletions(-)

arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +29 ~~-18~~

index 2f2ccd77af30a..ed3ff03f3b11b 100644
@@ -63,10 +63,6 @@ hss: hss-buffer@bfc00000 {
 };
 
 &gpio0 {
-	interrupts = <13>, <14>, <15>, <16>,
-		     <17>, <18>, <19>, <20>,
-		     <21>, <22>, <23>, <24>,
-		     <25>, <26>;
 	status ="okay";
 	gpio-line-names =
 		"", "", "", "", "", "", "", "",

@@ -74,12 +70,6 @@ &gpio0 {
 };
 
 &gpio1 {
-	interrupts = <27>, <28>, <29>, <30>,
-		     <31>, <32>, <33>, <34>,
-		     <35>, <36>, <37>, <38>,
-		     <39>, <40>, <41>, <42>,
-		     <43>, <44>, <45>, <46>,
-		     <47>, <48>, <49>, <50>;
 	status ="okay";
 	gpio-line-names =
 		"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",

@@ -88,14 +78,6 @@ &gpio1 {
 };
 
 &gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
 		    <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;

@@ -107,6 +89,35 @@ &gpio2 {
 		"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
 };
 
+&irqmux {
+	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
+			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
+			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
+			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
+			<12 &plic 25>, <13 &plic 26>,
+
+			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
+			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
+			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
+			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
+			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
+			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
+			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
+			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
+
+			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
+			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
+			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
+			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
+			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
+			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
+			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
+			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
+			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
+			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
+			<94 &plic 53>, <95 &plic 53>;
+};
+
 &mac0 {
 	status = "okay";
 	phy-mode = "sgmii";

arch/riscv/boot/dts/microchip/pic64gx.dtsi +29 -3

index e9ec376b1776b..5cf3e3de0e067 100644
@@ -295,6 +295,14 @@ mss_top_sysreg: syscon@20002000 {
 			#size-cells = <1>;
 			#reset-cells = <1>;
 
+			irqmux: interrupt-controller@54 {
+				compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux";
+				reg = <0x54 0x4>;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0x7f>;
+			};
+
 			iomux0: pinctrl@200 {
 				compatible = "microchip,pic64gx-pinctrl-iomux0",
 					     "microchip,mpfs-pinctrl-iomux0";

@@ -484,9 +492,13 @@ mac1: ethernet@20112000 {
 		gpio0: gpio@20120000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20120000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <0>, <1>, <2>, <3>,
+				     <4>, <5>, <6>, <7>,
+				     <8>, <9>, <10>, <11>,
+				     <12>, <13>;
 			clocks = <&clkcfg CLK_GPIO0>;
 			gpio-controller;
 			#gpio-cells = <2>;

@@ -497,9 +509,15 @@ gpio0: gpio@20120000 {
 		gpio1: gpio@20121000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20121000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <32>, <33>, <34>, <35>,
+				     <36>, <37>, <38>, <39>,
+				     <40>, <41>, <42>, <43>,
+				     <44>, <45>, <46>, <47>,
+				     <48>, <49>, <50>, <51>,
+				     <52>, <53>, <54>, <55>;
 			clocks = <&clkcfg CLK_GPIO1>;
 			gpio-controller;
 			#gpio-cells = <2>;

@@ -510,9 +528,17 @@ gpio1: gpio@20121000 {
 		gpio2: gpio@20122000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20122000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <64>, <65>, <66>, <67>,
+				     <68>, <69>, <70>, <71>,
+				     <72>, <73>, <74>, <75>,
+				     <76>, <77>, <78>, <79>,
+				     <80>, <81>, <82>, <83>,
+				     <84>, <85>, <86>, <87>,
+				     <88>, <89>, <90>, <91>,
+				     <92>, <93>, <94>, <95>;
 			clocks = <&clkcfg CLK_GPIO2>;
 			gpio-controller;
 			#gpio-cells = <2>;

Signature · 1 line

2.53.0

Conor Dooley

author

2026-04-07 15:36 UTC #3 lore raw

PATCH 3/3 riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

The i2c nodes are out of place, sort them where they should be.

Signed-off-by Conor Dooley <[email protected]>

---
 .../boot/dts/microchip/pic64gx-curiosity-kit.dts | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts +8 -8

index ed3ff03f3b11b..ef5bff3093fc3 100644
@@ -89,6 +89,14 @@ &gpio2 {
 		"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
 };
 
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
 &irqmux {
 	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
 			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,

@@ -134,14 +142,6 @@ &mbox {
 	status = "okay";
 };
 
-&i2c0 {
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
 &mmc {
 	bus-width = <4>;
 	disable-wp;

Signature · 1 line

2.53.0

Conor Dooley

author Applied

2026-04-08 17:04 UTC #4 lore raw

In reply to Conor Dooley

From: Conor Dooley <[email protected]>

Quoted 14 lines · Conor Dooley

From: Conor Dooley <[email protected]>
CC Conor Dooley <[email protected]>
CC Daire McNamara <[email protected]>
CC Rob Herring <[email protected]>
CC Krzysztof Kozlowski <[email protected]>
CC Paul Walmsley <[email protected]>
CC Palmer Dabbelt <[email protected]>
CC Albert Ou <[email protected]>
CC Alexandre Ghiti <[email protected]>
CC [email protected]
CC [email protected]
CC [email protected]

Quoted 1 line

[...]

Applied to riscv-dt-for-next, thanks!

[1/3] riscv: dts: microchip: add tsu clock to macb on pic64gx

      https://git.kernel.org/conor/c/89991efc78d7
[2/3] riscv: dts: microchip: update pic64gx gpio interrupts to better match the SoC
      https://git.kernel.org/conor/c/53c013c3b27b
[3/3] riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically
      https://git.kernel.org/conor/c/ae488e2669f3

Thanks,
Conor.