Add Efinix FPGA configuration support
Subsystems (2)
v7 cover Add Efinix FPGA configuration support
From: Ian Dannapel <[email protected]>
Hi all,
This is v7 of the series adding support for programming Efinix FPGAs over SPI using the fpga-mgr subsystem.
The series adds DT bindings for the Efinix SPI configuration interface and a new FPGA manager driver implementing passive SPI configuration.
Testing:
- Verified on a custom board with an Efinix Trion T13 FPGA
- Tested full bitstream configuration over SPI at 25 MHz
Changes since v6:
dt-bindings: fpga: Add Efinix SPI programming bindings
- Require spi-cpha and spi-cpol in the binding to match the driver’s probe-time requirement
- Dropped review tag
fpga-mgr: Add Efinix SPI programming driver
- moved Makefile entry to the end of the FPGA manager section
- moved "keep asserted CS" comment to first appeareance
- removed unnecessary variable struct device *dev = &mgr->dev; in fpga mgr callbacks
- trimmed unused spi_device_id's
Ian Dannapel (3):
dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.
dt-bindings: fpga: Add Efinix SPI programming bindings
fpga-mgr: Add Efinix SPI programming driver
.../bindings/fpga/efinix,trion-config.yaml | 98 +++++++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 260 ++++++++++++++++++ 5 files changed, 368 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml create mode 100644 drivers/fpga/efinix-spi.c
Signature · 1 line
2.43.0
PATCH v7 1/3 dt-bindings: vendor-prefix: Add prefix for Efinix, Inc.
From: Ian Dannapel <[email protected]>
Add entry for Efinix, Inc. (https://www.efinixinc.com/)
--- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/vendor-prefixes.yaml +2 -0
@@ -485,6 +485,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^efinix,.*": + description: Efinix, Inc. "^egnite,.*": description: egnite GmbH "^einfochips,.*":
Signature · 1 line
2.43.0
PATCH v7 2/3 dt-bindings: fpga: Add Efinix SPI programming bindings
In reply to [email protected]From: Ian Dannapel <[email protected]>
Add device tree bindings documentation for configuring Efinix FPGA using serial SPI passive programming mode.
--- .../bindings/fpga/efinix,trion-config.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml
Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml new file +98 -0
@@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel <[email protected]> + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams + through "SPI Passive Mode". + Additional pin hogs for bus width configuration should be set + elsewhere, if necessary. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - efinix,titanium-config + - efinix,topaz-config + - const: efinix,trion-config + - const: efinix,trion-config + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - spi-cpha + - spi-cpol + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,titanium-config", "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +...
Signature · 1 line
2.43.0
Re: [PATCH v7 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
Quoted 6 lines · On Thu, Apr 16, 2026 at 04:42:35PM +0200, [email protected] wrote:
From: Ian Dannapel <[email protected]>
Add device tree bindings documentation for configuring Efinix FPGA using serial SPI passive programming mode.
Signed-off-by Ian Dannapel <[email protected]>
pw-bot: not-applicable
PATCH v7 3/3 fpga-mgr: Add Efinix SPI programming driver
In reply to [email protected]From: Ian Dannapel <[email protected]>
Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs.
Efinix passive SPI configuration requires chip select to remain asserted from reset until the complete bitstream and trailing idle clocks have been transferred, so the driver keeps CS active with cs_change and locks the SPI bus for the duration of configuration.
--- drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 260 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c
drivers/fpga/Kconfig +7 -0
@@ -288,6 +288,13 @@ config FPGA_MGR_LATTICE_SYSCONFIG_SPI FPGA manager driver support for Lattice FPGAs programming over slave SPI sysCONFIG interface. +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI" + depends on SPI + help + FPGA manager driver support for Efinix FPGAs configuration over SPI + (passive mode only). + source "drivers/fpga/tests/Kconfig" endif # FPGA
drivers/fpga/Makefile +1 -0
@@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-spi.o # FPGA Secure Update Drivers obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) += intel-m10-bmc-sec-update.o
drivers/fpga/efinix-spi.c new file +260 -0
260 lines not on this page · raw message
Signature · 1 line
2.43.0
Re: [PATCH v7 3/3] fpga-mgr: Add Efinix SPI programming driver
Quoted 11 lines · On Thu, Apr 16, 2026 at 04:42:36PM +0200, [email protected] wrote:
From: Ian Dannapel <[email protected]>
Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs.
Efinix passive SPI configuration requires chip select to remain asserted from reset until the complete bitstream and trailing idle clocks have been transferred, so the driver keeps CS active with
cs_changeand locks the SPI bus for the duration of configuration.Signed-off-by Ian Dannapel <[email protected]>
I applied this series to for-next. Thanks.