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wifi: rtw89: update hardware settings to fix interoperability

PATCH In review Ping-Ke Shih 1 participant 5 messages Apr 24 – Apr 29 Realtek wireless driver (rtw89)

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Ping-Ke Shih

author maintainer
#0 lore raw

cover wifi: rtw89: update hardware settings to fix interoperability

First is to clear CLK ready bit to prevent unstable for certain platforms. The second one is to fix low throughput problem in AP mode. The last one is related beamforming that CSI can't reply on 160MHz bandwidth for WiFi 6 chips.

Dian-Syuan Yang (2):
wifi: rtw89: disable HTC field in AP mode
wifi: rtw89: disable CSI STBC for VHT 160MHz

Ping-Ke Shih (1):
wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE

 drivers/net/wireless/realtek/rtw89/core.c   |  4 ++++
 drivers/net/wireless/realtek/rtw89/mac_be.c |  4 ++++
 drivers/net/wireless/realtek/rtw89/pci.h    |  2 ++
 drivers/net/wireless/realtek/rtw89/pci_be.c | 12 ++++++++++++
 4 files changed, 22 insertions(+)

base-commit: fa489a77e3267e05df95db96ba98e141ec07cbd9

Signature · 1 line
2.25.1
author maintainer
#1 lore raw

PATCH 1/3 wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE

The bit is to wait for CLK ready when entering PCIE L1SS. However, a certain host might not enable CLK for a situation, causing device state stuck and trigger PCIE SER. Unset this bit as default like earlier chips.

Signed-off-by Ping-Ke Shih <[email protected]>
---
 drivers/net/wireless/realtek/rtw89/pci.h    |  2 ++
 drivers/net/wireless/realtek/rtw89/pci_be.c | 12 ++++++++++++
 2 files changed, 14 insertions(+)
drivers/net/wireless/realtek/rtw89/pci.h +2 -0
index e7da37b9da7d..d0d1e2b99698 100644
@@ -33,6 +33,8 @@
 #define RAC_REG_REV2			0x1B
 #define BAC_CMU_EN_DLY_MASK		GENMASK(15, 12)
 #define PCIE_DPHY_DLY_25US		0x1
+#define RAC_ANA14			0x14
+#define EIEOS_L1SS_WAIT_CLKRDY		BIT(2)
 #define RAC_ANA19			0x19
 #define B_PCIE_BIT_RD_SEL		BIT(2)
 #define RAC_REG_FLD_0			0x1D
drivers/net/wireless/realtek/rtw89/pci_be.c +12 -0
index dfffec1ff3c7..473d491eb3f4 100644
@@ -83,6 +83,17 @@ static void _patch_pcie_power_wake_be(struct rtw89_dev *rtwdev, bool power_up)
 		rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, BIT_WAKE_CTRL_V1);
 }
 
+static void _patch_pre_init_be(struct rtw89_dev *rtwdev)
+{
+	struct rtw89_hal *hal = &rtwdev->hal;
+
+	if (!(rtwdev->chip->chip_id == RTL8922D && hal->cid == RTL8922D_CID7090))
+		return;
+
+	rtw89_write16_clr(rtwdev, R_RAC_DIRECT_OFFSET_BE_LANE0_G2 +
+				  RAC_ANA14 * RAC_MULT, EIEOS_L1SS_WAIT_CLKRDY);
+}
+
 static void rtw89_pci_set_io_rcy_be(struct rtw89_dev *rtwdev)
 {
 	const struct rtw89_pci_info *info = rtwdev->pci_info;

@@ -475,6 +486,7 @@ static int rtw89_pci_ops_mac_pre_init_be(struct rtw89_dev *rtwdev)
 
 	rtw89_pci_set_io_rcy_be(rtwdev);
 	_patch_pcie_power_wake_be(rtwdev, true);
+	_patch_pre_init_be(rtwdev);
 	rtw89_pci_ctrl_wpdma_pcie_be(rtwdev, false);
 	rtw89_pci_ctrl_trxdma_pcie_be(rtwdev, MAC_AX_PCIE_DISABLE,
 				      MAC_AX_PCIE_DISABLE, MAC_AX_PCIE_DISABLE);
Signature · 1 line
2.25.1
author maintainer
#2 lore raw

Re: [PATCH rtw-next 1/3] wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE

Quoted 5 lines · Ping-Ke Shih

The bit is to wait for CLK ready when entering PCIE L1SS. However, a certain host might not enable CLK for a situation, causing device state stuck and trigger PCIE SER. Unset this bit as default like earlier chips.

Signed-off-by Ping-Ke Shih <[email protected]>

3 patch(es) applied to rtw-next branch of rtw.git, thanks.

329e9fff98f8 wifi: rtw89: pci: no need to wait CLK ready for RTL8922DE 1e53b826d5f8 wifi: rtw89: disable HTC field in AP mode d1fba5522868 wifi: rtw89: disable CSI STBC for VHT 160MHz

---
https://github.com/pkshih/rtw.git

author maintainer
#3 lore raw

PATCH 2/3 wifi: rtw89: disable HTC field in AP mode

In reply to Ping-Ke Shih

From: Dian-Syuan Yang <[email protected]>

Disable HE QoS HTC field when operating in AP mode to resolve interoperability issues with some stations.

Signed-off-by Dian-Syuan Yang <[email protected]>
Signed-off-by Ping-Ke Shih <[email protected]>
---
 drivers/net/wireless/realtek/rtw89/core.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/net/wireless/realtek/rtw89/core.c +4 -0
index 70feab97dccb..ca3f8e356434 100644
@@ -931,6 +931,7 @@ __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
 				 enum btc_pkt_type pkt_type)
 {
 	struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
+	struct ieee80211_vif *vif = tx_req->vif;
 	struct sk_buff *skb = tx_req->skb;
 	struct ieee80211_hdr *hdr = (void *)skb->data;
 	struct ieee80211_link_sta *link_sta;

@@ -962,6 +963,9 @@ __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
 	if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
 		return false;
 
+	if (vif->type == NL80211_IFTYPE_AP)
+		return false;
+
 	return true;
 }
Signature · 1 line
2.25.1
author maintainer
#4 lore raw

PATCH 3/3 wifi: rtw89: disable CSI STBC for VHT 160MHz

In reply to Ping-Ke Shih

From: Dian-Syuan Yang <[email protected]>

Fix interoperability problem where CSI feedback with STBC enabled at VHT 160MHz BW cannot be properly decoded by certain APs, causing CSI reports to be rejected. This problem is specific to Wi-Fi 7 chips, as Wi-Fi 6 defaults to 20MHz CSI BW. Therefore, disable STBC encoding for CSI transmission in VHT 160MHz mode to ensure CSI feedback is accepted by these APs and maintain smooth throughput.

Signed-off-by Dian-Syuan Yang <[email protected]>
Signed-off-by Ping-Ke Shih <[email protected]>
---
 drivers/net/wireless/realtek/rtw89/mac_be.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/net/wireless/realtek/rtw89/mac_be.c +4 -0
index 39a28fd27412..4d61313a2a84 100644
@@ -2750,6 +2750,10 @@ static int rtw89_mac_set_csi_para_reg_be(struct rtw89_dev *rtwdev,
 		sound_dim = min(sound_dim, t);
 	}
 
+	/* Disable stbc_en in VHT 160MHz to avoid IOT issues with certain APs */
+	if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ)
+		stbc_en = 0;
+
 	nc = min(nc, sound_dim);
 	nr = min(nr, sound_dim);
Signature · 1 line
2.25.1