microchip core-qspi gpio-cs fixes + cleanup
Subsystems (4)
v2 cover microchip core-qspi gpio-cs fixes + cleanup
From: Conor Dooley <[email protected]>
Hey Mark,
v2 here drops 2 of the cleanup patches, but keeps one that conflicted with the changes made in the fixes.
Rebased as you requested.
Cheers,
Conor.
Conor Dooley (3):
spi: microchip-core-qspi: control built-in cs manually
spi: microchip-core-qspi: don't attempt to transmit during emulated
read-only dual/quad operations
spi: microchip-core-qspi: remove some inline markings
drivers/spi/spi-microchip-core-qspi.c | 102 +++++++++++++++++++++----- 1 file changed, 82 insertions(+), 20 deletions(-)
Signature · 1 line
2.53.0
PATCH v2 1/3 spi: microchip-core-qspi: control built-in cs manually
From: Conor Dooley <[email protected]>
The coreQSPI IP supports only a single chip select, which is automagically operated by the hardware - set low when the transmit buffer first gets written to and set high when the number of bytes written to the TOTALBYTES field of the FRAMES register have been sent on the bus. Additional devices must use GPIOs for their chip selects. It was reported to me that if there are two devices attached to this QSPI controller that the in-built chip select is set low while linux tries to access the device attached to the GPIO.
This went undetected as the boards that connected multiple devices to the SPI controller all exclusively used GPIOs for chip selects, not relying on the built-in chip select at all. It turns out that this was because the built-in chip select, when controlled automagically, is set low when active and high when inactive, thereby ruling out its use for active-high devices or devices that need to transmit with the chip select disabled.
Modify the driver so that it controls chip select directly, retaining the behaviour for mem_ops of setting the chip select active for the entire duration of the transfer in the exec_op callback. For regular transfers, implement the set_cs callback for the core to use.
As part of this, the existing setup callback, mchp_coreqspi_setup_op(), is removed. Modifying the CLKIDLE field is not safe to do during operation when there are multiple devices, so this code is removed entirely. Setting the MASTER and ENABLE fields is something that can be done once at probe, it doesn't need to be re-run for each device. Instead the new setup callback sets the built-in chip select to its inactive state for active-low devices, as the reset value of the chip select in software controlled mode is low.
--- drivers/spi/spi-microchip-core-qspi.c | 82 ++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 15 deletions(-)
drivers/spi/spi-microchip-core-qspi.c +67 -15
@@ -74,6 +74,13 @@#define STATUS_FLAGSX4 BIT(8)#define STATUS_MASK GENMASK(8, 0) +/* +* QSPI Direct Access register defines +*/ +#define DIRECT_ACCESS_EN_SSEL BIT(0) +#define DIRECT_ACCESS_OP_SSEL BIT(1) +#define DIRECT_ACCESS_OP_SSEL_SHIFT 1 +#define BYTESUPPER_MASK GENMASK(31, 16)#define BYTESLOWER_MASK GENMASK(15, 0)
@@ -158,6 +165,41 @@ static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mreturn 0 ; } +static void mchp_coreqspi_set_cs (struct spi_device *spi,bool enable) +{ +struct mchp_coreqspi *qspi =spi_controller_get_devdata (spi->controller); +u32 val; + + val =readl (qspi->regs +REG_DIRECT_ACCESS ); + + val &= ~BIT (1 ); +if (spi->mode &SPI_CS_HIGH ) + val |= enable <<DIRECT_ACCESS_OP_SSEL_SHIFT ; +else + val |= !enable <<DIRECT_ACCESS_OP_SSEL_SHIFT ; + +writel (val, qspi->regs +REG_DIRECT_ACCESS ); +} + +static int mchp_coreqspi_setup (struct spi_device *spi) +{ +struct mchp_coreqspi *qspi =spi_controller_get_devdata (spi->controller); +u32 val; + +/* +* Active low devices need to be specifically set to their inactive +* states during probe. +*/ +if (spi->mode &SPI_CS_HIGH ) +return 0 ; + + val =readl (qspi->regs +REG_DIRECT_ACCESS ); + val |=DIRECT_ACCESS_OP_SSEL ; +writel (val, qspi->regs +REG_DIRECT_ACCESS ); + +return 0 ; +} +static inline void mchp_coreqspi_read_op (struct mchp_coreqspi *qspi) {u32 control, data;
@@ -380,19 +422,6 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devireturn 0 ; } -static int mchp_coreqspi_setup_op (struct spi_device *spi_dev) -{ -struct spi_controller *ctlr = spi_dev->controller; -struct mchp_coreqspi *qspi =spi_controller_get_devdata (ctlr); -u32 control =readl_relaxed (qspi->regs +REG_CONTROL ); - - control |= (CONTROL_MASTER |CONTROL_ENABLE ); - control &= ~CONTROL_CLKIDLE ; -writel_relaxed (control, qspi->regs +REG_CONTROL ); - -return 0 ; -} -static inline void mchp_coreqspi_config_op (struct mchp_coreqspi *qspi,const struct spi_mem_op *op) {u32 idle_cycles =0 ;
@@ -483,6 +512,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *oreinit_completion (&qspi->data_completion);mchp_coreqspi_config_op (qspi, op); +mchp_coreqspi_set_cs (mem->spi, true);if (op->cmd.opcode) { qspi->txbuf = &opcode; qspi->rxbuf =NULL ;
@@ -523,6 +553,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o err = -ETIMEDOUT ; error: +mchp_coreqspi_set_cs (mem->spi, false);mutex_unlock (&qspi->op_lock);mchp_coreqspi_disable_ints (qspi);
@@ -686,6 +717,7 @@ static int mchp_coreqspi_probe(struct platform_device *pdev)struct device *dev = &pdev->dev;struct device_node *np = dev->of_node;int ret; +u32 num_cs, val; ctlr =devm_spi_alloc_host (&pdev->dev,sizeof (*qspi));if (!ctlr)
@@ -718,10 +750,18 @@ static int mchp_coreqspi_probe(struct platform_device *pdev)return ret; } +/* +* The IP core only has a single CS, any more have to be provided via +* gpios +*/ +if (of_property_read_u32 (pdev->dev.of_node,"num-cs" , &num_cs)) + num_cs =1 ; + + ctlr->num_chipselect = num_cs; + ctlr->bits_per_word_mask =SPI_BPW_MASK (8 ); ctlr->mem_ops = &mchp_coreqspi_mem_ops; ctlr->mem_caps = &mchp_coreqspi_mem_caps; - ctlr->setup = mchp_coreqspi_setup_op; ctlr->mode_bits =SPI_CPOL |SPI_CPHA |SPI_RX_DUAL |SPI_RX_QUAD |SPI_TX_DUAL |SPI_TX_QUAD ; ctlr->dev.of_node = np;
@@ -729,9 +769,21 @@ static int mchp_coreqspi_probe(struct platform_device *pdev) ctlr->prepare_message = mchp_coreqspi_prepare_message; ctlr->unprepare_message = mchp_coreqspi_unprepare_message; ctlr->transfer_one = mchp_coreqspi_transfer_one; - ctlr->num_chipselect =2 ; + ctlr->setup = mchp_coreqspi_setup; + ctlr->set_cs = mchp_coreqspi_set_cs; ctlr->use_gpio_descriptors = true; + val =readl_relaxed (qspi->regs +REG_CONTROL ); + val |= (CONTROL_MASTER |CONTROL_ENABLE ); +writel_relaxed (val, qspi->regs +REG_CONTROL ); + +/* +* Put cs into software controlled mode +*/ + val =readl_relaxed (qspi->regs +REG_DIRECT_ACCESS ); + val |=DIRECT_ACCESS_EN_SSEL ; +writel (val, qspi->regs +REG_DIRECT_ACCESS ); + ret =spi_register_controller (ctlr);if (ret) return dev_err_probe(&pdev->dev, ret,
Signature · 1 line
2.53.0
Mark Brown
maintainerRe: [PATCH v2 1/3] spi: microchip-core-qspi: control built-in cs manually
drivers/spi/spi-microchip-core-qspi.c static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_m · line 176
Quoted 9 lines · Conor Dooley
drivers/spi/spi-microchip-core-qspi.c +9
-0+static void mchp_coreqspi_set_cs (struct spi_device *spi,bool enable) +{ +struct mchp_coreqspi *qspi =spi_controller_get_devdata (spi->controller); +u32 val; + + val =readl (qspi->regs +REG_DIRECT_ACCESS ); + + val &= ~BIT (1 ); +if (spi->mode &SPI_CS_HIGH )
The core already has handling for SPI_CS_HIGH, you shouldn't need to do it in your driver.
PATCH v2 2/3 spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
The core will deal with reads by creating clock cycles itself, there's no need to generate clock cycles by transmitting garbage data at the driver level. Further, transmitting garbage data just bricks the transfer since QSPI doesn't have a dedicated master-out line like MOSI in regular SPI. I'm not entirely sure if the transfer is bricked because of the garbage data being transmitted on the bus or because the core loses track of whether it is supposed to be sending or receiving data.
--- drivers/spi/spi-microchip-core-qspi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
drivers/spi/spi-microchip-core-qspi.c +11 -1
@@ -693,18 +693,28 @@ static int mchp_coreqspi_transfer_one(struct spi_controller *ctlr, struct spi_de struct spi_transfer *t) {struct mchp_coreqspi *qspi =spi_controller_get_devdata (ctlr); +bool dual_quad = false; qspi->tx_len = t->len; +if (t->tx_nbits ==SPI_NBITS_QUAD || t->rx_nbits ==SPI_NBITS_QUAD || + t->tx_nbits ==SPI_NBITS_DUAL || + t->rx_nbits ==SPI_NBITS_DUAL ) + dual_quad = true; +if (t->tx_buf) qspi->txbuf = (u8 *)t->tx_buf;if (!t->rx_buf) {mchp_coreqspi_write_op (qspi); - }else { + }else if (!dual_quad) { qspi->rxbuf = (u8 *)t->rx_buf; qspi->rx_len = t->len;mchp_coreqspi_write_read_op (qspi); + }else { + qspi->rxbuf = (u8 *)t->rx_buf; + qspi->rx_len = t->len; +mchp_coreqspi_read_op (qspi); }return 0 ;
Signature · 1 line
2.53.0
PATCH v2 3/3 spi: microchip-core-qspi: remove some inline markings
In reply to Conor DooleyFrom: Conor Dooley <[email protected]>
Remove inline markings from a number of functions that are called as part of mem ops callbacks. None of them are either particularly trivial or sensitive to overhead of a function call. Just let the compiler decide what to do with them.
--- drivers/spi/spi-microchip-core-qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/spi/spi-microchip-core-qspi.c +4 -4
@@ -200,7 +200,7 @@ static int mchp_coreqspi_setup(struct spi_device *spi)return 0 ; } -static inline void mchp_coreqspi_read_op (struct mchp_coreqspi *qspi) +static void mchp_coreqspi_read_op (struct mchp_coreqspi *qspi) {u32 control, data;
@@ -236,7 +236,7 @@ static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) } } -static inline void mchp_coreqspi_write_op (struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_op (struct mchp_coreqspi *qspi) {u32 control, data;
@@ -264,7 +264,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) } } -static inline void mchp_coreqspi_write_read_op (struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_read_op (struct mchp_coreqspi *qspi) {u32 control, data;
@@ -422,7 +422,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_devireturn 0 ; } -static inline void mchp_coreqspi_config_op (struct mchp_coreqspi *qspi,const struct spi_mem_op *op) +static void mchp_coreqspi_config_op (struct mchp_coreqspi *qspi,const struct spi_mem_op *op) {u32 idle_cycles =0 ;int total_bytes, cmd_bytes, frames, ctrl;
Signature · 1 line
2.53.0